US20010045902A1 - Skewless differential switching scheme for current-mode digital-to-analog converters - Google Patents
Skewless differential switching scheme for current-mode digital-to-analog converters Download PDFInfo
- Publication number
- US20010045902A1 US20010045902A1 US09/774,443 US77444301A US2001045902A1 US 20010045902 A1 US20010045902 A1 US 20010045902A1 US 77444301 A US77444301 A US 77444301A US 2001045902 A1 US2001045902 A1 US 2001045902A1
- Authority
- US
- United States
- Prior art keywords
- inverter
- transistor
- pull
- coupled
- node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
- H03K17/04106—Modifications for accelerating switching without feedback from the output circuit to the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
Definitions
- This invention generally relates to electronic systems and in particular it relates to differential switching schemes for current-mode digital-to-analog converters (DACs).
- DACs digital-to-analog converters
- Digital-to-analog converters mainly designed for video applications have a very poor spectral purity when used in communication applications such as the transmit portion of wired and/or wireless digital communication systems.
- Delay differences between when a bit turns on and when it turns off results in a shift from the ideal fifty percent duty cycle (square wave) and leads to even-order harmonics in the output spectrum.
- a typical prior art CMOS current-mode DAC switching scheme shown in FIG. 1A, includes transistors 20 and 22 ; current source 24 ; input nodes Q and QB; and output nodes 26 and 28 .
- FIG. 1A includes transistors 20 and 22 ; current source 24 ; input nodes Q and QB; and output nodes 26 and 28 .
- the time skew between Q and QB is of major concern for communication applications.
- the switches (transistors) 20 and 22 are like a differential pair.
- the prior art circuit of FIG. 1 uses PMOS transistors, but the same problems with time skew also exist when NMOS switches and current sources are used.
- the differential switching circuit includes: a first inverter; a first pull-up transistor coupled between the first inverter and a high-side power supply node; a first pull-down transistor coupled between the first inverter and a low-side power supply node; an output node of the first inverter coupled to a control node of the first pull-up transistor and a control node of the first pull-down transistor; a second inverter; a second pull-up transistor coupled between the second inverter and the high-side power supply node; a second pull-down transistor coupled between the second inverter and the low-side power supply node; and an output node of the second inverter coupled to a control node of the second pull-up transistor and a control node of the second pull-down transistor, wherein the first and second inverters are coupled together between the inverters and the pull-up transistors, and between the inverters and the pull-down transistors.
- FIG. 1A is a schematic circuit diagram of a prior art CMOS current mode DAC switching scheme
- FIG. 1B is a schematic circuit diagram of a first prior art circuit for generating complementary signals
- FIG. 1C is a schematic circuit diagram of a second prior art circuit for generating complementary signals
- FIG. 2 is a schematic circuit diagram of a preferred embodiment skewless differential switching circuit
- FIG. 3 is a schematic circuit diagram of a preferred embodiment skewless differential switching circuit with built-in swing-limit
- FIG. 4 is a schematic circuit diagram of a skewless PMOS current mode DAC switching scheme
- FIG. 5 is a schematic circuit diagram of a skewless NMOS current mode DAC switching scheme.
- FIG. 2 A preferred embodiment skewless differential switching circuit is shown in FIG. 2.
- the circuit of FIG. 2 includes NMOS transistors 32 - 37 ; PMOS transistors 40 - 45 ; digital input data D and DB; switch control data Q and QB; clock signal CK; and source voltages V DD and V SS .
- Transistors 35 and 42 form inverter 46 .
- Transistors 37 and 44 form inverter 47 .
- Inverter 46 and transistors 34 and 43 form skewless switching element 48 .
- Inverter 47 and transistors 36 and 45 form skewless switching element 49 .
- Transistors 40 and 41 serve as digital data storage elements. This circuit provides a switching scheme that minimizes the time skew between Q and QB.
- This switching scheme not only gives a minimum possible time-skew, but, also, gives the same rise and fall times. Equal rise and fall times is very essential when a DAC is reconstructing a sine wave. For minimum harmonic distortion, both half-cycles of the sinusoidal waveform need to have the same rise and fall characteristics.
- D and DB are the complementary signals with skew, while Q and QB are their respective final skewless outputs.
- both control signals by design are forced to wait for each other before moving on to control one of the two switches.
- the path of Q to its final level is controlled by QB, while at the same time, Q controls the path of QB to its final voltage level.
- the only way for D to reach the switch is if and only if QB allows Q to do so
- the only way for DB to reach the other switch is if and only if Q allows QB to do so.
- the circuit of FIG. 2 operates as follows.
- the digital data D and DB is allowed to settle and take its final value before clock signal CK goes high and turns on the pass transistors (switches) 32 and 33 .
- NMOS transistors 32 and 33 pass bad ONES (voltage levels not high enough to be detected as a ONE)
- pull up transistors (switches) 40 and 41 are used to restore the voltage level to V DD.
- transistors 20 and 21 form a differential pair, Q and QB do not need to swing to V DD and V SS .
- a diode-connected PMOS transistor 50 is added between V DD and transistor 43
- a diode-connected PMOS transistor 52 is added between V DD and transistor 45 , as shown in the circuit of FIG. 3.
- a diode-connected NMOS transistor 54 is added between V SS and transistor 34
- a diode connected NMOS transistor 56 is added between V SS and transistor 36 , as shown in FIG. 3.
- the skewless differential DAC switch driver is used as shown in FIGS. 4 and 5.
- the circuit of FIG. 4 includes PMOS transistors 60 and 62 ; DAC load resistances 64 and 66 ; switch driver 68 ; and current source 70 .
- the circuit of FIG. 5 includes NMOS transistors 74 and 76 ; DAC load resistances 78 and 80 ; switch driver 82 ; and current source 84 .
- the circuit of FIG. 4 uses PMOS transistors and the circuit of FIG. 5 uses NMOS transistors. D and DB are provided by DAC logic circuitry and are assumed to have settled to their final state.
- the preferred embodiment provides several advantages. Skew reduction is guaranteed by design because Q waits for QB to become valid, while at the same time, QB waits for Q to become valid before allowing either one of them to go to the differential switch. This circuit works well for a wide supply range such as 2.7 to 5.0 volts. Unlike the prior art solution of U.S. Pat. No. 5,689,257, there is no reduction in performance from the additional skew introduced between D and DB by NMOS pass transistors 32 and 33 as they pass a good ZERO, but a bad ONE. If needed, instead of using the simple pull-up PMOS transistors 40 and 41 , a variety of different types of storage elements, such as cross-coupled inverters, can be used. The preferred embodiment is not limited by the mismatches between the two identical cross-coupled inverters used for minimizing the skew in U.S. Pat. No. 5,689,257.
Abstract
A differential switching circuit includes: a first inverter 46; a first pull-up transistor 43 coupled between the first inverter 46 and a high-side power supply node; a first pull-down transistor 34 coupled between the first inverter 46 and a low-side power supply node; an output node of the first inverter 46 coupled to a control node of the first pull-up transistor 43 and a control node of the first pull-down transistor 34; a second inverter 47; a second pull-up transistor 45 coupled between the second inverter 47 and the high-side power supply node; a second pull-down transistor 36 coupled between the second inverter 47 and the low-side power supply node; and an output node of the second inverter 47 coupled to a control node of the second pull-up transistor 45 and a control node of the second pull-down transistor 36, wherein the first and second inverters 46 and 47 are coupled together between the inverters and the pull-up transistors 43 and 45, and between the inverters and the pull-down transistors 34 and 36.
Description
- This invention generally relates to electronic systems and in particular it relates to differential switching schemes for current-mode digital-to-analog converters (DACs).
- Digital-to-analog converters mainly designed for video applications have a very poor spectral purity when used in communication applications such as the transmit portion of wired and/or wireless digital communication systems. Delay differences between when a bit turns on and when it turns off results in a shift from the ideal fifty percent duty cycle (square wave) and leads to even-order harmonics in the output spectrum. For a given delay difference or skew in time (when a bit turns off or on), the higher the output frequency, the more pronounced the distortion. A typical prior art CMOS current-mode DAC switching scheme, shown in FIG. 1A, includes
transistors current source 24; input nodes Q and QB; andoutput nodes - Individual current sources in current mode digital-to-analog converters (DACs) use differential switches to steer current through either one of the two switches. The above mentioned differential switches are controlled by two digital complementary control signals, Q and QB, where, if Q=VDD (power of the highest potential), then QB=VSS (ground or the lowest potential) and vice-versa. Due to the physics of the inverting circuit, there is always some time delay or skew between the original signal and its inverted counterpart. Normally, QB is derived by inverting Q, as shown in FIG. 1B, and thus, there is always some skew present between Q and QB. When current mode DACs are used in frequency domain applications, such as communications systems, the skew between, Q and QB introduces both harmonic and non-harmonic related distortion in the spectrum of the output signal. Hence, the spurious-free dynamic range (SFDR) of the DAC is greatly reduced.
- Some attempts have been made in the prior art to improve the time skew problems described above. One example is U.S. Pat. No. 5,689,257 “Skewless Differential Switch and DAC Employing the Same”, Nov. 18, 1997. In this patent, two
cross-coupled inverters - Generally, and in one form of the invention, the differential switching circuit includes: a first inverter; a first pull-up transistor coupled between the first inverter and a high-side power supply node; a first pull-down transistor coupled between the first inverter and a low-side power supply node; an output node of the first inverter coupled to a control node of the first pull-up transistor and a control node of the first pull-down transistor; a second inverter; a second pull-up transistor coupled between the second inverter and the high-side power supply node; a second pull-down transistor coupled between the second inverter and the low-side power supply node; and an output node of the second inverter coupled to a control node of the second pull-up transistor and a control node of the second pull-down transistor, wherein the first and second inverters are coupled together between the inverters and the pull-up transistors, and between the inverters and the pull-down transistors.
- In the drawings:
- FIG. 1A is a schematic circuit diagram of a prior art CMOS current mode DAC switching scheme;
- FIG. 1B is a schematic circuit diagram of a first prior art circuit for generating complementary signals;
- FIG. 1C is a schematic circuit diagram of a second prior art circuit for generating complementary signals;
- FIG. 2 is a schematic circuit diagram of a preferred embodiment skewless differential switching circuit;
- FIG. 3 is a schematic circuit diagram of a preferred embodiment skewless differential switching circuit with built-in swing-limit;
- FIG. 4 is a schematic circuit diagram of a skewless PMOS current mode DAC switching scheme;
- FIG. 5 is a schematic circuit diagram of a skewless NMOS current mode DAC switching scheme.
- A preferred embodiment skewless differential switching circuit is shown in FIG. 2. The circuit of FIG. 2 includes NMOS transistors32-37; PMOS transistors 40-45; digital input data D and DB; switch control data Q and QB; clock signal CK; and source voltages VDD and VSS. Transistors 35 and 42
form inverter 46.Transistors form inverter 47. Inverter 46 andtransistors skewless switching element 48. Inverter 47 andtransistors skewless switching element 49.Transistors - In the circuit of FIG. 2, D and DB are the complementary signals with skew, while Q and QB are their respective final skewless outputs. By using this skewless differential switching scheme, both control signals by design are forced to wait for each other before moving on to control one of the two switches. In the circuit of FIG. 2, the path of Q to its final level is controlled by QB, while at the same time, Q controls the path of QB to its final voltage level. With the circuit of FIG. 2, the only way for D to reach the switch is if and only if QB allows Q to do so, and the only way for DB to reach the other switch is if and only if Q allows QB to do so. Because Q and QB control each other, the final values of Q and QB, by design, can only be reached simultaneously, leaving no skew between Q and QB. As a result of this, the two complementary signals, Q and QB, are applied simultaneously (without any skew) to the differential switches.
- The circuit of FIG. 2 operates as follows. The digital data D and DB is allowed to settle and take its final value before clock signal CK goes high and turns on the pass transistors (switches)32 and 33. As
NMOS transistors PMOS transistors transistor 33 passes a bad ONE andtransistor 32 passes a good ZERO. Then the good ZERO passed bytransistor 32 turns ontransistor 41 and restores the bad ONE to VDD. - In order to describe the operation of the rest of the circuit of FIG. 2, assume D=1, DB=0, Q=1, and QB=0. A restored D=1 turns on
transistor 35 and turns offtransistor 42. Similarly, DB=0 turns offtransistor 37 and turns ontransistor 44. With Q=0,transistor 36 is on andtransistor 45 is off. With QB=0,transistor 34 is off andtransistor 43 is on. This assures that, for Q=1, QB=0, D=1, and DB=0, Q is at voltage level VDD becausetransistors transistors - When the state of D changes to ZERO from ONE and DB changes to ONE from ZERO, the circuit of FIG. 2 operates as follows. For D=0,
transistor 35 is off andtransistor 42 is on. QB starts moving to a higher voltage. This couples QB to the drain oftransistor 45 and to the source oftransistor 44. Similarly, for DB=1,transistor 37 is on andtransistor 44 is off. Q starts moving to a lower voltage. This couples Q to the drain oftransistor 34 and to the source oftransistor 35. With QB going high,transistor 43 turns off andtransistor 34 turns on. With Q going low,transistor 45 turns on andtransistor 36 turns off. Then Q goes to ZERO becausetransistor 37 is turned on by DB andtransistor 34 is turned on by QB. Similarly, QB goes to ONE becausetransistor 42 is turned on by D andtransistor 45 is turned on by Q. Because the final output is controlled by the complementary input, the circuit of FIG. 2 minimizes skew and provides an improved differential switch driver for a DAC current source as shown in FIG. 1. - Because
transistors 20 and 21, shown in FIG. 1, form a differential pair, Q and QB do not need to swing to VDD and VSS. In order to achieve swing-limit from the differential switching scheme of FIG. 2, a diode-connectedPMOS transistor 50 is added between VDD andtransistor 43, and a diode-connectedPMOS transistor 52 is added between VDD andtransistor 45, as shown in the circuit of FIG. 3. Also, a diode-connectedNMOS transistor 54 is added between VSS andtransistor 34, and a diode connectedNMOS transistor 56 is added between VSS andtransistor 36, as shown in FIG. 3. - The skewless differential DAC switch driver is used as shown in FIGS. 4 and 5. The circuit of FIG. 4 includes
PMOS transistors DAC load resistances switch driver 68; andcurrent source 70. The circuit of FIG. 5 includesNMOS transistors DAC load resistances switch driver 82; andcurrent source 84. The circuit of FIG. 4 uses PMOS transistors and the circuit of FIG. 5 uses NMOS transistors. D and DB are provided by DAC logic circuitry and are assumed to have settled to their final state. - The preferred embodiment provides several advantages. Skew reduction is guaranteed by design because Q waits for QB to become valid, while at the same time, QB waits for Q to become valid before allowing either one of them to go to the differential switch. This circuit works well for a wide supply range such as 2.7 to 5.0 volts. Unlike the prior art solution of U.S. Pat. No. 5,689,257, there is no reduction in performance from the additional skew introduced between D and DB by
NMOS pass transistors PMOS transistors - While this invention has been described with reference to an illustrative embodiment, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.
Claims (10)
1. A differential switching circuit comprising:
a first inverter;
a first pull-up transistor coupled between the first inverter and a high-side power supply node;
a first pull-down transistor coupled between the first inverter and a low-side power supply node;
an output node of the first inverter coupled to a control node of the first pull-up transistor and a control node of the first pull-down transistor;
a second inverter;
a second pull-up transistor coupled between the second inverter and the high-side power supply node;
a second pull-down transistor coupled between the second inverter and the low-side power supply node; and
an output node of the second inverter coupled to a control node of the second pull-up transistor and a control node of the second pull-down transistor, wherein the first and second inverters are coupled together between the inverters and the pull-up transistors, and between the inverters and the pull-down transistors.
2. The circuit of further comprising:
claim 1
a first transfer switch coupled to an input of the first inverter; and
a second transfer switch coupled to an input of the second inverter.
3. The circuit of further comprising:
claim 2
a first storage element coupled to the input of the first inverter; and
a second storage element coupled to the input of the second inverter.
4. The circuit of wherein the first storage element is a first transistor coupled between the input of the first inverter and the high side power supply node; and the second storage element is a second transistor coupled between the input of the second inverter and the high side power supply node.
claim 3
5. The circuit of wherein a control node of the first transistor is coupled to the input of the second inverter; and a control node of the second transistor is coupled to the input of the first inverter.
claim 4
6. The circuit of wherein the first and second transfer switches are transistors.
claim 2
7. The circuit of wherein the first and second transfer switches are NMOS transistors.
claim 2
8. The circuit of further comprising a current mode digital-to-analog converter switching circuit coupled to the output node of the first inverter and the output node of the second inverter.
claim 1
9. The circuit of wherein the converter switching circuit comprises:
claim 8
a current source;
a first transistor coupled to the current source, a control node of the first transistor coupled to the output of the first inverter; and
a second transistor coupled to the current source, a control node of the second transistor coupled to the output of the second inverter.
10. A digital-to-analog converter comprising:
a first inverter;
a first pull-up transistor coupled between the first inverter and a high-side power supply node;
a first pull-down transistor coupled between the first inverter and a low-side power supply node;
an output node of the first inverter coupled to a control node of the first pull-up transistor and a control node of the first pull-down transistor
a second inverter;
a second pull-up transistor coupled between the second inverter and the high-side power supply node;
a second pull-down transistor coupled between the second inverter and the low-side power supply node;
an output node of the second inverter coupled to a control node of the second pull-up transistor and a control node of the second pull-down transistor, wherein the first and second inverters are coupled together between the inverters and the pull-up transistors, and between the inverters and the pull-down transistors; and
a current mode digital-to-analog converter switching circuit coupled to the output node of the first inverter and the output node of the second inverter.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/774,443 US6310569B1 (en) | 2000-02-25 | 2001-01-31 | Skewless differential switching scheme for current-mode digital-to-analog converters |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US18499500P | 2000-02-25 | 2000-02-25 | |
US09/774,443 US6310569B1 (en) | 2000-02-25 | 2001-01-31 | Skewless differential switching scheme for current-mode digital-to-analog converters |
Publications (2)
Publication Number | Publication Date |
---|---|
US6310569B1 US6310569B1 (en) | 2001-10-30 |
US20010045902A1 true US20010045902A1 (en) | 2001-11-29 |
Family
ID=26880679
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/774,443 Expired - Lifetime US6310569B1 (en) | 2000-02-25 | 2001-01-31 | Skewless differential switching scheme for current-mode digital-to-analog converters |
Country Status (1)
Country | Link |
---|---|
US (1) | US6310569B1 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003007059A (en) * | 2001-06-22 | 2003-01-10 | Mitsubishi Electric Corp | Semiconductor memory |
US6931560B1 (en) * | 2001-08-02 | 2005-08-16 | Lsi Logic Corporation | Programmable transmit SCSI equalization |
US7098830B2 (en) * | 2004-04-09 | 2006-08-29 | Texas Instruments Incorporated | Current switching arrangement for D.A.C. reconstruction filtering |
DE102004063198B4 (en) * | 2004-12-23 | 2009-04-30 | Atmel Germany Gmbh | Driver circuit, in particular for laser diodes and method for providing a drive pulse train |
US8324868B2 (en) * | 2007-08-24 | 2012-12-04 | Valence Technology, Inc. | Power source with temperature sensing |
US8928513B1 (en) | 2014-09-18 | 2015-01-06 | IQ-Analog Corporation | Current steering digital-to-analog converter (DAC) switch driver |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5450084A (en) * | 1993-08-12 | 1995-09-12 | Analog Devices, Incorporated | D/A converter with differential switching circuit providing symmetrical switching |
US5689257A (en) | 1996-01-05 | 1997-11-18 | Analog Devices, Inc. | Skewless differential switch and DAC employing the same |
GB2333191A (en) * | 1998-01-08 | 1999-07-14 | Fujitsu Microelectronics Ltd | DAC current switch with reduced crossover noise |
US6031477A (en) * | 1998-05-07 | 2000-02-29 | Analog Devices, Inc. | Differential current switch |
-
2001
- 2001-01-31 US US09/774,443 patent/US6310569B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6310569B1 (en) | 2001-10-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0935345B1 (en) | Differential switching circuitry | |
KR100780758B1 (en) | Reducing jitter in mixed-signal integrated circuit devices | |
US6020768A (en) | CMOS low-voltage comparator | |
US9048864B2 (en) | Digital to analog converter with current steering source for reduced glitch energy error | |
KR0165538B1 (en) | Integrated circuit for signal level converter | |
US5164725A (en) | Digital to analog converter with current sources paired for canceling error sources | |
US5103116A (en) | CMOS single phase registers | |
US6977602B1 (en) | Wide band digital to analog converters and methods, including converters with selectable impulse response | |
EP2965425B1 (en) | Voltage level shifter with a low-latency voltage boost circuit | |
US5600321A (en) | High speed, low power CMOS D/A converter for wave synthesis in network | |
WO2012176250A1 (en) | Differential switch drive circuit and current-steering d/a converter | |
US5517148A (en) | Low current differential level shifter | |
JPH11168359A (en) | High speed clock enable latch circuit | |
US20210005231A1 (en) | Latching sense amplifier | |
JP2006518964A (en) | Signal processing circuit and method | |
US7629910B2 (en) | Methods and apparatus to control current steering digital to analog converters | |
US7629814B2 (en) | Latch circuit and deserializer circuit | |
WO2009073640A1 (en) | Low-noise pecl output driver | |
US6310569B1 (en) | Skewless differential switching scheme for current-mode digital-to-analog converters | |
TWI660585B (en) | Latch circuit | |
US7199742B2 (en) | Digital-to-analog converter and related level shifter thereof | |
US6798251B1 (en) | Differential clock receiver with adjustable output crossing point | |
EP1134894A2 (en) | Improvements in or relating to digital-to-analog converters | |
US6294940B1 (en) | Symmetric clock receiver for differential input signals | |
US10771077B1 (en) | Hybrid return-to-zero voltage-mode DAC driver |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHAUDHRY, IRFAN A.;BELLAOUAR, ABDELLATIF;FARES, MOUNIR;AND OTHERS;REEL/FRAME:011508/0937 Effective date: 20000307 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |