CN112736132A - InP PHEMT epitaxial structure and preparation method thereof - Google Patents

InP PHEMT epitaxial structure and preparation method thereof Download PDF

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CN112736132A
CN112736132A CN202110015630.6A CN202110015630A CN112736132A CN 112736132 A CN112736132 A CN 112736132A CN 202110015630 A CN202110015630 A CN 202110015630A CN 112736132 A CN112736132 A CN 112736132A
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inp
buffer layer
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furnace
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CN112736132B (en
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周书星
王寅
张欣
类淑来
胡青松
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Hubei University of Arts and Science
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Abstract

The invention discloses an InP PHEMT epitaxial structure and a preparation method thereof, wherein the epitaxial structure comprises an InP substrate, a graded buffer layer, a channel layer, an isolation layer, a Si plane doping layer, a barrier layer, an etching stop layer, a first contact layer and a second contact layer which are sequentially stacked from bottom to top, and the graded buffer layer is made of InxA11‑ xAs, wherein x is sequentially and continuously increased from 0.52 to 0.8 from the lower end to the upper end of the graded buffer layer, and the material of the channel layer is InyGa1‑yAs, y is more than or equal to 0.8 and less than or equal to 1. Because the In component In the graded buffer layer is continuously graded, the lattice constant of the virtual substrate is increased and slowly increased, which is beneficial to growing the high-quality high-In-component grooveThe electron mobility of the two-dimensional electron gas of the InP PHEMT epitaxial structure is mentioned.

Description

InP PHEMT epitaxial structure and preparation method thereof
Technical Field
The invention relates to the field of semiconductor thin film materials, in particular to an InP PHEMT epitaxial structure and a preparation method thereof.
Background
HEMT (High Electron Mobility Transistor) is a heterojunction semiconductor device developed in the first 80 th century, and is also called modulation doped field effect Transistor (MODFET), two-dimensional Electron gas field effect Transistor (2-DEGFET), Selective Doped Heterojunction Transistor (SDHT), and the like. Both such devices and their integrated circuits can operate in the ultra high frequency (mm wave), ultra high speed domain because they operate with a so-called two-dimensional electron gas (2DEG) having a very high mobility. PHEMT is an improved structure for High Electron Mobility Transistors (HEMTs), also known as pseudomodulation doped heterojunction field effect transistors (PMODFETs).
The high electron mobility transistor based on the InP base material works by utilizing high mobility two-dimensional electron gas (2DEG) of the InGaAs channel, so that the high electron mobility transistor has the characteristics of high speed, high frequency, high power gain, low noise, low power consumption and the like, is very suitable for manufacturing millimeter wave terahertz wave low noise amplifier circuits and systems, and is widely applied to the fields of radar, communication, navigation, safety, radio astronomy, medical treatment and the like which are closely related to national economy and national safety. However, the In component In the InGaAs channel layer of the conventional InP HEMT epitaxial structure is too low, which limits the improvement of the two-dimensional electron gas characteristics of the InP HEMT.
Disclosure of Invention
The invention mainly aims to provide an InP PHEMT epitaxial structure and a preparation method thereof, and aims to solve the problem that the In component In a channel layer of the conventional InP HEMT epitaxial structure is too low.
In order to achieve the purpose, the InP PHEMT epitaxial structure provided by the invention comprises an InP substrate, a graded buffer layer, a channel layer, an isolation layer, a Si plane doping layer, a barrier layer, an etching stop layer, a first contact layer and a second contact layer which are sequentially stacked from bottom to top, wherein the graded buffer layer is made of InxA11-xAs, x is sequentially and continuously increased from 0.52 to 0.8 from the lower end to the upper end of the graded buffer layer, and the channel layerThe material is InyGa1-yAs，0.8≤y≤1。
Preferably, the InP PHEMT epitaxial structure further includes a lower buffer layer and an upper buffer layer, the lower buffer layer, the graded buffer layer, the upper buffer layer and the channel layer are sequentially stacked from bottom to top, and the lower buffer layer is made of InP and In0.52Al0.48As or In0.53Ga0.47As, the upper buffer layer is made of InzA11-zAs, wherein, z is more than or equal to 0.7 and less than or equal to 0.9.
Preferably, the material of the isolation layer is InmA11-mAs, 0.7-m 0.9, and the barrier layer is InnA11-nAs，0.7≤n≤0.9。
Preferably, the material of the etching stop layer is InAs1-jPj，0.1≤j≤1。
Preferably, the material of the first contact layer is N-type In doped with SikGa1-kAs, k is more than or equal to 0.8 and less than or equal to 0.9; the material of the second contact layer is N-type InAs doped with Si.
Preferably, the doping concentration of the Si plane doping layer is 4 x 1012cm-2～7×1012cm-2(ii) a The doping concentration of the first contact layer is more than 1019cm-3The doping concentration of the second contact layer is more than 1018cm-3。
Preferably, the InP substrate is 50nm to 150nm, the graded buffer layer is 0.5um to 3um, the channel layer is 10nm to 30nm, the isolation layer is 2nm to 6nm, the barrier layer is 5nm to 20nm, the etch stop layer is 2nm to 6nm, the first contact layer is 10nm to 20nm, and the second contact layer is 5nm to 10 nm.
In addition, the invention also provides a preparation method of the InP PHEMT epitaxial structure, which is used for preparing the InP PHEMT epitaxial structure and comprises the following steps:
placing the InP substrate in a reaction chamber, and carrying out heat treatment on the InP substrate;
epitaxially growing the graded buffer layer on the InP substrate;
epitaxially growing the channel layer on the graded buffer layer;
epitaxially growing the isolation layer on the channel layer;
epitaxially growing the Si plane doping layer on the isolation layer;
epitaxially growing the barrier layer on the Si planar doping layer;
epitaxially growing the etch stop layer on the barrier layer;
epitaxially growing the first contact layer on the etching stop layer;
epitaxially growing the second contact layer on the first contact layer.
Preferably, the conditions of the heat treatment are: and (3) sending the InP substrate into a pretreatment chamber of a gaseous source molecular beam epitaxy system (GSMBE), and degassing at the temperature of 250-300 ℃ for 20-40 min.
Preferably, the temperature in the epitaxial growth process of the graded buffer layer is 300-500 ℃, and AsH3The cracking pressure of the furnace is 300-800 Torr, the temperature of the Al furnace is kept unchanged, and the temperature of the In furnace is gradually increased In a one-way so as to lead In to be InxA11-xThe In component x In As gradually increases from 0.52 to 0.8.
In the technical scheme of the invention, the InP PHEMT epitaxial structure comprises an InP substrate, a graded buffer layer, a channel layer, an isolation layer, a Si plane doping layer, a barrier layer, an etching stop layer, a first contact layer and a second contact layer which are sequentially stacked from bottom to top, wherein the graded buffer layer is made of InxA11-xAs, wherein x is sequentially and continuously increased from 0.52 to 0.8 from the lower end to the upper end of the graded buffer layer, and the material of the channel layer is InyGa1-yAs, y is more than or equal to 0.8 and less than or equal to 1. Due to the fact that the In component In the graded buffer layer is graded continuously, the lattice constant of the virtual substrate is increased and is slowly increased, growth of a channel layer with high quality and high In component is facilitated, and the electron mobility of two-dimensional electron gas of the InP PHEMT epitaxial structure is improved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic diagram of an InP PHEMT epitaxial structure according to an embodiment of the invention;
FIG. 2 is a partial schematic view of an InP PHEMT epitaxial structure according to another embodiment of the invention;
FIG. 3 is an XRD (X-ray diffraction) characterization diagram of an InP PHEMT epitaxial structure according to an embodiment of the present invention;
FIG. 4 is a flow chart of a method for fabricating an InP PHEMT epitaxial structure according to an embodiment of the present invention;
fig. 5 is a partial flow chart of a method for fabricating an InP PHEMT epitaxial structure according to another embodiment of the present invention.
Examples reference numbers illustrate:
Figure BDA0002885912260000031
Figure BDA0002885912260000041
the implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The references to "up" and "down" in the present invention are based on the orientation shown in fig. 1 and are used only to explain the relative positional relationship between the components in the attitude shown in fig. 1, and if the particular attitude is changed, the directional indication is changed accordingly.
The invention provides an InP PHEMT epitaxial structure, which comprises an InP substrate 10, a graded buffer layer 22, a channel layer 30, an isolation layer 40, a Si plane doping layer 50, a barrier layer 60, an etching stop layer 70, a first contact layer 80 and a second contact layer 90 which are sequentially stacked from bottom to top as shown In figure 1, wherein the graded buffer layer 22 is made of InxA11-xAs, wherein x continuously increases from 0.52 to 0.8 from the lower end to the upper end of the graded buffer layer 22, and the material of the channel layer is InyGa1-yAs，0.8≤y≤1。
The graded buffer layer 22 is epitaxially grown by using MBE (molecular beam epitaxy), which is an epitaxial technique for preparing a multi-layered ultra-thin single crystal film and is formed along the crystal axis of a substrate material under appropriate conditions and an appropriate substrateThe method for growing the thin film layer by layer in the direction has the advantages that: the substrate used has low temperature, the film layer growth rate is slow, the beam intensity is easy to control accurately, and the film layer components and the doping concentration can be adjusted rapidly along with the source change. Since the In composition In the graded buffer layer 22 of the present invention is continuously graded, In at the lower end of the graded buffer layer 22xA11-xX In As is 0.52, In at the upper endxA11-xX In As is 0.8, the whole graded buffer layer 22 is a continuously increasing change process from bottom to top, so that the epitaxial material is slowly relaxed, the lattice constant is slowly increased, and the In with a high In component is grown by adopting a component continuous graded growth technologyxA11-xAs graded buffer layer 22 increases the lattice constant of the virtual substrate, and is favorable for growing high-quality and high-composition InyGa1-yAs (y is more than or equal to 0.8 and less than or equal to 1) channel layer 30 improves the electron mobility of the two-dimensional electron gas of the InP PHEMT epitaxial structure, improves the electrical characteristics of the epitaxial layer, and greatly improves the device performance of the InP PHEMT.
Further, as shown in fig. 2, the InP PHEMT epitaxial structure further includes a lower buffer layer 21 and an upper buffer layer 23; the lower buffer layer 21, the graded buffer layer 22, the upper buffer layer 23 and the channel layer 30 are sequentially stacked from bottom to top, and the lower buffer layer 21 is made of InP or In0.52Al0.48As or In0.53Ga0.47As, the upper buffer layer 23 is made of InzA11-zAs, wherein, z is more than or equal to 0.7 and less than or equal to 0.9. The lower buffer layer 21 and the upper buffer layer 23 are both constant components, and the growth quality of the surface of the virtual substrate is further improved. InP lower buffer layer 21, In grown In sequencexA11-xAs graded buffer layer 22(x is increased from 0.52 to 0.8) and InzA11-zThe As upper buffer layer 23 can reduce defects and dislocation caused by heteroepitaxy, and simultaneously, the epitaxial material is slowly relaxed, the lattice constant is slowly increased, and the growth of high-quality high-In component In is facilitatedyGa1-yAs (y is more than or equal to 0.8 and less than or equal to 1) channel layer 30.
The material of the isolation layer 40 is InmA11-m0.7-0.9 of As, and the barrier layer 60 is made of InnA11-nAs，N is more than or equal to 0.7 and less than or equal to 0.9. The material of the etch stop layer 70 is InAs1-jPjJ is more than or equal to 0.1 and less than or equal to 1, and the As element is added into the etching stop layer 70 to increase the lattice constant, better match the epitaxial layer and grow the etching stop layer 70 material with good quality. The material of the first contact layer 80 is Si-doped N-type InkGa1-kAs, k is more than or equal to 0.8 and less than or equal to 0.9. The material of the second contact layer 90 is Si-doped N-type InAs, so that the gold half-contact potential barrier is reduced, and the contact performance of the device is better.
The doping concentration of the Si plane doping layer 50 is 4X 1012cm-2～7×1012cm-2(ii) a The first contact layer 80 has a doping concentration of Si greater than 1019cm-3The doping concentration of the second contact layer 90Si is more than 1018cm-3。
The thickness of the InP substrate 10 is 50 nm-150 nm, the thickness of the lower buffer layer 21 is 50 nm-150 nm, the thickness of the graded buffer layer 22 is 0.5 um-3 um, the thickness of the upper buffer layer 23 is 0.1 um-0.5 um, the thickness of the channel layer 30 is 10 nm-30 nm, the thickness of the isolation layer 40 is 2 nm-6 nm, the thickness of the barrier layer 60 is 5 nm-20 nm, the thickness of the etching stop layer 70 is 2 nm-6 nm, the thickness of the first contact layer 80 is 10 nm-20 nm, and the thickness of the second contact layer 90 is 5 nm-10 nm. Table 1 is a parameter table of an InP PHEMT epitaxial structure of an embodiment, where Un means undoped, and the first contact layer 80, the second contact layer 90, and the Si plane-doped layer 50 are doped with Si, respectively.
TABLE 1 InP PHEMT epitaxial structure parameter table
Figure BDA0002885912260000061
In addition, the invention also provides a preparation method of the InP PHEMT epitaxial structure, which is used for preparing the InP PHEMT epitaxial structure, and as shown in FIG. 4, the preparation method comprises the following steps:
s10, placing the InP substrate in a reaction chamber, and carrying out heat treatment on the InP substrate;
the conditions of the heat treatment are as follows: and (3) sending the InP substrate into a pretreatment chamber of a gaseous source molecular beam epitaxy system, and degassing at the temperature of 250-300 ℃ for 20-40 min.
S20, epitaxially growing a graded buffer layer on the InP substrate;
in the epitaxial growth process of the graded buffer layer, the temperature is 300-500 ℃, and AsH3The cracking pressure of the furnace is 300-800 Torr, the temperature of the Al furnace is kept unchanged, and the temperature of the In furnace is gradually increased In a one-way so as to lead In to be InxA11-xThe In component x In As is gradually increased from 0.52 to 0.8 to obtain InxA11-xAn As graded buffer layer.
S30, epitaxially growing a channel layer on the graded buffer layer;
the epitaxial growth conditions were: the growth temperature is 300-500 ℃, and AsH3The cracking pressure of the furnace is 300-800 Torr, the furnace temperature of Ca and In is adjusted, and In growsyGa1-yAs (y is more than or equal to 0.8 and less than or equal to 1) channel layer.
S40, epitaxially growing an isolation layer on the channel layer;
the epitaxial growth conditions were: the growth temperature is 300-500 ℃, and AsH3The cracking pressure of the furnace is 300-800 Torr, the furnace temperature of Al and In is adjusted, and In growsmA11-mAn As (m is more than or equal to 0.7 and less than or equal to 0.9) isolating layer.
S50, epitaxially growing a Si plane doping layer on the isolation layer;
the epitaxial growth conditions were: the growth temperature is 300-500 ℃, and AsH3The cracking pressure of the silicon substrate is 300-800 Torr, the temperature of the maximum Si furnace is adjusted, and a Si plane doping layer grows.
S60, epitaxially growing a barrier layer on the Si plane doping layer;
the epitaxial growth conditions were: the growth temperature is 300-500 ℃, and AsH3The cracking pressure of the furnace is 300-800 Torr, the furnace temperature of Al and In is adjusted, and In growsnA11-nAn As (n is more than or equal to 0.7 and less than or equal to 0.9) barrier layer.
S70, epitaxially growing an etching stop layer on the barrier layer;
the epitaxial growth conditions were: the growth temperature is 300-500 ℃, and AsH3The cracking pressure of (A) is 50to 600Torr and the pH of the solution3The cracking pressure of 300-800 Torr, InAs growth1-jPj(j is more than or equal to 0.1 and less than or equal to 1) an etching stop layer.
S80, epitaxially growing a first contact layer on the etching stop layer;
the epitaxial growth conditions were: the growth temperature is 300-500 ℃, and AsH3The cracking pressure of the furnace is 300-800 Torr, the temperature of the Si furnace is adjusted to 1200-1300 ℃, the temperature of the Ca and In furnace is adjusted, and N-type In growskGa1-kAs (k is more than or equal to 0.8 and less than or equal to 0.9) first contact layer.
And S90, epitaxially growing a second contact layer on the first contact layer.
The epitaxial growth conditions were: the growth temperature is 300-500 ℃, and AsH3The cracking pressure of the InAs is 300-800 Torr, the proper temperature of the Si and In furnace is adjusted, and the N-type InAs second contact layer is grown.
In another embodiment, as shown in fig. 5, step S20 includes the following steps:
s21, epitaxially growing a lower buffer layer on the InP substrate;
the epitaxial growth conditions were: the growth temperature is 300-500 ℃, and AsH3The cracking pressure of the reactor is 300-800 Torr, the temperature of an In furnace is adjusted properly, and an InP lower buffer layer is grown.
S22, epitaxially growing a graded buffer layer on the lower buffer layer;
s23, epitaxially growing an upper buffer layer on the graded buffer layer;
the epitaxial growth conditions were: the growth temperature is 300-500 ℃, and AsH3The cracking pressure of the furnace is 300-800 Torr, the proper temperature of Al and In furnace is adjusted, and In growszA11-zAn As (z is more than or equal to 0.7 and less than or equal to 0.9) upper buffer layer.
Then, a channel layer is epitaxially grown on the upper buffer layer.
Example 1
Specific parameters of the InP PHEMT epitaxial structure of this embodiment are shown in table 2, and an XRD characterization pattern of the InP PHEMT epitaxial structure of this embodiment is shown in fig. 3.
TABLE 2 InP PHEMT epitaxy concrete structure table
Figure BDA0002885912260000081
The InP PHEMT epitaxial structure of this embodiment includes the following steps:
in step S10, the InP substrate is sent to the pretreatment chamber of the gaseous source molecular beam epitaxy system, and degassing is performed at a temperature of 300 ℃ for 30 minutes;
in step S21, the substrate is transferred to a growth chamber of a gaseous source molecular beam epitaxy system, and PH is adjusted3Cleavage at a temperature of l000 ℃ to give P2Used as phosphorus source for adjusting PH of gas source furnace3The pressure is 600Torr, the substrate is heated to the desorption temperature of 500 ℃ under the protection of P atmosphere to remove an oxide layer on the surface, the desorption process is monitored by high-energy electron diffraction (RHEED), the temperature of the substrate is reduced to 400 ℃ after the desorption, the temperature of an In furnace is 800 ℃, an In furnace shutter is opened to carry out the epitaxial growth of an InP buffer layer, the substrate rotates at the speed of 8 revolutions per minute during the growth to ensure the uniformity of an epitaxial material, the growth rate is 0.5um/h at the moment, and the growth thickness is 50 nm;
in step S22, the gas source furnace PH is turned off3Opening the gas source furnace AsH3AsH is prepared by3Cleavage at l000 ℃ to give As2Furnace AsH used as arsenic source and adjusting gas source3The pressure is 600Torr, the epitaxial layer is under the protection of As atmosphere, the growth temperature is adjusted to 400 ℃, the temperature of the Al furnace is kept unchanged at 1000 ℃, the temperature of the In furnace is slowly increased from 800 ℃ to 950 ℃ In one way, the speed is 0.005 ℃, so that In is enabledxA11-xThe In component x In As is slowly changed to 0.8 when the In component x is 0.52, and the growth thickness is about 1500 nm;
in step S23, the growth temperature is 400 ℃, the Al furnace temperature is 1000 ℃, the In furnace temperature is 950 ℃, and the AsH temperature is3The cracking pressure of the furnace is 650Torr, the cracking temperature is l000 ℃, and the shutter of the fast Al and In furnace is opened simultaneously to grow In0.8A10.2As buffer layer with thickness of 250 nm.
In step S30, the conditions for epitaxial growth are: growth temperature 400 deg.C, AsH3The cracking pressure of the furnace is 650Torr, the temperature of the Ga furnace and the In furnace are respectively adjusted to 1020 ℃ and 950 ℃, and the shutter of the fast Ga furnace and the In furnace are opened simultaneously to grow In0.85Ga0.15An As channel layer having a thickness of 20 nm.
In step S40, the conditions for epitaxial growth are: growth temperature 400 deg.C, AsH3Cracking pressure ofThe pressure is 650Torr, the temperature of the Al furnace is adjusted to 1000 ℃, the temperature of the In furnace is adjusted to 950 ℃, and the shutter of the fast Al furnace and the In furnace are opened to grow In0.8A10.2As spacer layer with thickness of 4 nm.
In step S50, the growth temperature is 400 ℃, AsH3The cracking pressure of the Si furnace is 650Torr, the temperature of the Si furnace is 1260 ℃, and the Si plane doped layer 5010s is grown to reach the doped concentration of the doped layer of 6 multiplied by 12cm-2。
In step S60, the conditions for epitaxial growth are: growth temperature 400 deg.C, AsH3The cracking pressure of the furnace is 650Torr, the temperature of the Al furnace is adjusted to 1000 ℃, the temperature of the In furnace is adjusted to 950 ℃, and the shutter of the Al furnace and the In furnace are opened to grow In with the thickness of 10nm0.8A10.2An As barrier layer.
In step S70, the conditions for epitaxial growth are: growth temperature 400 deg.C, AsH3The cracking pressure of (A) is 100Torr and pH is3The cracking pressure of the furnace is 650Torr, the temperature of the In furnace is 950 ℃, and 3nm InAs grows0.3P0.7And etching the stop layer.
In step S80, the conditions for epitaxial growth are: growth temperature 400 deg.C, AsH3The cracking pressure of the furnace is 650Torr, the temperature of the Si furnace is 1265 ℃, the temperatures of the Ga furnace and the In furnace are respectively adjusted to be 1020 ℃ and 950 ℃, and 15nm N-type In grows0.85Ga0.15An As first contact layer.
In step S90, the conditions for epitaxial growth are: growth temperature 350 ℃, AsH3The cracking pressure of the furnace is 650Torr, the temperature of the Si furnace is 1265 ℃, the temperature of the In furnace is 950 ℃, and a 5nm N-type InAs second contact layer grows.
In this example, MBE was used for epitaxial growth, and In having a high In content was grown by using a continuous graded growth techniquexA11-xAn As graded buffer layer to grow In with high In componentxGa1-xThe As (x is more than or equal to 0.8 and less than or equal to 1) channel layer improves the electrical characteristics of the InP PHEMT epitaxial layer, greatly improves the device performance of the InP PHEMT, and meanwhile, the InP PHEMT epitaxial structure is simple and is suitable for batch production.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (10)

1. The InP PHEMT epitaxial structure is characterized by comprising an InP substrate, a graded buffer layer, a channel layer, an isolation layer, a Si plane doping layer, a barrier layer, an etching stop layer, a first contact layer and a second contact layer which are sequentially stacked from bottom to top, wherein the graded buffer layer is made of InxA11-xAs, wherein x is sequentially and continuously increased from 0.52 to 0.8 from the lower end to the upper end of the graded buffer layer, and the material of the channel layer is InyGa1-yAs，0.8≤y≤1。
2. The InP PHEMT epitaxial structure according to claim 1, further comprising a lower buffer layer and an upper buffer layer, wherein the lower buffer layer, the graded buffer layer, the upper buffer layer and the channel layer are sequentially stacked from bottom to top, and the lower buffer layer is made of InP and In0.52Al0.48As or In0.53Ga0.47As, the upper buffer layer is made of InzA11-zAs, wherein, z is more than or equal to 0.7 and less than or equal to 0.9.
3. The InP PHEMT epitaxial structure of claim 1, wherein the spacer layer is InmA11- mAs, 0.7-m 0.9, and the barrier layer is InnA11-nAs，0.7≤n≤0.9。
4. The InP PHEMT epitaxial structure of claim 1 wherein the material of the etch stop layer is InAs1-jPj，0.1≤j≤1。
5. The InP PHEMT epitaxial structure of claim 1, wherein the material of the first contact layer is Si-doped N-type InkGa1-kAs, k is more than or equal to 0.8 and less than or equal to 0.9; the second connectionThe contact layer is made of N-type InAs doped with Si.
6. The InP PHEMT epitaxial structure of claim 5, wherein the doping concentration of the Si-plane doped layer is 4 x 1012cm-2～7×1012cm-2(ii) a The doping concentration of the first contact layer is more than 1019cm-3The doping concentration of the second contact layer is more than 1018cm-3。
7. The InP PHEMT epitaxial structure according to any one of claims 1 to 6, wherein the InP substrate has a thickness of 50nm to 150nm, the graded buffer layer has a thickness of 0.5um to 3um, the channel layer has a thickness of 10nm to 30nm, the isolation layer has a thickness of 2nm to 6nm, the barrier layer has a thickness of 5nm to 20nm, the etch stop layer has a thickness of 2nm to 6nm, the first contact layer has a thickness of 10nm to 20nm, and the second contact layer has a thickness of 5nm to 10 nm.
8. A method for preparing an InP PHEMT epitaxial structure, which is used for preparing the InP PHEMT epitaxial structure as claimed in any one of claims 1-7, and comprises the following steps:
placing the InP substrate in a reaction chamber, and carrying out heat treatment on the InP substrate;
epitaxially growing the graded buffer layer on the InP substrate;
epitaxially growing the channel layer on the graded buffer layer;
epitaxially growing the isolation layer on the channel layer;
epitaxially growing the Si plane doping layer on the isolation layer;
epitaxially growing the barrier layer on the Si planar doping layer;
epitaxially growing the etch stop layer on the barrier layer;
epitaxially growing the first contact layer on the etching stop layer;
epitaxially growing the second contact layer on the first contact layer.
9. The method of claim 8, wherein the heat treatment is carried out under the following conditions: and sending the InP substrate into a pretreatment chamber of a gaseous source molecular beam epitaxy system, and degassing at the temperature of 250-300 ℃ for 20-40 min.
10. The method according to claim 8, wherein the temperature of the epitaxial growth process of the graded buffer layer is 300-500 ℃ and the AsH temperature is higher than that of the epitaxial growth process of the graded buffer layer3The cracking pressure of the furnace is 300-800 Torr, the temperature of the Al furnace is kept unchanged, and the temperature of the In furnace is gradually increased In a one-way so as to lead In to be InxA11-xThe In component x In As gradually increases from 0.52 to 0.8.
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