CN112714270A - DP interface chip, high definition video receiving chip and electronic equipment - Google Patents
DP interface chip, high definition video receiving chip and electronic equipment Download PDFInfo
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Abstract
The application provides a DP interface chip, high definition video receive chip and electronic equipment. The DP interface chip comprises a buffer, the buffer comprises a plurality of output channels, the buffer is used for receiving identification information of a Type-C interface and a plurality of input signals of the Type-C interface, the output channels receive the input signals in a one-to-one correspondence mode and output the input signals according to the identification information, and the identification information comprises information of whether a Type-C cable is inserted into the Type-C interface or not. Compared with the prior art, the DP interface chip does not need to increase a multiplexer, can realize corresponding output of the input signal which is inserted or reversely inserted into the Type-C interface, avoids the problem that the cost is higher due to the fact that the multiplexer is added to the existing Type-C video interface chip, and well saves the manufacturing cost of the DP interface chip.
Description
Technical Field
The application relates to the field of Type-C interfaces, in particular to a DP interface chip, a high-definition video receiving chip and electronic equipment.
Background
A new generation of Type-C interface is increasingly used for DisplayPort (DP, display interface) video transmission because it supports forward and reverse insertion and is convenient to use. The Type-C socket signal definitions are shown in Table 1 below (for more information please see the Type-C standard for the USB-IF organization and the DP Alt Mode on USB Type-C standard for the VESA organization):
TABLE 1
The CC1 and the CC2 can be used for positive and negative insertion detection, for example, if the CC of the current Type-C interface is connected with the CC1, it indicates that the current Type-C interface is a positive insertion; the CC2 connected to the current Type-C interface indicates reverse insertion.
A2/A3(TX1+/-), B11/B10(RX1+/-), A11/A10(RX2+/-), B2/B3(TX2+/-) four groups of differential channels are used for high-speed signal transmission. When the DisplayPort video 4-channel mode is entered, the four groups of differential channels are used for DisplayPort high-speed video signal transmission, and the correspondence between the 4 channels Lane0, Lane1, Lane2 and Lane3 of DisplayPort and the four groups of differential channels is as follows:
when the cable is inserted frontally, as shown in table 2:
TABLE 2
| Type-C differential group pin | DisplayPort lane |
| A2/A3 | Lane2 |
| B11/B10 | Lane3 |
| A11/A10 | Lane0 |
| B2/B3 | Lane1 |
When the cable is inserted on the reverse side, as shown in table 3:
TABLE 3
| Type-C differential group pin | DisplayPort lane |
| A2/A3 | Lane1 |
| B11/B10 | Lane0 |
| A11/A10 | Lane3 |
| B2/B3 | Lane2 |
Therefore, when the cable is inserted in a forward direction and a backward direction, the corresponding relation between the Type-C difference grouping pin and the DisplayPort lane is different. In order to support the forward and reverse insertion of a Type-C display device, a Multiplexer (MUX) needs to be configured on the circuit design, and the MUX is either an external discrete device or embedded in a video interface chip. Fig. 1 illustrates a block diagram of the circuit design of the MUX 40 as a discrete device. The Type-C controller chip 30 configures the high-speed data selection matrix inside the MUX 40 according to the front and back identification information (CC1 or CC2) of the Type-C interface 20, and sends the high-speed video serial signals to the DP interface chip 10 in a correct correspondence.
The MUX 40 configuration is specifically shown in fig. 2(a) and 2 (b). When the front surface is inserted, the configuration is according to the corresponding relation of table 2, as shown in fig. 2 (a); when the reverse side is inserted, the corresponding relationship configuration according to table 3 is shown in fig. 2 (b);
as a discrete device, high-speed MUXs add to circuit component inventory costs. When the high-speed MUX is embedded in a DP interface chip, the cost of the chip is also increased.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The application mainly aims to provide a DP interface chip, a high definition video receiving chip and an electronic device to solve the problem that the Type-C video interface chip in the prior art is high in cost.
In order to achieve the above object, according to an aspect of the present application, there is provided a DP interface chip, including a buffer, where the buffer includes a plurality of output channels, the buffer is configured to receive identification information of a Type-C interface and a plurality of input signals of the Type-C interface, and according to the identification information, the output channels receive and output the input signals in a one-to-one correspondence, and the identification information includes information on whether a Type-C cable is inserted into the Type-C interface in a front side.
Optionally, the chip further comprises a serial-to-parallel converter electrically connected to the input of the buffer, the serial-to-parallel converter being configured to convert a plurality of serial input signals of the Type-C interface into a plurality of parallel output signals, and to transmit the plurality of parallel output signals to the buffer, the rate of the parallel output signals being smaller than the rate of the serial input signals.
Optionally, the chip further includes a data processor, the data processor is electrically connected to an output end of the buffer, and the data processor is configured to receive a signal output from the output channel and process the signal to obtain a data format of the predetermined code stream.
Optionally, the buffer is a digital buffer.
Optionally, the buffer further includes a matrix control unit, where the matrix control unit includes a control program for connecting the input signal and the corresponding output channel, and the matrix control unit is configured to control the output channels to receive the input signal in a one-to-one correspondence manner according to the identification information and the control program.
In order to achieve the above object, according to another aspect of the present application, there is provided a high definition video receiving chip, including a DP interface chip, where the DP interface chip is any one of the chips.
Optionally, the chip further comprises a Type-C interface, the Type-C interface is electrically connected with the DP interface chip, and the Type-C interface is used for transmitting a plurality of input signals of a Type-C cable to the DP interface chip.
Optionally, the chip further comprises a Type-C control chip, the Type-C control chip is electrically connected with the Type-C interface and the DP interface chip respectively, and the Type-C control chip is used for identifying whether the Type-C cable is inserted into the Type-C interface or not, generating identification information and sending the identification information to the DP interface chip.
In order to achieve the above object, according to still another aspect of the present application, there is provided an electronic device, including a high definition video receiving chip, where the high definition video receiving chip is any one of the chips.
The DP interface chip of this application includes the buffer, the buffer includes a plurality of output channel, the buffer is used for receiving a plurality of input signal of identification information and Type-C interface, identification information has two kinds, and is first, and the Type-C cable openly inserts Type-C interface, the second kind, Type-C cable do not openly insert Type-C interface, also be exactly Type-C cable reverse side inserts Type-C interface, according to identification information, the output channel one-to-one is received input signal and output. Compared with the prior art, the DP interface chip does not need to increase a multiplexer, can realize corresponding output of the input signal which is inserted or reversely inserted into the Type-C interface, avoids the problem that the cost is higher due to the fact that the multiplexer is added to the existing Type-C video interface chip, and well saves the manufacturing cost of the DP interface chip.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 shows a block diagram of a circuit design of a prior MUX as a discrete device;
fig. 2(a) and fig. 2(b) are schematic diagrams respectively showing two configurations of the prior MUX as an input/output signal of a discrete device;
FIG. 3 shows a schematic diagram of the components of a DP interface chip according to an embodiment of the present application;
fig. 4 shows a schematic composition diagram of a high definition video receiving chip according to an embodiment of the present application;
fig. 5 and fig. 6 respectively show a schematic configuration relationship of input and output signals of a high definition video receiving chip according to an embodiment of the present application;
FIG. 7 shows a circuit schematic of a single pole double throw switch according to an embodiment of the present application;
fig. 8 is a schematic diagram illustrating an operation flow of a high definition video receiving chip according to an embodiment of the present application.
Wherein the figures include the following reference numerals:
10. a DP interface chip; 20. a Type-C interface; 30. a Type-C control chip; 40. MUX; 100. a buffer; 101. a serial to parallel converter; 102. a data processor; 103. outputting the signal; 104. inputting a signal.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
Just as the introduction of background art, Type-C video interface chip cost is higher among the prior art, in order to solve above-mentioned problem, this application has proposed a DP interface chip, high definition video receiving chip and electronic equipment.
According to an exemplary embodiment of the present application, there is provided a DP interface chip 10, as shown in fig. 3, where the DP interface chip 10 includes a buffer 100, the buffer 100 includes a plurality of output channels, the buffer 100 is configured to receive identification information of a Type-C interface and a plurality of input signals of the Type-C interface, the output channels receive and output the input signals in a one-to-one correspondence according to the identification information, and the identification information includes information on whether a Type-C cable is inserted into the Type-C interface in a front side.
The DP interface chip comprises a buffer, the buffer comprises a plurality of output channels, the buffer is configured to receive a plurality of input signals of the identification information and the Type-C interface, the identification information has two types, the first Type is that the Type-C cable is inserted into the Type-C interface in a front side, the second Type is that the Type-C cable is not inserted into the Type-C interface in a front side, that is, the Type-C cable is inserted into the Type-C interface in a back side, and the output channels receive and output the input signals in a one-to-one correspondence manner according to the identification information. Compared with the prior art, the DP interface chip does not need to be added with a multiplexer, and can realize corresponding output of the input signal which is inserted in the front or back of the Type-C interface, so that the problem that the cost is higher due to the addition of the Multiplexer (MUX) in the conventional Type-C video interface chip is solved, and the manufacturing cost of the DP interface chip is better saved.
According to a specific embodiment of the present application, as shown in fig. 3, the chip further includes a serial-to-parallel converter 101, the serial-to-parallel converter 101 is electrically connected to an input terminal of the buffer 100, the serial-to-parallel converter 101 is configured to convert a plurality of serial input signals of the Type-C interface into a plurality of parallel output signals, and transmit the plurality of parallel output signals to the buffer 100 as the input signals, and a rate of the parallel output signals is smaller than a rate of the serial input signals. The chip converts a plurality of high-speed serial input signals into a plurality of relatively low-speed parallel output signals through the serial-parallel converter, and then transmits the plurality of parallel output signals to the buffer. Moreover, the serial-to-parallel converter is a module that the DP interface chip originally has, and is not a module that is added for facilitating the corresponding output of the buffer to the input signal that the Type-C interface is being inserted or being reversely inserted, so that the manufacturing cost of the DP interface chip is further ensured to be low, and the problem that the cost is high due to the addition of a multiplexer in the existing Type-C video interface chip is further avoided.
In one specific embodiment, the serial-to-parallel converter can convert a pair of serial input signals into 20 sets of parallel output signals, and the rate of the parallel output signals is only 1/20 times the rate of the serial input signals. Of course, the serial-to-parallel converter described above may also convert other numbers of serial input signals into other numbers of parallel output signals.
According to another specific embodiment of the present application, as shown in fig. 3, the chip further includes a data processor 102, the data processor 102 is electrically connected to an output end of the buffer 100, and the data processor 102 is configured to receive a signal output from the output channel and process the signal to obtain a data format of a predetermined code stream. The data processor realizes processing of the signal output from the output channel. Moreover, the data processor is a module that the DP interface chip originally has, and is not a module that is added for the convenience of performing corresponding output on the input signal that the Type-C interface is being inserted or being reversely inserted by the buffer, so that the manufacturing cost of the DP interface chip is further ensured to be low, and the problem that the cost is high due to the addition of a multiplexer in the existing Type-C video interface chip is further avoided.
In an actual application process, the data processor firstly decodes the received signal output by the output channel, and then re-encodes the decoded signal to obtain a data format of a predetermined code stream, wherein the predetermined code stream is a code stream format required by the display processor. In a specific embodiment, the signal output by the output channel may be a DP original video signal, but the signal may also be other digital signals.
In practical applications, the buffer may be any kind of buffer in the prior art, and those skilled in the art can select the buffer according to practical requirements.
In order to further ensure that the output channels in the buffer can more accurately receive and output the corresponding input signals, in another specific embodiment of the present application, the buffer further includes a matrix control unit, the matrix control unit includes a control program for connecting the input signals to the corresponding output channels, and the matrix control unit is configured to control the output channels to receive the input signals in a one-to-one correspondence manner according to the identification information and the control program.
According to another exemplary embodiment of the present application, there is further provided a high definition video receiving chip, as shown in fig. 4, the high definition video receiving chip includes a DP interface chip 10, and the DP interface chip 10 is any one of the above chips.
The high-definition video receiving chip comprises any DP interface chip, and compared with the prior art, the high-definition video receiving chip can realize corresponding output of input signals which are inserted into the Type-C interface or inserted into the Type-C interface reversely without adding a Multiplexer (MUX), so that the problem that the cost is high due to the fact that the multiplexer is added to the Type-C video interface chip in the prior art is avoided, and the manufacturing cost of the high-definition video receiving chip is well saved.
According to another specific embodiment of the present application, as shown in fig. 4, the chip further includes a Type-C interface 20, the Type-C interface 20 is electrically connected to the DP interface chip 10, and the Type-C interface 20 is configured to transmit a plurality of input signals of a Type-C cable to the DP interface chip. Above-mentioned high definition video receiving chip transmits a plurality of input signal of Type-C cable for above-mentioned DP interface chip through above-mentioned Type-C interface, and the follow-up DP interface chip of being convenient for corresponds the output to a plurality of above-mentioned input signal.
In an actual application process, as shown in fig. 4, the chip further includes a Type-C control chip 30, the Type-C control chip 30 is electrically connected to the Type-C interface 20 and the DP interface chip 10, and the Type-C control chip 30 is configured to identify whether the Type-C cable is inserted into the Type-C interface 20 from the front side, generate identification information, and send the identification information to the DP interface chip 10. Above-mentioned high definition video receiving chip discerns above-mentioned Type-C cable through above-mentioned Type-C control chip and inserts openly or the reverse side to with identification information transmission above-mentioned DP interface chip, further made things convenient for like this follow-up DP interface chip to correspond the output to a plurality of above-mentioned input signal according to above-mentioned identification information, further guaranteed that the accuracy of corresponding output is higher.
In a specific embodiment, according to the corresponding relationship between table 2 and table 3, schematic diagrams of the high definition video receiving chip performing one-to-one output on a plurality of input signals are shown in fig. 5 and fig. 6, where fig. 5 is a schematic diagram corresponding to a Type-C cable inserted in a front side, and fig. 6 is a schematic diagram corresponding to a Type-C cable inserted in a back side.
In practical applications, the crossing of any two low-speed digital signals can be implemented by a simple circuit similar to a "single-pole double-throw" switch, as shown in fig. 7, and the output signal 103 is selectively connected to one of the two input signals 104 through the single-pole double-throw switch. In a specific embodiment, according to the corresponding relationship between table 2 and table 3, the serial-to-parallel converter converts a pair of serial input signals into 20 sets of parallel output signals, the number of the serial input signals is 4, the number of the output channels is 4, and 80 sets of parallel output signals are obtained after the conversion by the serial-to-parallel converter. When 80 sets of parallel output signals are applied to the circuit shown in fig. 4, a matrix is formed, and the input-output relationship shown in fig. 5 and fig. 6 is obtained, namely, the control program in the matrix control unit. The equivalent hardware language of the control program may be as follows:
if (select) CC 1// front insertion
{
O1[19:0]＝I3[19:0]；
O2[19:0]＝I4[19:0]；
O3[19:0]＝I1[19:0]；
O4[19:0]＝I2[19:0]；
}
else// reverse insertion
{
O1[19:0]＝I2[19:0]；
O2[19:0]＝I1[19:0]；
O3[19:0]＝I4[19:0]；
O4[19:0]＝I5[19:0]；
}
Of course, the number of the output channels may be other numbers, the serial-to-parallel converter may convert other numbers of serial input signals into other numbers of parallel output signals, and the control program of the matrix unit may be implemented by other hardware languages.
In another specific embodiment of the present application, an operation flow of the high definition video receiving chip is as shown in fig. 8, and firstly, it is determined whether a Type-C cable is inserted into a Type-C interface, in case that the Type-C cable is inserted into the Type-C interface, the chip is powered on, the Type-C interface transmits a plurality of input signals of the Type-C cable to the serial-parallel converter in the DP interface chip, the serial-parallel converter converts a plurality of serial input signals of the Type-C interface into a plurality of parallel output signals and transmits the plurality of parallel output signals as the input signals to the buffer, the Type-C control chip identifies whether the Type-C cable is inserted into the Type-C interface in a front side, and generates identification information to transmit to the buffer in the DP interface chip, when the buffer receives the identification information of the Type-C interface inserted into the front side of the Type-C cable, the buffer configures an input signal according to a control program shown in fig. 5 and transmits an output signal to the data processor; when the buffer receives the identification information of the Type-C interface inserted into the reverse side of the Type-C cable, the buffer configures an input signal according to a control program shown in fig. 6 and transmits an output signal to the data processor. Of course, the control program is not limited to the configuration shown in fig. 5 and 6, and may be in other configurations.
According to still another exemplary embodiment of the present application, there is provided an electronic device including a high definition video receiving chip, the high definition video receiving chip being any one of the above chips.
Compared with the prior art, the electronic equipment comprises any high-definition video receiving chip, and can realize corresponding output of the input signal which is just inserted or reversely inserted into the Type-C interface without adding a Multiplexer (MUX), so that the problem that the cost is high due to the fact that the multiplexer is added to the existing Type-C video interface chip is avoided, and the manufacturing cost of the electronic equipment is well saved.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) the DP interface chip of this application includes the buffer, and above-mentioned buffer includes a plurality of output channel, and above-mentioned buffer is used for receiving a plurality of input signals of above-mentioned identification information and Type-C interface, and above-mentioned identification information has two kinds, and is the first kind, and above-mentioned Type-C interface is openly inserted to Type-C cable, and the second kind, Type-C cable do not openly insert above-mentioned Type-C interface, that is to say Type-C cable reverse side inserts above-mentioned Type-C interface, according to above-mentioned identification information, above-mentioned input signal of above-mentioned output channel one-to-one ground receipt is exported. Compared with the prior art, the DP interface chip does not need to be added with a multiplexer, and can realize corresponding output of the input signal which is inserted in the front or back of the Type-C interface, so that the problem that the cost is higher due to the addition of the Multiplexer (MUX) in the conventional Type-C video interface chip is solved, and the manufacturing cost of the DP interface chip is better saved.
2) The high definition video receiving chip of this application includes any kind of foretell DP interface chip, compares prior art, and foretell high definition video receiving chip need not to increase Multiplexer (MUX), can realize inserting or anti-the input signal who inserts to Type-C interface and correspond the output, has avoided current Type-C video interface chip to lead to the problem that the cost is higher because of increasing the multiplexer, has saved high definition video receiving chip's cost of manufacture betterly.
3) The electronic equipment comprises any one of the high-definition video receiving chips, and compared with the prior art, the electronic equipment does not need to increase a Multiplexer (MUX), can realize corresponding output of input signals which are inserted into a Type-C interface or inserted into a reverse mode, avoids the problem that the cost is high due to the fact that the multiplexer is added to the existing Type-C video interface chip, and well saves the manufacturing cost of the electronic equipment.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (9)
1. A DP interface chip, comprising:
the buffer comprises a plurality of output channels, the buffer is used for receiving identification information of a Type-C interface and a plurality of input signals of the Type-C interface, the output channels receive the input signals in a one-to-one correspondence mode and output the input signals according to the identification information, and the identification information comprises information of whether a Type-C cable is inserted into the Type-C interface or not.
2. The chip of claim 1, wherein the chip further comprises:
and the serial-parallel converter is electrically connected with the input end of the buffer and is used for converting a plurality of serial input signals of the Type-C interface into a plurality of parallel output signals and transmitting the plurality of parallel output signals to the buffer, and the rate of the parallel output signals is smaller than that of the serial input signals.
3. The chip of claim 1, wherein the chip further comprises:
and the data processor is electrically connected with the output end of the buffer and used for receiving the signal output from the output channel and processing the signal to obtain the data format of the preset code stream.
4. The chip of claim 1, in which the buffer is a digital buffer.
5. The chip according to any one of claims 1 to 4, wherein the buffer further comprises a matrix control unit, the matrix control unit includes a control program for connecting the input signals with the corresponding output channels, and the matrix control unit is configured to control the output channels to receive the input signals in a one-to-one correspondence according to the control program according to the identification information.
6. A high definition video receiving chip, comprising:
a DP interface chip as claimed in any one of claims 1 to 5.
7. The chip of claim 6, wherein the chip further comprises:
the Type-C interface, with DP interface chip electricity is connected, the Type-C interface is used for transmitting a plurality of input signal of Type-C cable for DP interface chip.
8. The chip of claim 7, wherein the chip further comprises:
Type-C control chip, with Type-C interface with DP interface chip electricity respectively is connected, Type-C control chip is used for discerning whether the Type-C cable openly inserts the Type-C interface generates identifying information and sends for DP interface chip.
9. An electronic device, comprising:
a high definition video receiving chip, the high definition video receiving chip being the chip of any one of claims 6 to 8.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114095669A (en) * | 2021-10-20 | 2022-02-25 | 瑞芯微电子股份有限公司 | Multi-input multi-output video bridging chip |
| WO2023184064A1 (en) * | 2022-03-28 | 2023-10-05 | 京东方科技集团股份有限公司 | Data transfer method and apparatus, and computer-readable storage medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107003970A (en) * | 2014-12-24 | 2017-08-01 | 英特尔公司 | The transceiver interconnected by USB c-types is multiplexed |
| CN109346883A (en) * | 2018-09-20 | 2019-02-15 | 合肥联宝信息技术有限公司 | A kind of system for realizing the positive anti-plug of Type-C interface |
| CN109344108A (en) * | 2018-09-10 | 2019-02-15 | 普联技术有限公司 | A kind of Type-C interface equipment, communication means and communication system |
| TWI691846B (en) * | 2018-10-04 | 2020-04-21 | 宏碁股份有限公司 | Electronic device and electronic system |
| CN111418013A (en) * | 2018-02-07 | 2020-07-14 | 美光科技公司 | Memory device parallelizer |
| CN212112455U (en) * | 2020-05-19 | 2020-12-08 | 广州视源电子科技股份有限公司 | Type-c interface circuit, chip and electronic equipment |
-
2020
- 2020-12-17 CN CN202011504148.0A patent/CN112714270A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107003970A (en) * | 2014-12-24 | 2017-08-01 | 英特尔公司 | The transceiver interconnected by USB c-types is multiplexed |
| CN111418013A (en) * | 2018-02-07 | 2020-07-14 | 美光科技公司 | Memory device parallelizer |
| CN109344108A (en) * | 2018-09-10 | 2019-02-15 | 普联技术有限公司 | A kind of Type-C interface equipment, communication means and communication system |
| CN109346883A (en) * | 2018-09-20 | 2019-02-15 | 合肥联宝信息技术有限公司 | A kind of system for realizing the positive anti-plug of Type-C interface |
| TWI691846B (en) * | 2018-10-04 | 2020-04-21 | 宏碁股份有限公司 | Electronic device and electronic system |
| CN212112455U (en) * | 2020-05-19 | 2020-12-08 | 广州视源电子科技股份有限公司 | Type-c interface circuit, chip and electronic equipment |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114095669A (en) * | 2021-10-20 | 2022-02-25 | 瑞芯微电子股份有限公司 | Multi-input multi-output video bridging chip |
| WO2023184064A1 (en) * | 2022-03-28 | 2023-10-05 | 京东方科技集团股份有限公司 | Data transfer method and apparatus, and computer-readable storage medium |
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