CN112711157B - Array substrate, array substrate manufacturing method and display panel - Google Patents

Array substrate, array substrate manufacturing method and display panel Download PDF

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Publication number
CN112711157B
CN112711157B CN202110005485.3A CN202110005485A CN112711157B CN 112711157 B CN112711157 B CN 112711157B CN 202110005485 A CN202110005485 A CN 202110005485A CN 112711157 B CN112711157 B CN 112711157B
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layer
hole
array substrate
electrode
planar
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CN112711157A (en
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黄建龙
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
    • G03F1/32—Attenuating PSM [att-PSM], e.g. halftone PSM or PSM having semi-transparent phase shift portion; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Abstract

The application discloses an array substrate, an array substrate manufacturing process method and a display panel, wherein an interlayer insulating layer covering a metal layer is replaced by a first flat layer, and a third hole and a fourth hole corresponding to a first hole and a second hole on the first flat layer are formed in a second flat layer, so that the second flat layer can share the same mask plate with the first flat layer when being perforated. Therefore, one mask plate can be reduced in the manufacturing process of the array substrate provided by the application, so that the production cost can be saved.

Description

Array substrate, array substrate manufacturing method and display panel
Technical Field
The application relates to the technical field of display, in particular to an array substrate, an array substrate manufacturing method and a display panel.
Background
In the last 20 years, the technology and market of liquid crystal displays (Liquid Crystal Display, LCD) has been rapidly developed, and a huge industry has been developed. It grows at a rate of 20% per year, and has now become the primary display device, one of the most important industry sectors in the electronics industry.
In the process of manufacturing a liquid crystal display panel, an exposure technology is generally used, and the exposure technology is to project a pattern on a mask plate onto a photoresist after illumination by utilizing illumination, so as to realize pattern transfer.
In the course of research and practice, the inventors of the present application have found that in the liquid crystal panel industry, the manufacturing cost of the mask plate is high, and the cost is high because eight to fourteen photomasks are generally required in the existing process architecture.
Disclosure of Invention
The application provides an array substrate, an array substrate manufacturing method and a display panel, wherein the same mask plate is shared in two photomask manufacturing processes, so that the cost can be saved.
The application provides an array substrate, comprising:
a semiconductor layer;
a gate insulating layer disposed on the semiconductor layer, the gate insulating layer covering the semiconductor layer;
a gate layer disposed on the gate insulating layer, the gate layer partially covering the gate insulating layer;
a first planarization layer disposed on the gate layer, the first planarization layer extending to the gate insulating layer, the first planarization layer being provided with a first hole and a second hole;
a metal layer disposed on the first planarization layer, the metal layer being connected to the semiconductor layer through the first and second holes;
a second planar layer disposed on the metal layer, the second planar layer extending to the first planar layer, the second planar layer being provided with third and fourth holes;
a first electrode layer disposed on the second flat layer, the first electrode layer partially covering the second flat layer, the first electrode layer being a common electrode layer and multiplexed as a driving electrode;
the passivation layer is arranged on the first electrode layer, covers the first electrode layer and is connected with the metal layer through the fourth hole, a through hole is arranged on the passivation layer corresponding to the fourth hole,
the second electrode layer is arranged on the passivation layer, the second electrode layer partially covers the passivation layer, the second electrode layer is connected with the metal layer through the through hole, and the second electrode layer is a pixel electrode layer and is multiplexed into an induction electrode;
the third hole is arranged corresponding to the first hole, and the fourth hole is arranged corresponding to the second hole.
Alternatively, in some embodiments of the application, the second planar layer has a thickness of five to ten times the thickness of the first planar layer.
Optionally, in some embodiments of the present application, the first planar layer has a thickness of 3000 a to 7000 a and the second planar layer has a thickness of 15000 a to 70000 a.
Optionally, in some embodiments of the present application, the light-shielding layer further includes a substrate, a light-shielding layer, and a buffer layer; the light shielding layer is arranged on the substrate, the buffer layer is arranged on the light shielding layer, and the buffer layer covers the light shielding layer and extends to the substrate; the semiconductor layer is disposed on the buffer layer.
Correspondingly, the application also provides a manufacturing method of the array substrate, which comprises the following steps:
providing a semiconductor layer;
providing a gate insulating layer on the semiconductor layer, the gate insulating layer covering the semiconductor layer;
providing a gate layer on the gate insulating layer, the gate layer partially covering the gate insulating layer;
providing a first planarization layer on the gate layer, the first planarization layer extending to the gate insulating layer;
setting a halftone mask plate on the first flat layer;
illuminating the first planar layer to provide a first aperture and a second aperture;
removing the half-tone mask plate, and arranging a metal layer on the first flat layer, wherein the metal layer is connected with the semiconductor layer through the first hole and the second hole;
providing a second planar layer on the metal layer, the second planar layer extending to the first planar layer;
setting a halftone mask plate on the second flat layer;
illuminating the second planar layer to provide a third aperture and a fourth aperture;
wherein the third hole is arranged corresponding to the first hole, and the fourth hole is arranged corresponding to the second hole;
the array substrate further comprises a first electrode layer, a passivation layer and a second electrode layer; the first electrode layer is arranged on the second flat layer, and the first electrode layer partially covers the second flat layer; the passivation layer is arranged on the first electrode layer, the passivation layer covers the first electrode layer and is connected with the metal layer through the fourth hole, a through hole is formed in the passivation layer corresponding to the fourth hole, the second electrode layer is arranged on the passivation layer, the second electrode layer partially covers the passivation layer, and the second electrode layer is connected with the metal layer through the through hole.
Alternatively, in some embodiments of the present application, the exposure degrees of the first hole and the second hole are set to be the same, and the exposure degrees of the third hole and the fourth hole are set to be the same.
Alternatively, in some embodiments of the application, the first and second apertures are provided with an exposure of 20 mj/cm 2 Up to 30 mj/cm 2 。
Alternatively, in some embodiments of the present application, the third and fourth apertures are provided with an exposure of 110mj/cm 2 Up to 220 mj/cm 2 。
Correspondingly, the application also provides a display panel which comprises an array substrate, a liquid crystal layer and a black photoresist layer; the liquid crystal layer is arranged on the second electrode layer; the black photoresist layer is arranged on the liquid crystal layer, the black photoresist layer at least covers the third hole and the fourth hole, and the array substrate is the array substrate.
According to the array substrate, the interlayer insulating layer covering the metal layer is replaced by the first flat layer, and the third hole and the fourth hole corresponding to the first hole and the second hole on the first flat layer are formed in the second flat layer, so that the second flat layer can share the same mask plate with the first flat layer when being perforated. Therefore, one mask plate can be reduced in the manufacturing process of the array substrate provided by the application, so that the production cost can be saved.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a first structure of an array substrate according to the present application;
FIG. 2 is a schematic diagram of a second structure of the array substrate according to the present application;
FIG. 3 is a schematic diagram of a third structure of the array substrate according to the present application;
FIG. 4 is a schematic flow chart of a method for manufacturing an array substrate according to the present application;
FIG. 5 is a schematic diagram of a step of disposing a halftone mask on a first planarization layer according to the present application;
FIG. 6 is a schematic diagram of the step of illuminating a first planar layer to provide a first aperture and a second aperture provided by the present application;
FIG. 7 is a schematic diagram of a step of disposing a halftone mask on a second planarization layer according to the present application;
FIG. 8 is a schematic diagram of the step of illuminating the second planar layer to provide third and fourth apertures provided by the present application;
fig. 9 is a schematic structural diagram of a display panel provided by the present application.
Detailed Description
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and description only, and is not intended to limit the application. In the present application, unless otherwise indicated, terms of orientation such as "upper" and "lower" are used to generally refer to the upper and lower positions of the device in actual use or operation, and specifically the orientation of the drawing figures; while "inner" and "outer" are for the outline of the device.
The application provides an array substrate, an array substrate manufacturing method and a display panel. The following will describe in detail.
Referring to fig. 1, fig. 1 is a schematic diagram of a first structure of an array substrate 10 according to the present application. The array substrate 10 includes a semiconductor layer 101, a gate insulating layer 102, a gate layer 103, a first planarization layer 104, a metal layer 105, and a second planarization layer 106. A gate insulating layer 102 is provided on the semiconductor layer 101, the gate insulating layer 102 covering the semiconductor layer 101. A gate layer 103 is disposed on the gate insulating layer 102, and the gate layer 103 partially covers the gate insulating layer 102. A first planarization layer 104 is disposed on the gate layer 103, the first planarization layer 104 extending to the gate insulating layer 102, the first planarization layer 104 being provided with a first hole 104a and a second hole 104b. A metal layer 105 is provided on the first planarization layer 104, and the metal layer 105 is connected to the semiconductor layer 101 through the first hole 104a and the second hole 104b. A second planarization layer 106 is disposed on the metal layer 105, the second planarization layer 106 extending to the first planarization layer 104, the second planarization layer 106 being provided with a third hole 106a and a fourth hole 106b. The third hole 106a corresponds to the first hole 104a, and the fourth hole 106b corresponds to the second hole 104b.
In the array substrate 10 provided by the application, the interlayer insulating layer covering the metal layer 105 is replaced by the first flat layer 104, and the third hole 106a and the fourth hole 106b corresponding to the first hole 104a and the second hole 104b on the first flat layer 104 are arranged on the second flat layer 106, so that the same mask plate can be shared with the first flat layer 104 when the second flat layer 106 is perforated. Therefore, one mask plate can be reduced in the manufacturing process of the array substrate 10 provided by the application, so that the production cost can be saved. In addition, the first flat layer is adopted to replace the interlayer insulating layer, so that the material cost can be reduced, the productivity can be saved, and the productivity can be improved by 1%.
The material used for the semiconductor layer 101 includes any one of amorphous Silicon (α -Si), low temperature polysilicon (Low Temperature Poly-Silicon, LTPS), and indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO). The technology for manufacturing the semiconductor layer 101 by adopting the alpha-Si is simple and mature, has low cost, and is suitable for large-size liquid crystal display (Liquid Crystal Display, LCD) panels and low-cost electrophoresis display (Electrophoretic Display, EPD) panels. The LTPS is formed by uniformly irradiating amorphous silicon with laser light, and then absorbing internal atoms by the amorphous silicon to generate energy level transition deformation to form a polycrystalline structure. The semiconductor layer 101 made of LTPS has higher resolution, faster reflection speed, and higher brightness. The semiconductor layer 101 manufactured by IGZO has high mobility, good uniformity and simple manufacturing process. The IGZO has good stability under illumination, has strong bending property, and is suitable for flexible display.
The metal layer 105 is made of any one of silver (Ag), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), copper (Cu), tungsten (W), and titanium (Ti). The silver, aluminum, copper and other metals have good conductivity and lower cost, and the production cost can be reduced while the conductivity is ensured.
Wherein the widths of the first, second, third and fourth holes 104a, 104b, 106a and 106b are 3 to 6 μm. Specifically, the widths of the first, second, third, and fourth holes 104a, 104b, 106a, and 106b are 3 μm, 4 μm, 5 μm, or 6 μm.
Referring to fig. 2, fig. 2 is a schematic diagram of a second structure of the array substrate 10 according to the present application. The array substrate 10 further includes a first electrode layer 107, a passivation layer 108, and a second electrode layer 109. The first electrode layer 107 is disposed on the second flat layer 106, and the first electrode layer 107 partially covers the second flat layer 106. A passivation layer 108 is disposed on the first electrode layer 107, the passivation layer 108 covers the first electrode layer 107 and is connected to the metal layer 105 through the fourth hole 106b, a via hole is disposed on the passivation layer 108 corresponding to the fourth hole 106b, a second electrode layer 109 is disposed on the passivation layer 108, the second electrode layer 109 partially covers the passivation layer 108, and the second electrode layer 109 is connected to the metal layer 105 through the via hole.
The material used for the first electrode layer 107 and the second electrode layer 109 includes any one of Indium Gallium Zinc Oxide (IGZO), indium Zinc Tin Oxide (IZTO), indium Gallium Zinc Tin Oxide (IGZTO), indium Tin Oxide (ITO), indium Zinc Oxide (IZO), indium Aluminum Zinc Oxide (IAZO), indium Gallium Tin Oxide (IGTO), or Antimony Tin Oxide (ATO). The material has good conductivity and transparency, and has small thickness, and the whole thickness of the display panel is not affected. Meanwhile, the electronic radiation, ultraviolet and infrared light harmful to human bodies can be reduced.
Specifically, the material used for the first electrode layer 107 and the second electrode layer 109 is Indium Tin Oxide (ITO), the first electrode layer 107 may be referred to as BITO (Back side Indium Tin Oxides) layer, and the second electrode layer 109 may be referred to as TITO (Top Indium Tin Oxides) layer. In some embodiments, when the array substrate 10 is applied to a liquid crystal display (Liquid Crystal Display, LCD), BITO is used as a common electrode layer and TITO is used as a pixel electrode layer for controlling liquid crystal deflection. In addition, BITO and TITO can be multiplexed into touch electrodes, BITO is used as a driving electrode, and TITO is used as an induction electrode. Since the voltage U between the driving electrode and the sensing electrode is unchanged, the capacitance c=q/U between the driving electrode and the sensing electrode. Therefore, when a finger approaches or touches the screen, a part of electric field energy Q between the driving electrode and the sensing electrode is shunted to the finger, and the capacitance C decreases without changing the voltage U, and the display panel employing the array substrate 10 is touch-operated according to this principle.
In the present application, a first electrode layer 107, a second electrode layer 109, and a passivation layer 108 are further disposed on the array substrate 10. As described above, when the width of the third hole 106a is 5 μm, since the third hole 106a is small, unevenness of the first electrode layer 107 at the position of the third hole 106a does not affect the liquid crystal display. In addition, after the second flat layer 106 is cured, some protrusions are easily formed by stress, and these protrusions often cause the first electrode layer 107 and the second electrode layer 109 to overlap to show dark spots. The array substrate 10 of the present application has the third hole 106a and the fourth hole 106b provided on the second flat layer 106, and the third hole 106a can enlarge the distance between the first electrode layer 107 and the second electrode layer 109, prevent the first electrode layer 107 and the second electrode layer 109 from overlapping, and reduce the display dark spot caused by the protrusion of the second flat layer 106.
Wherein the thickness of the second planarization layer 106 is five to ten times the thickness of the first planarization layer 104. Since the first planarization layer 104 is used for isolating the gate layer 103 and the metal layer 105, the second planarization layer 106 can isolate the metal layer 105 and the first electrode layer 107, and the second planarization layer 106 can planarize the array film layer, so as to reduce the problem of rotation disorder of the liquid crystal caused by uneven film layers of the array substrate 10. Thus, the second planar layer 106 may be thicker than the first planar layer 104, but an excessive increase in thickness may increase production costs. In order to achieve a better display effect without affecting the production cost, the thickness of the second flat layer 106 is set to five times the thickness of the first flat layer 104.
The thickness of the first planarization layer 104 is 3000 a to 7000 a, and the thickness of the second planarization layer 106 is 15000 a to 70000 a. Specifically, the thickness of the first planar layer 104 is 3000 a, 3500 a, 4000 a, 4500 a, 5000 a, 5500 a, 6000 a, 6500 a, or 7000 a. The second planar layer 106 has a thickness of 15000 a, 17500 a, 20000 a, 22500 a, 25000 a, 27500 a, 30000 a, 32500 a, 35000 a, 50000 a, 55000 a, 60000 a, 65000 a, or 70000 a.
Referring to fig. 3, fig. 3 is a schematic diagram of a third structure of the array substrate 10 according to the present application. The array substrate 10 further includes a substrate 110, a light shielding layer 111, and a buffer layer 112. The light shielding layer 111 is disposed on the substrate 110, the buffer layer 112 is disposed on the light shielding layer 111, and the buffer layer 112 covers the light shielding layer 111 and extends to the substrate 110. The semiconductor layer 101 is disposed on the buffer layer 112.
The substrate 110 refers to a base member for carrying the touch electrode structure. The substrate 110 is glass, functional glass (sensor glass), or a flexible substrate. The functional glass is obtained by sputtering a transparent metal oxide conductive film coating on ultrathin glass and performing high-temperature annealing treatment. The transparent metal oxide material may be any one of Indium Gallium Zinc Oxide (IGZO), indium Zinc Tin Oxide (IZTO), indium Gallium Zinc Tin Oxide (IGZTO), indium Tin Oxide (ITO), indium Zinc Oxide (IZO), indium Aluminum Zinc Oxide (IAZO), indium Gallium Tin Oxide (IGTO), or Antimony Tin Oxide (ATO). The material used for the flexible substrate is a polymer material, and specifically, the material used for the flexible substrate may be Polyimide (PI), polyethylene (PE), polypropylene (PP), polystyrene (PS), polyethylene terephthalate (Polyethylene glycol terephthalate, PET) or Polyethylene naphthalate (Polyethylene naphthalate two formic acid glycol ester, PEN). The polymer material has good flexibility, light weight and impact resistance, and is suitable for flexible display panels. Among them, polyimide can also achieve good heat resistance and stability.
The material of the light shielding layer 111 may be, for example, tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), titanium (Ti), copper-niobium (CuNb) alloy, or the like, or may be, for example, a stack of copper (Cu) and molybdenum (Mo), a stack of copper (Cu) and molybdenum-titanium (MoTi) alloy, a stack of copper (Cu) and titanium (Ti), a stack of aluminum (Al) and molybdenum (Mo), a stack of molybdenum (Mo) and tantalum (Ta), a stack of molybdenum (Mo) and tungsten (W), a stack of molybdenum (Mo) -aluminum (Al) -molybdenum (Mo), or the like. The light shielding layer 111 is disposed on the substrate 110, and the light shielding layer 111 is disposed corresponding to the gate layer 103 and covers at least a corresponding region of the gate layer 103. The light shielding layer 111 can reflect or absorb the ambient light and other light sources on the substrate 110 side, eliminate signal interference of the ambient light and other light sources, and can obviously reduce interference of the ambient light and other light sources on devices, and obviously improve the signal to noise ratio of the display panel.
The buffer layer 112 includes a silicon nitride compound layer, a silicon oxide compound layer, or a combination of the above layers, which are sequentially stacked, and the stacking manner of the buffer layer 112 is not a major point of protection of the present application, and thus is not shown in the drawings of the present application. The silicon nitride compound layer is made of silicon nitride compound (SiNx) and has a thickness of 40 nm-60 nm. The silicon oxide layer is made of silicon dioxide (SiO 2), and the thickness of the silicon oxide layer is 200 nm to 400 nm. Specifically, the thickness of the silicon nitride compound layer is 40 nm, 45 nm, 50 nm, 55 nm, or 60 nm. The thickness of the silicone compound is 200 nm, 250 nm, 300 nm, 350 nm or 400 nm.
Referring to fig. 4, fig. 4 is a schematic flow chart of a method for manufacturing an array substrate 10 according to the present application. The manufacturing method of the array substrate 10 specifically comprises the following steps:
201. a semiconductor layer 101 is provided.
202. A gate insulating layer 102 is provided over the semiconductor layer 101, and the gate insulating layer 102 covers the semiconductor layer 101.
203. A gate layer 103 is provided over the gate insulating layer 102, and the gate layer 103 partially covers the gate insulating layer 102.
204. A first planarization layer 104 is disposed on the gate layer 103, and the first planarization layer 104 extends to the gate insulating layer 102.
205. A halftone mask plate 10a is provided on the first planarization layer 104.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating a step of disposing a halftone mask plate 10a on a first planarization layer 104 according to the present application.
The Halftone Mask 10a of the present application is subjected to photolithography using a Halftone Mask (Halftone Mask) process, and the Halftone Mask 10a has a light-transmitting region and a semi-transmitting region, or semi-transmitting regions having different light transmittances. The semi-transparent region of the halftone mask plate 10a can change the light transmittance of the mask plate in the region by adjusting the gray value or the tone, and different light transmittances can form holes with different depths after exposure, the region with better light transmittance is deeper after exposure, the region with weaker light transmittance is deeper after exposure, and the depth of the hole formed after exposure is shallower, so that holes with different depths can be etched in different regions of the first planarization layer 104.
206. The first planar layer 104 is illuminated to provide a first aperture 104a and a second aperture 104b.
Referring to fig. 6, fig. 6 is a schematic diagram illustrating a step of illuminating the first planarization layer 104 to set the first hole 104a and the second hole 104b according to the present application. The arrows in fig. 6 illustrate the light rays.
207. The halftone mask plate 10a is removed, a metal layer 105 is provided on the first planarization layer 104, and the metal layer 105 is connected to the semiconductor layer 101 through the first hole 104a and the second hole 104b.
208. A second planarization layer 106 is disposed on the metal layer 105, the second planarization layer 106 extending to the first planarization layer 104.
209. A halftone mask plate 10a is provided on the second flat layer 106.
Referring to fig. 7, fig. 7 is a schematic diagram illustrating a step of disposing a halftone mask plate 10a on a second planarization layer 106 according to the present application.
The halftone mask 10a set in the step shown in fig. 7 and the halftone mask 10a set in fig. 5 are the same halftone mask 10a.
210. Illuminating the second planar layer 106 to provide a third aperture 106a and a fourth aperture 106b; the third hole 106a corresponds to the first hole 104a, and the fourth hole 106b corresponds to the second hole 104b.
Referring to fig. 8, fig. 8 is a schematic diagram illustrating a step of illuminating the second planarization layer 106 to provide the third hole 106a and the fourth hole 106b according to the present application. The arrows in fig. 8 illustrate light.
The exposure degrees of the first hole 104a and the second hole 104b are set to be the same, and the exposure degrees of the third hole 106a and the fourth hole 106b are set to be the same. Specifically, the exposure degree of the first holes 104a and the second holes 104b is set to 20 mj/cm 2 Up to 30 mj/cm 2 The third hole 106a and the fourth hole 106b were set to have an exposure of 110mj/cm 2 Up to 220 mj/cm 2 . Further, the exposure degree of the first holes 104a and the second holes 104b is set to be 20 mj/cm 2 、25 mj/cm 2 Or 30 mj/cm 2 The third hole 106a and the fourth hole 106b are set to have an exposure of 110mj/cm 2 、150 mj/cm 2 、175 mj/cm 2 、200 mj/cm 2 、210 mj/cm 2 、220 mj/cm 2 。
For example, when the thickness of the first planarization layer 104 is 6000A, an exposure of 25 mj/cm may be used 2 . When the thickness of the second planarization layer 106 is 25000A, an exposure of 110mj/cm may be used 2 . Since the difference in film thickness between the first planarization layer 104 and the second planarization layer 106 is large, when the first planarization layer 104 and the second planarization layer 106 are perforated by the same halftone mask plate 10a, the first planarization layer 104 is formed with the first holes 104a and the second holes 104b having the same depth by controlling the exposure degree, and the third holes 106a and the fourth holes 106b having different depths are formed in the second planarization layer 106.
In the method for manufacturing the array substrate 10, when the third hole 106a and the fourth hole 106b are formed in the second flat layer 106, the same halftone mask 10a is shared with the first hole 104a and the second hole 104b formed in the first flat layer 104. Therefore, in the method for manufacturing the array substrate 10 provided by the application, one mask plate can be reduced, so that the production cost can be saved.
Referring to fig. 9, fig. 9 is a schematic diagram of a structure of a display panel 100 according to the present application. The display panel 100 includes an array substrate 10, a liquid crystal layer 20, and a black photoresist layer 30. The liquid crystal layer 20 is disposed on the second electrode layer 109. The black resist layer 30 is disposed on the liquid crystal layer 20, and the black resist layer 30 covers at least the third hole 106a and the fourth hole 106b. In some embodiments, between the second electrode layer 109 and the liquid crystal layer 20, an organic layer 114 is also provided.
Wherein the organic layer 114 material is selected from one or more of Polyimide (PI), polyethylene naphthalate (Polyethylene naphthalate two formic acid glycol ester, PEN), polyethylene terephthalate (polyethylene glycol terephthalate, PET), polycarbonate (PC), polyetherimide (PEI) and polyethersulfone (Polyether sulfone, PES).
Since the Black Matrix layer 30 (BM) covers at least the third hole 106a and the fourth hole 106b, it is possible to prevent the influence of the disturbance of the liquid crystal at the positions corresponding to the third hole 106a and the fourth hole 106b on the display of the pixel unit, and to ensure the display effect of the display panel 100.
The display panel 100 provided by the present application may be at least one of a smart phone (smart phone), a tablet computer (tablet personal computer), a mobile phone (mobile phone), a video phone, an electronic book reader (e-book reader), a desktop computer (desktop PC), a laptop PC, a netbook computer (netbook computer), a workstation (workstation), a server, a personal digital assistant (personal digital assistant), a portable media player (portable multimedia player), an MP3 player, a mobile medical machine, a camera, a game machine, a digital camera, a car navigator, an electronic billboard, an automated teller machine, or a web equipment (mobile device).
It should be noted that the display panel 100 may further include other components, and the array substrate 10 is the above-described array substrate 10. Other components and arrangements are well known to those skilled in the art and will not be described in detail herein.
The display panel 100 provided by the application comprises an array substrate 10. In the array substrate 10, the interlayer insulating layer covering the metal layer is replaced with a first flat layer, and a third hole and a fourth hole corresponding to the first hole and the second hole on the first flat layer are formed on the second flat layer, so that the same mask plate can be shared with the first flat layer when the second flat layer is perforated. Therefore, one mask plate can be reduced in the manufacturing process of the array substrate provided by the application, so that the production cost can be saved. In addition, the first flat layer is adopted to replace the interlayer insulating layer, so that the material cost can be reduced, the productivity can be saved, and the productivity can be improved by 1%.
The above description is provided for the details of an array substrate, a manufacturing method of the array substrate and a display panel, and specific examples are applied to illustrate the principles and embodiments of the present application, and the above examples are only used to help understand the method and core ideas of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application.

Claims (9)

1. The array substrate manufacturing method is characterized by comprising the following steps:
providing a semiconductor layer;
providing a gate insulating layer on the semiconductor layer, the gate insulating layer covering the semiconductor layer;
providing a gate layer on the gate insulating layer, the gate layer partially covering the gate insulating layer;
providing a first planarization layer on the gate layer, the first planarization layer extending to the gate insulating layer;
setting a halftone mask plate on the first flat layer;
illuminating the first planar layer to provide a first aperture and a second aperture;
removing the half-tone mask plate, and arranging a metal layer on the first flat layer, wherein the metal layer is connected with the semiconductor layer through the first hole and the second hole;
providing a second planar layer on the metal layer, the second planar layer extending to the first planar layer;
setting a halftone mask plate on the second flat layer;
illuminating the second planar layer to provide a third aperture and a fourth aperture; the third hole is arranged corresponding to the first hole, the fourth hole is arranged corresponding to the second hole, and the second flat layer is shared with the first hole and the second hole by the same halftone mask plate when the third hole and the fourth hole are arranged;
the array substrate further comprises a first electrode layer, a passivation layer and a second electrode layer; the first electrode layer is arranged on the second flat layer, and the first electrode layer partially covers the second flat layer; the passivation layer is arranged on the first electrode layer, the passivation layer covers the first electrode layer and is connected with the metal layer through the fourth hole, a through hole is formed in the passivation layer corresponding to the fourth hole, the second electrode layer is arranged on the passivation layer, the second electrode layer partially covers the passivation layer, and the second electrode layer is connected with the metal layer through the through hole.
2. The method of claim 1, wherein the first hole and the second hole are set to have the same exposure, and the third hole and the fourth hole are set to have the same exposure.
3. The method of claim 2, wherein the first and second holes are provided with an exposure of 20 mj/cm 2 Up to 30 mj/cm 2 。
4. The method of claim 2, whereinWherein the third and fourth holes are provided with an exposure of 110mj/cm 2 Up to 220 mj/cm 2 。
5. An array substrate, wherein the array substrate is formed by the array substrate manufacturing method according to any one of claims 1 to 4, and the array substrate comprises:
a semiconductor layer;
a gate insulating layer disposed on the semiconductor layer, the gate insulating layer covering the semiconductor layer;
a gate layer disposed on the gate insulating layer, the gate layer partially covering the gate insulating layer;
a first planarization layer disposed on the gate layer, the first planarization layer extending to the gate insulating layer, the first planarization layer being provided with a first hole and a second hole;
a metal layer disposed on the first planarization layer, the metal layer being connected to the semiconductor layer through the first and second holes;
a second planar layer disposed on the metal layer, the second planar layer extending to the first planar layer, the second planar layer being provided with third and fourth holes;
a first electrode layer disposed on the second flat layer, the first electrode layer partially covering the second flat layer, the first electrode layer being a common electrode layer and multiplexed as a driving electrode;
the passivation layer is arranged on the first electrode layer, covers the first electrode layer and is connected with the metal layer through the fourth hole, a through hole is arranged on the passivation layer corresponding to the fourth hole,
the second electrode layer is arranged on the passivation layer, the second electrode layer partially covers the passivation layer, the second electrode layer is connected with the metal layer through the through hole, and the second electrode layer is a pixel electrode layer and is multiplexed into an induction electrode;
the third hole is arranged corresponding to the first hole, and the fourth hole is arranged corresponding to the second hole.
6. The array substrate of claim 5, wherein the second planar layer has a thickness of five to ten times the thickness of the first planar layer.
7. The array substrate of claim 6, wherein the first planar layer has a thickness of 3000 a to 7000 a and the second planar layer has a thickness of 15000 a to 70000 a.
8. The array substrate of claim 5, further comprising a substrate, a light shielding layer, and a buffer layer; the light shielding layer is arranged on the substrate, the buffer layer is arranged on the light shielding layer, and the buffer layer covers the light shielding layer and extends to the substrate; the semiconductor layer is disposed on the buffer layer.
9. The display panel is characterized by comprising an array substrate, a liquid crystal layer and a black photoresist layer; the liquid crystal layer is arranged on the second electrode layer; the black photoresist layer is arranged on the liquid crystal layer, at least covers the third hole and the fourth hole, and the array substrate is the array substrate according to any one of claims 5 to 8.
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KR20110138964A (en) * 2010-06-22 2011-12-28 엘지디스플레이 주식회사 Array substrate for fringe field switching mode liquid crystal display device and method of fabricating the same
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