CN112711157A - Array substrate, array substrate manufacturing method and display panel - Google Patents

Array substrate, array substrate manufacturing method and display panel Download PDF

Info

Publication number
CN112711157A
CN112711157A CN202110005485.3A CN202110005485A CN112711157A CN 112711157 A CN112711157 A CN 112711157A CN 202110005485 A CN202110005485 A CN 202110005485A CN 112711157 A CN112711157 A CN 112711157A
Authority
CN
China
Prior art keywords
layer
hole
array substrate
planarization
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110005485.3A
Other languages
Chinese (zh)
Other versions
CN112711157B (en
Inventor
黄建龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to CN202110005485.3A priority Critical patent/CN112711157B/en
Publication of CN112711157A publication Critical patent/CN112711157A/en
Application granted granted Critical
Publication of CN112711157B publication Critical patent/CN112711157B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
    • G03F1/32—Attenuating PSM [att-PSM], e.g. halftone PSM or PSM having semi-transparent phase shift portion; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Abstract

The application discloses an array substrate, an array substrate manufacturing method and a display panel. Therefore, one mask plate can be reduced in the array substrate manufacturing process, and the production cost can be further saved.

Description

Array substrate, array substrate manufacturing method and display panel
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to an array substrate, an array substrate manufacturing method, and a display panel.
Background
Liquid Crystal Display (LCD) technology and the market have gained rapid growth over as short as 20 years and have formed a huge industry. It has grown at a rate of 20% per year, has now become the primary display device, and is one of the most important sectors of the electronics industry.
In the manufacturing process of the liquid crystal display panel, an exposure technique is generally used, and the exposure technique is a technique of projecting a pattern on a mask plate onto a photoresist by illumination to transfer the pattern.
In the research and practice process, the inventor of the present application finds that in the liquid crystal panel industry, the manufacturing cost of the mask plate is high, and the existing process architecture generally needs eight to fourteen photomasks, so that the cost is high.
Disclosure of Invention
The application provides an array substrate, an array substrate manufacturing method and a display panel, wherein the same mask plate is shared in two photomask manufacturing processes, and cost can be saved.
The application provides an array substrate, includes:
a semiconductor layer;
a gate insulating layer disposed on the semiconductor layer, the gate insulating layer covering the semiconductor layer;
a gate layer disposed on the gate insulating layer, the gate layer partially covering the gate insulating layer;
a first planarization layer disposed on the gate electrode layer, the first planarization layer extending to the gate insulating layer, the first planarization layer being provided with a first hole and a second hole;
a metal layer disposed on the first planarization layer, the metal layer being connected to the semiconductor layer through the first and second holes;
a second planar layer disposed on the metal layer, the second planar layer extending to the first planar layer, the second planar layer being provided with a third aperture and a fourth aperture;
wherein the third hole is disposed corresponding to the first hole, and the fourth hole is disposed corresponding to the second hole.
Optionally, in some embodiments of the present application, the thickness of the second planarization layer is five to ten times the thickness of the first planarization layer.
Optionally, in some embodiments of the present application, the first planarization layer has a thickness of
Figure BDA0002883160380000021
To
Figure BDA0002883160380000022
The second flat layer has a thickness of
Figure BDA0002883160380000023
To
Figure BDA0002883160380000024
Optionally, in some embodiments of the present application, the display device further includes a first electrode layer, a passivation layer, and a second electrode layer; the first electrode layer is arranged on the second flat layer, and the first electrode layer partially covers the second flat layer; the passivation layer is arranged on the first electrode layer, covers the first electrode layer and is connected with the metal layer through the fourth hole, a through hole is formed in the passivation layer corresponding to the fourth hole, the second electrode layer is arranged on the passivation layer, the first electrode layer partially covers the passivation layer, and the second electrode layer is connected with the metal layer through the through hole.
Optionally, in some embodiments of the present application, the display device further includes a substrate, a light-shielding layer, and a buffer layer; the light shielding layer is arranged on the substrate, the buffer layer is arranged on the light shielding layer, and the buffer layer covers the light shielding layer and extends to the substrate; the semiconductor layer is disposed on the buffer layer.
Correspondingly, the application also provides an array substrate manufacturing method, which comprises the following steps:
providing a semiconductor layer;
providing a gate insulating layer on the semiconductor layer, the gate insulating layer covering the semiconductor layer;
providing a gate layer on the gate insulating layer, the gate layer partially covering the gate insulating layer;
providing a first planarization layer on the gate layer, the first planarization layer extending to the gate insulating layer;
a halftone mask plate is arranged on the first flat layer;
illuminating the first planarization layer to provide a first aperture and a second aperture;
moving out the halftone mask plate, and arranging a metal layer on the first flat layer, wherein the metal layer is connected with the semiconductor layer through the first hole and the second hole;
disposing a second planar layer on the metal layer, the second planar layer extending to the first planar layer;
a halftone mask plate is arranged on the second flat layer;
illuminating the second planar layer to provide a third aperture and a fourth aperture;
wherein the third hole is disposed corresponding to the first hole, and the fourth hole is disposed corresponding to the second hole.
Optionally, in some embodiments of the present application, the exposure of the first hole is set to be the same as the exposure of the second hole, and the exposure of the third hole is set to be the same as the exposure of the fourth hole.
Optionally, in some embodiments of the present application, the exposure level of the first hole and the second hole is set to 20mj/cm2To 30mj/cm2。
Optionally, in some embodiments of the present application, the exposure of the third hole and the fourth hole is set to 110mj/cm2To 220mj/cm2。
Correspondingly, the application also provides a display panel, which comprises an array substrate, a liquid crystal layer and a black light resistance layer; the liquid crystal layer is arranged on the second electrode layer; the black light resistance layer is arranged on the liquid crystal layer, the black light resistance layer at least covers the third hole and the fourth hole, and the array substrate is the array substrate.
The array substrate comprises an array substrate body, wherein the array substrate body is provided with a first flat layer, an interlayer insulating layer covering a metal layer is replaced by the first flat layer, a third hole and a fourth hole are formed in the second flat layer, the third hole and the fourth hole correspond to the first hole and the second hole in the first flat layer, and the second flat layer and the first flat layer can share the same mask plate when the second flat layer is punched. Therefore, one mask plate can be reduced in the array substrate manufacturing process, and the production cost can be further saved.
Drawings
In order to more clearly illustrate the technical solutions in the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic view of a first structure of an array substrate provided in the present application;
fig. 2 is a schematic view of a second structure of the array substrate provided in the present application;
FIG. 3 is a schematic diagram of a third structure of the array substrate provided in the present application;
FIG. 4 is a schematic flow chart illustrating a method for fabricating an array substrate according to the present disclosure;
FIG. 5 is a schematic diagram of a halftone mask step provided herein on a first planarization layer;
FIG. 6 is a schematic illustration of the step of illuminating the first planarization layer to provide a first aperture and a second aperture provided herein;
FIG. 7 is a schematic diagram of the step of providing a halftone mask on the second planarization layer provided herein;
FIG. 8 is a schematic illustration of the step of illuminating the second planar layer to provide a third aperture and a fourth aperture provided herein;
fig. 9 is a schematic structural diagram of a display panel provided in the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings in the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The application provides an array substrate, an array substrate manufacturing method and a display panel. The following are detailed below.
Referring to fig. 1, fig. 1 is a schematic view illustrating a first structure of an array substrate 10 according to the present application. The array substrate 10 includes a semiconductor layer 101, a gate insulating layer 102, a gate layer 103, a first planarization layer 104, a metal layer 105, and a second planarization layer 106. A gate insulating layer 102 is disposed on the semiconductor layer 101, and the gate insulating layer 102 covers the semiconductor layer 101. The gate layer 103 is disposed on the gate insulating layer 102, and the gate layer 103 partially covers the gate insulating layer 102. The first planarization layer 104 is disposed on the gate layer 103, the first planarization layer 104 extends to the gate insulating layer 102, and the first planarization layer 104 is provided with a first hole 104a and a second hole 104 b. A metal layer 105 is disposed on the first planarization layer 104, and the metal layer 105 is connected to the semiconductor layer 101 through the first and second holes 104a and 104 b. The second planarization layer 106 is disposed on the metal layer 105, the second planarization layer 106 extends to the first planarization layer 104, and the second planarization layer 106 is provided with a third hole 106a and a fourth hole 106 b. The third hole 106a is disposed corresponding to the first hole 104a, and the fourth hole 106b is disposed corresponding to the second hole 104 b.
In the array substrate 10 provided by the present application, the interlayer insulating layer covering the metal layer 105 is replaced by the first flat layer 104, and the second flat layer 106 is provided with the third hole 106a and the fourth hole 106b corresponding to the first hole 104a and the second hole 104b on the first flat layer 104, so that the second flat layer 106 and the first flat layer 104 can share the same mask plate when the holes are punched. Therefore, one mask plate can be reduced in the manufacturing process of the array substrate 10 provided by the present application, and the production cost can be further saved. In addition, the first flat layer is adopted to replace an interlayer insulating layer, so that the material cost can be reduced, the productivity is saved, and the productivity is improved by 1%.
The semiconductor layer 101 is made of any one of amorphous Silicon (α -Si), Low Temperature Polysilicon (LTPS), and Indium Gallium Zinc Oxide (IGZO). The technology for manufacturing the semiconductor layer 101 by using α -Si is simple and mature, has low cost, and is suitable for large-sized Liquid Crystal Display (LCD) panels and low-price electrophoretic Display (EPD) panels. The LTPS is formed by that amorphous silicon absorbs internal atoms to generate energy level transition deformation after being uniformly irradiated by laser light to form a polycrystalline structure. The semiconductor layer 101 made of LTPS has higher resolution, faster reflection speed, and higher luminance. The semiconductor layer 101 manufactured by IGZO has high mobility, good uniformity, and a simple manufacturing process. The IGZO has good stability under light irradiation, and the IGZO has strong bending properties, and is suitable for flexible display.
The metal layer 105 is made of any one of silver (Ag), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), copper (Cu), tungsten (W), and titanium (Ti). The silver, aluminum, copper and other metals have good conductivity and lower cost, and the production cost can be reduced while the conductivity is ensured.
Wherein the widths of the first, second, third and fourth holes 104a, 104b, 106a and 106b are 3 to 6 μm. Specifically, the widths of the first hole 104a, the second hole 104b, the third hole 106a, and the fourth hole 106b are 3 μm, 4 μm, 5 μm, or 6 μm.
Referring to fig. 2, fig. 2 is a schematic diagram of a second structure of the array substrate 10 provided in the present application. The array substrate 10 further includes a first electrode layer 107, a passivation layer 108, and a second electrode layer 109. The first electrode layer 107 is disposed on the second planarization layer 106, and the first electrode layer 107 partially covers the second planarization layer 106. A passivation layer 108 is disposed on the first electrode layer 107, the passivation layer 108 covers the first electrode layer 107 and is connected to the metal layer 105 through the fourth hole 106b, a through hole is disposed on the passivation layer 108 corresponding to the fourth hole 106b, a second electrode layer 109 is disposed on the passivation layer 108, the first electrode layer 107 partially covers the passivation layer 108, and the second electrode layer 109 is connected to the metal layer 105 through the through hole.
The material used for the first electrode layer 107 and the second electrode layer 109 includes any one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), Indium Gallium Zinc Tin Oxide (IGZTO), Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Aluminum Zinc Oxide (IAZO), Indium Gallium Tin Oxide (IGTO), or Antimony Tin Oxide (ATO). The materials have good conductivity and transparency, and are small in thickness, so that the whole thickness of the display panel cannot be influenced. Meanwhile, the electronic radiation and ultraviolet and infrared light which are harmful to human bodies can be reduced.
Specifically, the material used for the first electrode layer 107 and the second electrode layer 109 is Indium Tin Oxide (ITO), the first electrode layer 107 may be referred to as a bito (back side Indium Tin oxides) layer, and the second electrode layer 109 may be referred to as a tito (topind titanium oxides) layer. In some embodiments, the array substrate 10 is applied to a Liquid Crystal Display (LCD), and the BITO is used as a common electrode layer and the TITO is used as a pixel electrode layer for controlling Liquid Crystal deflection. In addition, BITO and TITO can be multiplexed into a touch electrode, BITO is used as a driving electrode, and TITO is used as a sensing electrode. Since the voltage U between the driving electrode and the sensing electrode is constant, the capacitance C between the driving electrode and the sensing electrode is Q/U. Therefore, when a finger approaches or touches the screen, a part of electric field energy Q between the driving electrode and the sensing electrode is shunted to the finger, and the capacitance C is reduced under the condition that the voltage U is not changed, so that the touch operation is performed on the display panel adopting the array substrate 10 according to the principle.
In this application, the array substrate 10 is further provided with a first electrode layer 107, a second electrode layer 109 and a passivation layer 108. As described above, when the width of the third hole 106a is 5 μm, since the third hole 106a is small, unevenness of the first electrode layer 107 at the position of the third hole 106a does not affect the liquid crystal display. In addition, after the second planarization layer 106 is cured, some bumps are easily formed due to stress, and these bumps often cause the first electrode layer 107 and the second electrode layer 109 to overlap and cause dark spots. In the array substrate 10 of the present application, the third hole 106a and the fourth hole 106b are disposed on the second flat layer 106, and the third hole 106a can enlarge the distance between the first electrode layer 107 and the second electrode layer 109, thereby preventing the first electrode layer 107 and the second electrode layer 109 from overlapping, and reducing the display dark spots caused by the protrusion of the second flat layer 106.
Wherein the thickness of the second planarization layer 106 is five to ten times the thickness of the first planarization layer 104. Since the first planarization layer 104 serves to isolate the gate layer 103 from the metal layer 105, and the second planarization layer 106 can isolate the metal layer 105 from the first electrode layer 107, on the one hand, and planarize the array film layer on the other hand, the problem of liquid crystal rotation disorder caused by unevenness of each film layer of the array substrate 10 is reduced. Thus, the second planar layer 106 may be thicker than the first planar layer 104, but an excessive increase in thickness may increase production costs. In order to achieve a better display effect without affecting the production cost, the thickness of the second planarization layer 106 is set to be five times as large as that of the first planarization layer 104.
Wherein the thickness of the first planarization layer 104 is
Figure BDA0002883160380000061
To
Figure BDA0002883160380000062
The second planarization layer 106 has a thickness of
Figure BDA0002883160380000071
To
Figure BDA0002883160380000072
Specifically, the first planarization layer 104 has a thickness of
Figure BDA0002883160380000073
Figure BDA0002883160380000074
Or
Figure BDA0002883160380000075
The second planarization layer 106 has a thickness of
Figure BDA0002883160380000076
Figure BDA0002883160380000077
Or
Figure BDA0002883160380000078
Referring to fig. 3, fig. 3 is a schematic view of a third structure of the array substrate 10 provided in the present application. The array substrate 10 further includes a substrate 110, a light-shielding layer 111 and a buffer layer 112. The light-shielding layer 111 is disposed on the substrate 110, the buffer layer 112 is disposed on the light-shielding layer 111, and the buffer layer 112 covers the light-shielding layer 111 and extends to the substrate 110. The semiconductor layer 101 is disposed on the buffer layer 112.
The substrate 110 refers to a base member for carrying the touch electrode structure. The substrate 110 is glass, functional glass (sensor glass), or a flexible substrate. The functional glass is obtained by sputtering a transparent metal oxide conductive film coating on the ultrathin glass and carrying out high-temperature annealing treatment. The transparent metal oxide may be any one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), Indium Gallium Zinc Tin Oxide (IGZTO), Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Aluminum Zinc Oxide (IAZO), Indium Gallium Tin Oxide (IGTO), or Antimony Tin Oxide (ATO). The flexible substrate is made of a polymer material, and specifically, the flexible substrate may be made of Polyimide (PI), Polyethylene (PE), Polypropylene (PP), Polystyrene (PS), Polyethylene terephthalate (PET), or Polyethylene naphthalate (PEN). The polymer material has good flexibility, light weight and impact resistance, and is suitable for flexible display panels. Among them, polyimide can also achieve good heat resistance and stability.
The material of the light-shielding layer 111 may be, for example, tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), titanium (Ti), a copper niobium (CuNb) alloy, or the like, or may be, for example, a stack of copper (Cu) and molybdenum (Mo), a stack of copper (Cu) and molybdenum titanium (MoTi), a stack of aluminum (Al) and molybdenum (Mo), a stack of molybdenum (Mo) and tantalum (Ta), a stack of molybdenum (Mo) and tungsten (W), a stack of molybdenum (Mo) -aluminum (Al) -molybdenum (Mo), or the like. The light-shielding layer 111 is disposed on the substrate 110, and the light-shielding layer 111 is disposed corresponding to the gate layer 103 and covers at least a region corresponding to the gate layer 103. The light shielding layer 111 can reflect or absorb the ambient light and other light sources on the substrate 110 side, so as to eliminate signal interference of the ambient light and other light sources, significantly reduce interference of the ambient light and other light sources to the device, and significantly improve the signal-to-noise ratio of the display panel.
The buffer layer 112 includes a silicon nitride compound layer, a silicon oxide compound layer, or a combination of the above layers, which are sequentially stacked, and the stacking manner of the buffer layer 112 is not important for protection of the present application, and thus is not shown in the drawings of the present application. The silicon nitride compound layer is made of silicon nitride compound (SiNx), and the thickness of the silicon nitride compound layer is 40 nm-60 nm. The material used for the silicon oxide layer is silicon dioxide (SiO2), and the thickness of the silicon oxide layer is 200nm to 400 nm. Specifically, the thickness of the silicon nitride compound layer is 40nm, 45nm, 50nm, 55nm, or 60 nm. The thickness of the silicon-oxygen compound is 200nm, 250nm, 300nm, 350nm or 400 nm.
Referring to fig. 4, fig. 4 is a schematic flow chart of a method for manufacturing the array substrate 10 according to the present application. The manufacturing method of the array substrate 10 specifically includes the following steps:
201. a semiconductor layer 101 is provided.
202. A gate insulating layer 102 is provided over the semiconductor layer 101, and the gate insulating layer 102 covers the semiconductor layer 101.
203. A gate layer 103 is disposed on the gate insulating layer 102, the gate layer 103 partially covering the gate insulating layer 102.
204. A first planarization layer 104 is disposed on the gate layer 103, the first planarization layer 104 extending to the gate insulating layer 102.
205. A halftone mask plate 10a is provided on the first flat layer 104.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating a step of disposing a halftone mask blank 10a on the first flat layer 104 according to the present application.
In the present application, the Halftone Mask 10a is subjected to photolithography by using a Halftone Mask (Halftone Mask) process, and the Halftone Mask 10a has a light-transmitting region and a semi-light-transmitting region, or semi-light-transmitting regions with different transmittances. The half-tone mask plate 10a can change the light transmittance of the mask plate in the semi-light-transmitting area by adjusting the gray value or tone, different light transmittances can form holes with different depths when the light intensities of the light transmittances are different after exposure, the better the light transmittance is, the deeper the depth of the formed hole after exposure is, the shallower the depth of the formed hole after exposure is at the position with the weaker light transmittance, and thus, the holes with different depths can be etched in different areas of the first flat layer 104.
206. The first planarization layer 104 is illuminated to dispose the first hole 104a and the second hole 104 b.
Referring to fig. 6, fig. 6 is a schematic diagram illustrating a step of illuminating the first planarization layer 104 to form the first hole 104a and the second hole 104 b. The arrows in fig. 6 illustrate the light rays.
207. The halftone mask plate 10a is removed, the metal layer 105 is provided on the first planarization layer 104, and the metal layer 105 is connected to the semiconductor layer 101 through the first holes 104a and the second holes 104 b.
208. A second planarization layer 106 is disposed on the metal layer 105, the second planarization layer 106 extending to the first planarization layer 104.
209. A halftone mask plate 10a is provided on the second flat layer 106.
Referring to fig. 7, fig. 7 is a schematic diagram of a step of disposing a halftone mask blank 10a on the second flat layer 106 according to the present application.
Note that the halftone mask plate 10a provided in the step shown in fig. 7 is the same halftone mask plate 10a as the halftone mask plate 10a provided in fig. 5.
210. Illuminating the second planarization layer 106 to dispose the third hole 106a and the fourth hole 106 b; the third hole 106a is disposed corresponding to the first hole 104a, and the fourth hole 106b is disposed corresponding to the second hole 104 b.
Referring to fig. 8, fig. 8 is a schematic diagram illustrating a step of illuminating the second planarization layer 106 to dispose the third hole 106a and the fourth hole 106 b. The arrows in fig. 8 illustrate the light rays.
Wherein the exposure level of the first hole 104a and the second hole 104b are set to be the same, and the exposure level of the third hole 106a and the fourth hole 106b are set to be the same. Utensil for cleaning buttockIn particular, the first hole 104a and the second hole 104b are set to have an exposure of 20mj/cm2To 30mj/cm2Setting the exposure of the third hole 106a and the fourth hole 106b to 110mj/cm2To 220mj/cm2. Further, the exposure levels of the first hole 104a and the second hole 104b were set to 20mj/cm2、25mj/cm2Or 30mj/cm2Setting the exposure of the third hole 106a and the fourth hole 106b to 110mj/cm2、150mj/cm2、175mj/cm2、200mj/cm2、210mj/cm2、220mj/cm2。
For example, when the first planarization layer 104 has a thickness of
Figure BDA0002883160380000091
When the exposure is 25mj/cm2. When the thickness of the second planarization layer 106 is
Figure BDA0002883160380000092
When the exposure is 110mj/cm, the exposure can be used2. Since the difference in film thickness between the first and second planarization layers 104 and 106 is large, when the same halftone mask blank 10a is used to punch the first and second planarization layers 104 and 106, the exposure is controlled so that the first planarization layer 104 has the first and second holes 104a and 104b with the same depth, and the second planarization layer 106 has the third and fourth holes 106a and 106b with different depths.
In the array substrate 10 manufacturing method adopted in the present application, when the third hole 106a and the fourth hole 106b are provided in the second flat layer 106, the same halftone mask plate 10a is shared with the first hole 104a and the second hole 104b provided in the first flat layer 104. Therefore, one mask plate can be reduced in the array substrate 10 processing method provided by the present application, and the production cost can be further saved.
Please refer to fig. 9, wherein fig. 9 is a schematic structural diagram of the display panel 100 according to the present application. The display panel 100 includes an array substrate 10, a liquid crystal layer 20, and a black photoresist layer 30. The liquid crystal layer 20 is disposed on the second electrode layer 109. The black photoresist layer 30 is disposed on the liquid crystal layer 20, and the black photoresist layer 30 covers at least the third hole 106a and the fourth hole 106 b. In some embodiments, between the second electrode layer 109 and the liquid crystal layer 20, an organic layer 114 is further disposed.
The organic layer 114 is made of one or more materials selected from Polyimide (PI), Polyethylene naphthalate (PEN), Polyethylene terephthalate (PET), Polycarbonate (PC), Polyetherimide (PEI), and Polyethersulfone (PES).
Since the Black Matrix (BM) covers at least the third hole 106a and the fourth hole 106b, the influence of the disturbance of the liquid crystal on the display of the pixel unit at the corresponding positions of the third hole 106a and the fourth hole 106b can be prevented, and the display effect of the display panel 100 can be ensured.
The display panel 100 provided in the present application may be at least one of a smart phone (smartphone), a tablet personal computer (tablet personal computer), a mobile phone (mobile phone), a video phone, an electronic book reader (e-book reader), a desktop computer (desktop PC), a laptop computer (laptop PC), a netbook computer (netbook computer), a workstation (workstation), a server, a personal digital assistant (personal digital assistant), a portable media player (portable multimedia player), an MP3 player, a mobile medical machine, a camera, a game machine, a digital camera, a car navigation device, an electronic billboard, an automatic teller machine, or a wearable device (wearable device).
The display panel 100 may further include other components, and the array substrate 10 is the above-described array substrate 10. Other components and arrangements are well known to those skilled in the art and will not be described in detail herein.
The present application provides a display panel 100 including an array substrate 10. In the array substrate 10, the interlayer insulating layer covering the metal layer is replaced with the first flat layer, and the second flat layer is provided with the third hole and the fourth hole corresponding to the first hole and the second hole in the first flat layer, so that the second flat layer and the first flat layer can share the same mask plate when the second flat layer is punched. Therefore, one mask plate can be reduced in the array substrate manufacturing process, and the production cost can be further saved. In addition, the first flat layer is adopted to replace an interlayer insulating layer, so that the material cost can be reduced, the productivity is saved, and the productivity is improved by 1%.
The array substrate, the array substrate manufacturing method and the display panel provided by the present application are introduced in detail, and specific examples are applied herein to explain the principle and the implementation of the present application, and the description of the above embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. An array substrate, comprising:
a semiconductor layer;
a gate insulating layer disposed on the semiconductor layer, the gate insulating layer covering the semiconductor layer;
a gate layer disposed on the gate insulating layer, the gate layer partially covering the gate insulating layer;
a first planarization layer disposed on the gate electrode layer, the first planarization layer extending to the gate insulating layer, the first planarization layer being provided with a first hole and a second hole;
a metal layer disposed on the first planarization layer, the metal layer being connected to the semiconductor layer through the first and second holes;
a second planar layer disposed on the metal layer, the second planar layer extending to the first planar layer, the second planar layer being provided with a third aperture and a fourth aperture;
wherein the third hole is disposed corresponding to the first hole, and the fourth hole is disposed corresponding to the second hole.
2. The array substrate of claim 1, wherein the thickness of the second planarization layer is five to ten times the thickness of the first planarization layer.
3. The array substrate of claim 2, wherein the first planarization layer has a thickness of
Figure FDA0002883160370000011
To
Figure FDA0002883160370000012
The second flat layer has a thickness of
Figure FDA0002883160370000013
To
Figure FDA0002883160370000014
4. The array substrate of claim 1, further comprising a first electrode layer, a passivation layer, a second electrode layer; the first electrode layer is arranged on the second flat layer, and the first electrode layer partially covers the second flat layer; the passivation layer is arranged on the first electrode layer, covers the first electrode layer and is connected with the metal layer through the fourth hole, a through hole is formed in the passivation layer corresponding to the fourth hole, the second electrode layer is arranged on the passivation layer, the first electrode layer partially covers the passivation layer, and the second electrode layer is connected with the metal layer through the through hole.
5. The array substrate of claim 1, further comprising a substrate, a light-shielding layer and a buffer layer; the light shielding layer is arranged on the substrate, the buffer layer is arranged on the light shielding layer, and the buffer layer covers the light shielding layer and extends to the substrate; the semiconductor layer is disposed on the buffer layer.
6. A method for manufacturing an array substrate includes:
providing a semiconductor layer;
providing a gate insulating layer on the semiconductor layer, the gate insulating layer covering the semiconductor layer;
providing a gate layer on the gate insulating layer, the gate layer partially covering the gate insulating layer;
providing a first planarization layer on the gate layer, the first planarization layer extending to the gate insulating layer;
a halftone mask plate is arranged on the first flat layer;
illuminating the first planarization layer to provide a first aperture and a second aperture;
moving out the halftone mask plate, and arranging a metal layer on the first flat layer, wherein the metal layer is connected with the semiconductor layer through the first hole and the second hole;
disposing a second planar layer on the metal layer, the second planar layer extending to the first planar layer;
a halftone mask plate is arranged on the second flat layer;
illuminating the second planar layer to provide a third aperture and a fourth aperture;
wherein the third hole is disposed corresponding to the first hole, and the fourth hole is disposed corresponding to the second hole.
7. The array substrate processing method of claim 6, wherein the exposure of the first hole and the exposure of the second hole are the same, and the exposure of the third hole and the exposure of the fourth hole are the same.
8. The array substrate processing method of claim 7, wherein the exposure level of the first hole and the second hole is set to 20mj/cm2To 30mj/cm2。
9. The array substrate processing method of claim 7, wherein the exposure level of the third holes and the fourth holes is set to 110mj/cm2To 220mj/cm2。
10. A display panel is characterized by comprising an array substrate, a liquid crystal layer and a black light resistance layer; the liquid crystal layer is arranged on the second electrode layer; the black photoresist layer is disposed on the liquid crystal layer, the black photoresist layer covers at least the third hole and the fourth hole, and the array substrate is the array substrate according to any one of claims 1 to 5.
CN202110005485.3A 2021-01-05 2021-01-05 Array substrate, array substrate manufacturing method and display panel Active CN112711157B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110005485.3A CN112711157B (en) 2021-01-05 2021-01-05 Array substrate, array substrate manufacturing method and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110005485.3A CN112711157B (en) 2021-01-05 2021-01-05 Array substrate, array substrate manufacturing method and display panel

Publications (2)

Publication Number Publication Date
CN112711157A true CN112711157A (en) 2021-04-27
CN112711157B CN112711157B (en) 2023-11-28

Family

ID=75548194

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110005485.3A Active CN112711157B (en) 2021-01-05 2021-01-05 Array substrate, array substrate manufacturing method and display panel

Country Status (1)

Country Link
CN (1) CN112711157B (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101339343A (en) * 2007-07-06 2009-01-07 索尼株式会社 Display device and a method for manufacturing the same
KR20110138964A (en) * 2010-06-22 2011-12-28 엘지디스플레이 주식회사 Array substrate for fringe field switching mode liquid crystal display device and method of fabricating the same
CN104777692A (en) * 2015-05-08 2015-07-15 厦门天马微电子有限公司 Array substrate and preparation method and touch-control display panel
US20150221732A1 (en) * 2014-01-31 2015-08-06 Japan Display Inc. Display device
CN105895581A (en) * 2016-06-22 2016-08-24 武汉华星光电技术有限公司 TFT substrate manufacturing method
CN106775165A (en) * 2017-01-06 2017-05-31 武汉华星光电技术有限公司 In-cell touch display panel and electronic installation
US20180102379A1 (en) * 2016-03-01 2018-04-12 Shenzhen China Star Optoelectronics Technology Co., Ltd. Manufacture method of array substrate and array substrate manufactured by the method
CN112034655A (en) * 2020-08-19 2020-12-04 武汉华星光电技术有限公司 Liquid crystal display panel

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101339343A (en) * 2007-07-06 2009-01-07 索尼株式会社 Display device and a method for manufacturing the same
KR20110138964A (en) * 2010-06-22 2011-12-28 엘지디스플레이 주식회사 Array substrate for fringe field switching mode liquid crystal display device and method of fabricating the same
US20150221732A1 (en) * 2014-01-31 2015-08-06 Japan Display Inc. Display device
CN104777692A (en) * 2015-05-08 2015-07-15 厦门天马微电子有限公司 Array substrate and preparation method and touch-control display panel
US20180102379A1 (en) * 2016-03-01 2018-04-12 Shenzhen China Star Optoelectronics Technology Co., Ltd. Manufacture method of array substrate and array substrate manufactured by the method
CN105895581A (en) * 2016-06-22 2016-08-24 武汉华星光电技术有限公司 TFT substrate manufacturing method
CN106775165A (en) * 2017-01-06 2017-05-31 武汉华星光电技术有限公司 In-cell touch display panel and electronic installation
CN112034655A (en) * 2020-08-19 2020-12-04 武汉华星光电技术有限公司 Liquid crystal display panel

Also Published As

Publication number Publication date
CN112711157B (en) 2023-11-28

Similar Documents

Publication Publication Date Title
TWI553837B (en) Method for fabricating display panel
US9921677B1 (en) Method for fabricating touch display device
CN109906405B (en) Display device, display module, electronic apparatus, and method for manufacturing display device
US9939942B2 (en) Touch display panel
TWI698782B (en) Display device having touch sensors and method of manufacturing the same
US20200249511A1 (en) Display device
EP3171398A1 (en) Array substrate and manufacturing method therefor, and display apparatus
WO2016095263A1 (en) Low temperature poly-silicon array substrate
WO2016061940A1 (en) Thin film transistor array substrate and manufacturing method therefor, and display device
US9759941B2 (en) Array substrate used in liquid crystal panel and manufacturing method for the same
US10001858B2 (en) Substrate including thin film transistor for touch display
US10691244B2 (en) Display device
US20090209068A1 (en) Method of manufacturing thin film transistor substrate
CN107526224B (en) Display device
US20170373102A1 (en) Array substrate and manufacturing method thereof, display panel and display device
US9219088B2 (en) Array substrate, manufacturing method thereof, and display device
CN104022150B (en) Thin film transistor and pixel structure
KR20170089448A (en) Touch display apparatus and method of manufacturing the same
US11239260B2 (en) Substrate for electronic device, display apparatus, method of fabricating substrate for electronic device
EP3355346B1 (en) Manufacturing method of array substrate, array substrate, and display device
CN112711157B (en) Array substrate, array substrate manufacturing method and display panel
US20190355836A1 (en) Manufacturing method for amorphous silicon tft substrate
US9035364B2 (en) Active device and fabricating method thereof
US9105729B2 (en) Display substrate
US20130270546A1 (en) Active device and fabricating method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant