CN112701057A - Test method for improving metal layer leakage current - Google Patents
Test method for improving metal layer leakage current Download PDFInfo
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- CN112701057A CN112701057A CN202011561811.0A CN202011561811A CN112701057A CN 112701057 A CN112701057 A CN 112701057A CN 202011561811 A CN202011561811 A CN 202011561811A CN 112701057 A CN112701057 A CN 112701057A
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- leakage current
- metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
Abstract
The invention provides a test method for improving metal layer leakage current, which comprises the steps of providing a test machine, an SMU (surface Mount unit) instrument and a lot comprising a plurality of wafers; placing one wafer in lot on a chuck of a testing machine; connecting the SMU instrument to the test machine table end, and connecting the Force line end of the SMU instrument to the upper surface of the chuck; connecting the Guard line end of the SMU instrument to the lower surface of the chuck; performing a leakage current test on a plurality of metal layers in the wafer, and collecting leakage current data of the tested metal layers; testing the leakage current of the corresponding metal layer of each wafer in the lot, and collecting the leakage current data of the corresponding metal layer tested in all the wafers in the lot; and comparing the leakage current data of the same metal layer in all the tested wafers. The invention adopts an SMU mechanism with better discharge effect, effectively reduces the influence of charges on the metal layer leakage current test, and thus effectively reduces the problem that the leakage current of the same metal layer of a plurality of wafers in one lot rises.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a test method for improving metal layer leakage current.
Background
The magnitude of the electrical parameter leakage of the chip is low, so that high requirements are put on the test precision, and the electric charge introduced in the production and test processes can affect the accuracy of the test result. In a lot (including 25 wafers) test, as the leakage current of a metal layer is increased due to charge accumulation in the test, the GNDU discharge mechanism is commonly adopted in the industry at present, and the effect of the 28nm LP process with a high technology node is not obvious.
Therefore, it is necessary to provide a new method to solve the above problems.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a testing method for improving leakage current of a metal layer, so as to solve the problem in the prior art that a GNDU discharge mechanism is adopted to have a high electrical parameter leakage test accuracy for a process with a high technology node.
To achieve the above and other related objects, the present invention provides a testing method for improving leakage current of a metal layer, comprising:
providing a test machine, an SMU instrument and a lot containing a plurality of wafers;
secondly, placing one wafer in the lot on a chuck of the testing machine; connecting the SMU instrument to the test machine table end, and connecting the Force line end of the SMU instrument to the upper surface of the chuck; attaching a Guard line end of the SMU instrument to a lower surface of the cartridge;
thirdly, performing leakage current test on the plurality of metal layers in the wafer in the second step, and collecting leakage current data of the tested metal layers;
step four, repeating the step one to the step three, testing the leakage current of the corresponding metal layer of each wafer in the lot, and collecting the leakage current data of the corresponding metal layer tested in all the wafers in the lot;
and step five, comparing the leakage current data of the corresponding metal layer in each wafer.
Preferably, the testing machine in the first step is a testing machine including a function of testing leakage current.
Preferably, the one lot in the first step comprises 25 wafers, and the 25 wafers are stacked in sequence from bottom to top.
Preferably, in the second step, a wafer at the bottommost layer in the lot is placed on the chuck of the testing machine.
Preferably, in the second step, a wafer located at the top layer in the lot is placed on the chuck of the testing machine.
Preferably, in the third step, a leakage current test is performed on the first to fourth metal layers in the wafer.
Preferably, in the fourth step, the first to fourth steps are repeated, and the leakage currents of the first to fourth metal layers of each wafer in the lot are tested according to the sequence of the wafers in the lot from bottom to top.
Preferably, in the fourth step, the first to fourth steps are repeated, and the leakage current of the first to fourth metal layers of each wafer in the lot is tested according to the sequence of the wafers in the lot from top to bottom.
As described above, the test method for improving the metal layer leakage current of the present invention has the following beneficial effects: aiming at the problem that the leakage current of the metal layer corresponding to 25 wafers in one lot rises due to charge accumulation in chip testing, the SMU mechanism with better discharge effect is adopted, so that the influence of the charge on the leakage current testing of the metal layer is effectively reduced, and the problem that the leakage current of the same metal layer of a plurality of wafers in one lot rises is effectively reduced.
Drawings
FIG. 1 shows a SMU discharge schematic of the present invention;
FIGS. 2a to 2d are graphs showing the GNDU discharge test in the prior art and the leakage current test data of the first metal layer M1 to the fourth metal layer M4 in 25 wafers according to the present invention;
FIG. 3 is a flowchart of a testing method for improving leakage current of a metal layer according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 3. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
The invention provides a test method for improving metal layer leakage current, as shown in fig. 3, fig. 3 is a flow chart of the test method for improving metal layer leakage current of the invention, at least comprising the following steps:
providing a test machine, an SMU instrument and a lot containing a plurality of wafers; wherein the SMU (source measurement unit) is provided with two ends, one is a Source line and the other is a Guard line end; further, the testing machine in the first step of this embodiment is a testing machine including a function of testing leakage current.
Further, the one lot in the first step of this embodiment includes 25 wafers, and the 25 wafers are stacked in sequence from bottom to top. And each wafer is placed in one of the slots of the wafer cassette.
Secondly, placing one wafer in the lot on a chuck of the testing machine; connecting the SMU instrument to the test machine table end, and connecting the Force line end of the SMU instrument to the upper surface of the chuck; attaching a Guard line end of the SMU instrument to a lower surface of the cartridge; as shown in fig. 1, fig. 1 shows a schematic diagram of the discharge of an SMU according to the present invention. Placing one of the wafers in the lot on a chuck (chuck) of the test machine; connecting the SMU instrument to the end of the testing machine table, wherein a Force line end of the SMU instrument is connected to the upper surface of the chuck; the Guard line end of the SMU meter is attached to the lower surface of the chuck.
Further, in the second step of this embodiment, a wafer at the bottommost layer in the lot is placed on the chuck of the testing machine.
Thirdly, performing leakage current test on the plurality of metal layers in the wafer in the second step, and collecting leakage current data of the tested metal layers; due to the discharge mechanism of the SMU, the corresponding metal layer tested on each wafer does not cause charge accumulation.
Further, in the third step of this embodiment, a leakage current test is performed on the first to fourth metal layers in the wafer. That is, the leakage current test is performed on the M1-M4 metal layers of each wafer.
Step four, repeating the step one to the step three, testing the leakage current of the corresponding metal layer of each wafer in the lot, and collecting the leakage current data of the corresponding metal layer tested in all the wafers in the lot;
further, in step four of this embodiment, the first to fourth steps are repeated, and the leakage currents of the first to fourth metal layers of each wafer in lot are tested according to the sequence from bottom to top of the wafer in lot.
And step five, comparing the leakage current data of the same metal layer in all the tested wafers. Referring to fig. 2a to 2d, fig. 2a to 2d are graphs showing the GNDU discharge test in the prior art and the leakage current test data of the first metal layer M1 to the fourth metal layer M4 in 25 wafers according to the present invention.
Therefore, SMU discharge is adopted to replace GNDU discharge in the prior art, the phenomenon that leakage current of the same metal layer in different wafers rises can be effectively reduced, and accumulation of charges is reduced.
Example two
The invention provides a test method for improving metal layer leakage current, which at least comprises the following steps:
providing a test machine, an SMU instrument and a lot containing a plurality of wafers; wherein the SMU (source measurement unit) is provided with two ends, one is a Source line and the other is a Guard line end; further, the testing machine in the first step of this embodiment is a testing machine including a function of testing leakage current.
Further, the one lot in the first step of this embodiment includes 25 wafers, and the 25 wafers are stacked in sequence from bottom to top. And each wafer is placed in one of the slots of the wafer cassette.
Secondly, placing one wafer in the lot on a chuck of the testing machine; connecting the SMU instrument to the test machine table end, and connecting the Force line end of the SMU instrument to the upper surface of the chuck; attaching a Guard line end of the SMU instrument to a lower surface of the cartridge; as shown in fig. 1, fig. 1 shows a schematic diagram of the discharge of an SMU according to the present invention. Placing one of the wafers in the lot on a chuck (chuck) of the test machine; connecting the SMU instrument to the end of the testing machine table, wherein a Force line end of the SMU instrument is connected to the upper surface of the chuck; the Guard line end of the SMU meter is attached to the lower surface of the chuck.
Further, in the second step of this embodiment, a wafer at the top layer in the lot is placed on the chuck of the testing machine.
Thirdly, performing leakage current test on the plurality of metal layers in the wafer in the second step, and collecting leakage current data of the tested metal layers; due to the discharge mechanism of the SMU, the corresponding metal layer tested on each wafer does not cause charge accumulation.
Further, in the third step of this embodiment, a leakage current test is performed on the first to fourth metal layers in the wafer. That is, the leakage current test is performed on the M1-M4 metal layers of each wafer.
Step four, repeating the step one to the step three, testing the leakage current of the corresponding metal layer of each wafer in the lot, and collecting the leakage current data of the corresponding metal layer tested in all the wafers in the lot;
further, in step four of this embodiment, the first to fourth steps are repeated, and the leakage currents of the first to fourth metal layers of each wafer in lot are tested according to the sequence of the wafers in lot from top to bottom.
And step five, comparing the leakage current data of the same metal layer in all the tested wafers. Referring to fig. 2a to 2d, fig. 2a to 2d are graphs showing the GNDU discharge test in the prior art and the leakage current test data of the first metal layer M1 to the fourth metal layer M4 in 25 wafers according to the present invention.
Therefore, SMU discharge is adopted to replace GNDU discharge in the prior art, the phenomenon that leakage current of the same metal layer in different wafers rises can be effectively reduced, and accumulation of charges is reduced.
In summary, the invention employs an SMU mechanism with better discharge effect to effectively reduce the influence of charges on the metal layer leakage current test, so as to effectively reduce the problem that the leakage current of the same metal layer of a plurality of wafers in one lot rises. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A test method for improving metal layer leakage current is characterized by at least comprising the following steps:
providing a test machine, an SMU instrument and a lot containing a plurality of wafers;
secondly, placing one wafer in the lot on a chuck of the testing machine; connecting the SMU instrument to the test machine table end, and connecting the Force line end of the SMU instrument to the upper surface of the chuck; attaching a Guard line end of the SMU instrument to a lower surface of the cartridge;
thirdly, performing leakage current test on the plurality of metal layers in the wafer in the second step, and collecting leakage current data of the tested metal layers;
step four, repeating the step one to the step three, testing the leakage current of the corresponding metal layer of each wafer in the lot, and collecting the leakage current data of the corresponding metal layer tested in all the wafers in the lot;
and step five, comparing the leakage current data of the same metal layer in all the tested wafers.
2. The method as claimed in claim 1, wherein the step of testing the metal layer comprises: the testing machine in the first step is a testing machine with a function of testing leakage current.
3. The method as claimed in claim 1, wherein the step of testing the metal layer comprises: the lot in the step one comprises 25 wafers, and the 25 wafers are stacked in sequence from bottom to top.
4. The method as claimed in claim 1, wherein the step of testing the metal layer comprises: and in the second step, a wafer positioned at the bottommost layer in the lot is placed on the chuck of the testing machine.
5. The method as claimed in claim 1, wherein the step of testing the metal layer comprises: and in the second step, a wafer positioned at the uppermost layer in the lot is placed on the chuck of the testing machine.
6. The method as claimed in claim 1, wherein the step of testing the metal layer comprises: and in the third step, performing a leakage current test on the first to fourth metal layers in the wafer.
7. The method as claimed in claim 4, wherein the test method further comprises: and in the fourth step, repeating the first step to the fourth step, and testing the leakage current of the first metal layer to the fourth metal layer of each wafer in the lot according to the sequence of the wafers in the lot from bottom to top.
8. The method as claimed in claim 5, wherein the step of testing the metal layer comprises: and in the fourth step, repeating the first step to the fourth step, and testing the leakage current of the first metal layer to the fourth metal layer of each wafer in the lot according to the sequence of the wafers in the lot from top to bottom.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011561811.0A CN112701057A (en) | 2020-12-25 | 2020-12-25 | Test method for improving metal layer leakage current |
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| CN202011561811.0A CN112701057A (en) | 2020-12-25 | 2020-12-25 | Test method for improving metal layer leakage current |
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| CN112701057A true CN112701057A (en) | 2021-04-23 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5519327A (en) * | 1994-06-10 | 1996-05-21 | Vlsi Technology, Inc. | Pulse circuit using a transmission line |
| CN102866340A (en) * | 2011-07-07 | 2013-01-09 | 中芯国际集成电路制造(上海)有限公司 | Building-out circuit and testing method for testing negative bias temperature instability |
| JP2019009212A (en) * | 2017-06-22 | 2019-01-17 | 信越半導体株式会社 | Evaluation method of semiconductor substrate |
| CN111406228A (en) * | 2017-11-24 | 2020-07-10 | 浜松光子学株式会社 | Electrical inspection method |
-
2020
- 2020-12-25 CN CN202011561811.0A patent/CN112701057A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5519327A (en) * | 1994-06-10 | 1996-05-21 | Vlsi Technology, Inc. | Pulse circuit using a transmission line |
| CN102866340A (en) * | 2011-07-07 | 2013-01-09 | 中芯国际集成电路制造(上海)有限公司 | Building-out circuit and testing method for testing negative bias temperature instability |
| JP2019009212A (en) * | 2017-06-22 | 2019-01-17 | 信越半導体株式会社 | Evaluation method of semiconductor substrate |
| CN111406228A (en) * | 2017-11-24 | 2020-07-10 | 浜松光子学株式会社 | Electrical inspection method |
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