CN216792376U

CN216792376U - Multi-chip test fixture

Info

Publication number: CN216792376U
Application number: CN202122574206.3U
Authority: CN
Inventors: 罗立辉; 李春阳; 方梁洪; 任超; 彭祎; 刘凤; 刘明明
Original assignee: Ningbo Chipex Semiconductor Co ltd
Current assignee: Ningbo Chipex Semiconductor Co ltd
Priority date: 2021-10-26
Filing date: 2021-10-26
Publication date: 2022-06-21
Anticipated expiration: 2031-10-26

Abstract

The utility model relates to a multi-chip test fixture which is manufactured by adopting a test wafer, wherein chips and cutting channels which are in the same layout as those of a chip wafer to be tested are arranged on the test wafer, a blue film is arranged on the back surface of the test wafer, at least one chip groove for containing the chip to be tested is arranged on the test wafer, a single chip groove is positioned between two adjacent horizontal cutting channels or between two adjacent vertical cutting channels on the test wafer, and a plurality of chips to be tested can be contained in the single chip groove. The multi-chip test fixture can greatly improve the reliability and electrical performance test efficiency of the chip, reduce the risk of chip damage, and provide support for obtaining accurate test results and completing all test items.

Description

Multi-chip test fixture

Technical Field

The utility model relates to the technical field of chip jigs, in particular to a multi-chip test jig.

Background

With the development of semiconductor integrated circuit technology, at present, most of chips adopting advanced semiconductor processes adopt Wafer Level Chip Scale Packaging (WLCSP), the Packaging of chips and the testing of functions and performance of chips are all completed on wafers, and the Packaging and testing efficiency is high. After the packaging and the function testing are completed, the wafer is cut into single chips, and then reliability tests such as a High Temperature cooking Test (PCT), a Temperature Cycle Test (TCT), a High Temperature Storage Test (High Temperature Storage Test), a High Pressure cooking Test (High accessed Stress Test, HAST) and the like are arranged for the single chips, so that the electrical performance of the chip product can be tested again during the reliability Test or after the reliability Test is completed.

In the existing electrical performance test scheme for a chip after a reliability test is completed, a specially-made single chip fixture (socket) is prepared for a packaged chip to be tested, the socket is firstly installed on a test Load board (Load board), then a tester uses tweezers to place a single chip into the socket, and a manual probe station is used for testing the chip in the socket. In the face of hundreds or even thousands of chips to be tested, the testing method is actually too low in efficiency, various accidents are easy to occur in the process of clamping the chips by tweezers and putting the chips into a socket, the reliability and electrical performance testing results of the chips are affected, for example, the chips are damaged by the tweezers, the chips are collided with the socket to cause chip corner collapse damage, and the like, the problems that the testing results are unstable, the testing items are incomplete and the like exist when the chips in the socket are tested by using a manual probe station, and in addition, socket jigs are often complex in structure and expensive to manufacture. The reliability and electrical performance test of the chip has great market demand, and the existing test scheme is tedious and old.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a multi-chip test fixture, which can greatly improve the reliability and electrical performance test efficiency of a chip, reduce the risk of chip damage and provide support for obtaining accurate test results and completing all test items.

The technical scheme includes that the multi-chip testing jig is manufactured by adopting a testing wafer, chips and cutting channels which are in the same layout as those on a chip wafer to be tested are arranged on the testing wafer, a blue film is arranged on the back surface of the testing wafer, at least one chip groove for containing the chips to be tested is arranged on the testing wafer, a single chip groove is positioned between two adjacent horizontal cutting channels or between two adjacent vertical cutting channels on the testing wafer, and a plurality of chips to be tested can be contained in the single chip groove.

Compared with the prior art, the multi-chip test jig has the following advantages: the test wafer is provided with chips and cutting paths which have the same layout as the chips to be tested and are arranged on the test wafer, the test wafer can be cut along two horizontal cutting paths and two vertical cutting paths, the cut chip strips are picked out between two adjacent horizontal cutting paths or between two adjacent vertical cutting paths on the wafer, the positions of the chip strips are picked out to form chip grooves, a plurality of chips to be tested packaged by adopting the chip size can be placed at one time, the size of the chip grooves is completely matched with the chips to be tested, the risk of chip damage is reduced, the jig is practical, simple to manufacture and low in cost, the blue film arranged on the back of the test wafer can enable the cut test wafer to continuously keep the whole state, and the test wafer is prevented from being divided into four parts and five parts after being cut, so the multi-chip test jig can support an automatic test bench (wafer) and a cutting path which are applied in wafer level test, The test probe card (probe card) and the test program are used for testing, all test items can be completed, an accurate test result can be obtained, and the reliability and electrical performance test efficiency of the chip is greatly improved.

The test wafer is used for testing the process state of production equipment before the chip wafer is put into production formally, or is a wafer processed with normal production batches to test the quality condition of a certain process, the wafer adopts a mask plate and a production process which are the same as those of the chip wafer, the thickness of the wafer, the chip size on the wafer and the layout of cutting channels are completely the same as those of the chip wafer, and the wafer is used for testing the stability of a production line or judging whether the process is normal or not, and has no other use for the production batches.

Preferably, the test wafer is a single-item wafer having the same chip layout as the chip wafer to be tested, the test wafer is provided with a plurality of parallel chip grooves, all the chip grooves are located between two identical horizontal cutting lanes or between two identical vertical cutting lanes, and the spacing distances between any two adjacent chip grooves are identical. By adopting the structure, all the chip grooves are parallel, equal in length and aligned uniformly, and after the chip grooves are filled with the chips to be tested, all the chips to be tested are arranged in the square queue, so that the shift programming of the test pin card is facilitated, and the automatic test of the chips is completed.

Preferably, the test wafer is a multi-project wafer having the same chip layout as the chip wafer to be tested, at least one corresponding chip slot is arranged on the test wafer for each project chip, and the chip slot is used for accommodating a plurality of chips to be tested corresponding to the project. By adopting the structure, the chips of a plurality of projects can be tested by adopting the same chip test fixture, so that the cost is saved.

Preferably, a plurality of chip slots corresponding to the same project are arranged in parallel and are all located between two identical horizontal cutting lanes or located between two identical vertical cutting lanes. By adopting the structure, after the chips to be tested of the same item are fully arranged in the corresponding chip grooves, a square queue is formed, so that the shift programming of the test pin card is convenient, and the automatic test of the chips of the item is completed.

Preferably, a positioning notch is formed in the test wafer, and the positioning notch is used for positioning and mounting the test wafer on the test board. By adopting the structure, the multi-chip test fixture is convenient to be installed on an automatic test bench and positioned.

Preferably, the test wafer is further provided with at least three positioning chips, and the positioning chips are used for enabling the test equipment to automatically find the positions of the chip grooves. By adopting the structure, when the test pin card is initially positioned, the position of the chip slot can be accurately found according to the position of the positioning chip, and the initial test position and the subsequent displacement rule of the test pin card can be determined by the displacement program of the test pin card, so that the automatic test of the chip is realized.

Drawings

Fig. 1 is a schematic structural diagram of a multi-chip test fixture according to embodiment 1 of the utility model.

Fig. 2 is a schematic structural diagram of a multi-chip test fixture according to embodiment 2 of the utility model.

As shown in the figure: 1. the chip testing device comprises a testing wafer, 1-1 parts of a cutting channel, 1-2 parts of a chip groove, 1-3 parts of a testing chip, 2 parts of a plurality of visual test piece wafers, 2-1 parts of a chip groove I, 2-2 parts of a chip groove II, 2-3 parts of a chip groove III, 2-4 parts of a type I chip area, 2-5 parts of a type II chip area, 2-6 parts of a type III chip area, and 3 parts of a positioning notch.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification.

In the drawings, the thickness, size, and shape of an object have been slightly exaggerated for convenience of explanation. The figures are purely diagrammatic and not drawn to scale.

It will be further understood that the terms "comprises," "comprising," "includes," "including," and/or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Further, when a statement such as "… at least one" appears after the list of listed features, the entire listed feature is modified rather than modifying individual elements in the list.

In the production of integrated circuit wafers (ICs), on one hand, some wafers (wafers), which are commonly called Monitor wafers (Monitor wafers), are required to test the process status of the production equipment, such as particle level, etching rate, defect rate, etc., and the Monitor wafers are also used to test the quality of a certain process, such as CVD film thickness, etc., along with the normal production lots. On the other hand, after maintenance or repair of a production facility, if a batch of wafers is produced by an immediate process, the wafers are easily scrapped, so that usually some very low-cost Dummy wafers (Dummy wafers) are used to run the process to determine the quality of the maintenance or repair work, sometimes Dummy wafers are also used in the normal production process, for example, some machines must require a certain number of wafers to process, especially in a furnace (PVD/CVD/oxidation diffusion, etc.), if the batch of wafers is not full, gaps are left, which may affect the stability and uniformity of the gas flow, therefore, the shortage is made up by the Dummy wafers, and some machines must perform a certain type of Dummy run after processing a certain number of wafers, otherwise, the quality of the process cannot be guaranteed. The Monitor Wafer and the Dummy Wafer are both test wafers, the test wafers are made of the same mask plate and the same production process as the chip Wafer, and the thickness of the Wafer, the size of the chip on the Wafer and the layout of the cutting streets are also completely the same as those on the chip Wafer.

Example 1:

as shown in FIG. 1, the multi-chip testing jig of the utility model adopts a testing wafer 1 with the same chip layout as the wafer to be tested, the wafer is a single-item wafer, a plurality of testing chips 1-3 which are arranged in order in a square matrix are arranged on the testing wafer 1, the periphery of each testing chip 1-3 is surrounded by cutting channels 1-1 which are distributed vertically and horizontally, a chip belt is arranged between two adjacent horizontal cutting channels 1-1, a blue film is arranged on the back surface of the testing wafer 1, a positioning notch 3 is arranged at the bottom end of the testing wafer 1, two positioning chips (not shown) are respectively arranged at the two sides and the bottom of the middle of the

testing wafer

1, 3 parallel chip grooves 1-2 are arranged on the testing wafer 1, each chip groove 1-2 is arranged between two adjacent horizontal cutting channels 1-1 on the testing wafer, each chip groove 1-2 is also positioned between two same vertical cutting channels, 5 chips to be tested can be contained in a single chip groove, and 2 chip belts are arranged between each chip groove 1-2 at intervals.

The chip slot on the multi-chip test fixture of the embodiment can be manufactured by the following method: the test wafer 1 is cut along two horizontal cutting channels and two vertical cutting channels, chip strips between the 4 cutting channels are picked out, and chip slots are formed by picking out the positions of the chip strips.

Example 2:

as shown in fig. 2, the multi-chip testing tool of the present embodiment is different from embodiment 1 in that the present embodiment employs a plurality of visual test piece wafers 2, chips with 3 different items are fabricated on the plurality of visual test piece wafers 2, and the plurality of visual test piece wafers 2 are divided into type i chip regions 2-4, type ii chip regions 2-5, and type iii chip regions 2-6 according to positions of the different items. 2 parallel chip grooves I2-1 are arranged in a class I chip area 2-4, 2 chip grooves I2-1 are located between two adjacent horizontal cutting channels, each chip groove I2-1 is also located between two same vertical cutting channels, 13 class I chips can be contained in a single chip groove I2-1, 2 chip belts are arranged between 2 chip grooves I2-1 at intervals, 1 chip groove II 2-2 is arranged in a class II chip area 2-5, 5 class II chips can be contained in a chip groove II 2-2, 1 chip groove III 2-3 is arranged in a class III chip area 2-6, 10 class III chips can be contained in a chip groove III 2-3, and the chips of 3 projects can be placed on a chip testing jig for testing.

The above are merely specific examples of the present invention, and are not intended to limit the scope of the utility model; it is intended that the following claims be interpreted as including all such alterations, modifications, and equivalents as fall within the true spirit and scope of the utility model.

Claims

1. The utility model provides a multi-chip test fixture, its characterized in that adopts the preparation of test piece wafer, the test piece wafer on be provided with the chip and the cutting way of the same overall arrangement on the chip wafer that awaits measuring, the back of test piece wafer is provided with blue membrane, the test piece wafer on be provided with at least one chip groove that is used for holding the chip that awaits measuring, single chip trench is located on the test piece wafer between two adjacent horizontal cutting ways or between two adjacent vertical cut ways, single chip inslot can hold a plurality of chip that awaits measuring.

2. The multi-chip testing fixture of claim 1, wherein the testing wafer is a single-item wafer having the same chip layout as the chip wafer to be tested, the testing wafer is provided with a plurality of parallel chip slots, all the chip slots are located between two identical horizontal cutting lanes or between two identical vertical cutting lanes, and the spacing distance between any two adjacent chip slots is the same.

3. The multi-chip testing fixture according to claim 1, wherein the testing wafer is a multi-project wafer having the same chip layout as the chip wafer to be tested, and at least one corresponding chip slot is disposed on the testing wafer for each project chip, and the chip slot is used for accommodating a plurality of chips to be tested corresponding to the project.

4. The multi-chip testing fixture of claim 3, wherein a plurality of chip slots corresponding to a same project are arranged in parallel and are located between two same horizontal cutting lanes or located between two same vertical cutting lanes.

5. The multi-chip testing fixture according to any one of claims 1 to 4, wherein a positioning notch is disposed on the testing wafer, and the positioning notch is used for positioning and mounting the testing wafer on the testing platform.

6. The multi-chip testing fixture of any one of claims 1 to 4, wherein at least three positioning chips are further disposed on the test wafer, and the positioning chips are used for enabling the testing equipment to automatically find the positions of the chip slots.