CN112698173A - Nondestructive testing method for peak junction temperature of chips in multi-chip parallel packaging module - Google Patents
Nondestructive testing method for peak junction temperature of chips in multi-chip parallel packaging module Download PDFInfo
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- CN112698173A CN112698173A CN202011419747.2A CN202011419747A CN112698173A CN 112698173 A CN112698173 A CN 112698173A CN 202011419747 A CN202011419747 A CN 202011419747A CN 112698173 A CN112698173 A CN 112698173A
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Abstract
The invention discloses a nondestructive testing method for peak chip temperature of a parallel device in a module, which realizes the measurement of the peak junction temperature of the parallel device or the module by constructing a temperature-conduction voltage drop curve cluster based on current ratio under a specific test current. Obtaining a temperature correction current-temperature-conduction voltage drop three-dimensional database, and obtaining a temperature-conduction voltage drop curve cluster based on current ratio under a specific test current by using a current conversion formula according to the test current and the number of parallel devices; conducting voltage drop corresponding to the small current of the device working state test is obtained by utilizing the curve cluster and measurement, and a current ratio-temperature curve under different test currents is obtained; and finally, determining the peak junction temperature and the current ratio of the parallel device or module according to the current ratio-temperature curve intersection points under different test currents. By using the method, the nondestructive measurement of the peak chip temperature of the parallel device in the module can be realized without adding extra equipment on the basis of a mature small current drop method.
Description
Technical Field
The invention relates to a method for testing the peak junction temperature of chips in a multi-chip parallel packaging module, belonging to the field of power semiconductor device testing.
Background
The power semiconductor switch device/module is one of key components in a power electronic system, is mainly applied to an inverter, a rectifier and the like, realizes control and conversion of electric energy, and is the core of a power conversion technology. The current capacity of the wind power generation device is required to be increased in various application fields. When the high-voltage, high-current and high-power applications are solved, the current capacity of the existing single discrete device can not meet the requirement of large-capacity power conversion, the manufacturing difficulty of the large-capacity single discrete device is high, the cost is high, and based on the power grade and the current capacity limit of the single device, the current capacity or power expansion is realized by adopting a modular mode of parallel connection of discrete devices or multi-chip parallel connection packaging. In parallel connection, due to the factors of the difference of each chip, different heat dissipation conditions and the like, the temperature distribution of each chip is not uniform due to heat power consumption generated in work, wherein the reliability and the service life of the chip with the highest temperature determine the upper limit of the use reliability of a parallel system or a module, and therefore the method is particularly important for measuring the peak junction temperature of a parallel device or a module.
At present, for junction temperature measurement of a single semiconductor device, a mature method and a mature system are available, and lossless junction temperature measurement without damaging packaging mainly takes a small current drop method based on an electrical method and thermal resistance calculation as main points. In a parallel application system, because chips are packaged in parallel in the same module, the test of each chip branch is difficult to realize, and the error between the test result and the peak junction temperature is large when a traditional single-device test method is used for measuring the trunk of the parallel device, so that the reliability of the parallel device or the module is difficult to evaluate. Meanwhile, currently, for the peak junction temperature measurement of parallel devices or modules, only an infrared measurement mode for destroying packaging can be adopted, and a suitable nondestructive electrical test method is not available. Especially for novel packaging such as compression joint and the like, electrical connection cannot be guaranteed after the packaging is damaged, and measurement methods such as infrared and the like are not applicable any more.
Disclosure of Invention
Aiming at the problems, the invention provides a method for testing the peak junction temperature of a chip in a multi-chip parallel packaging module. According to the method, an additional test circuit is not required to be added, and the temperature calibration curve and the peak junction temperature can be measured by using low-current test equipment in the existing mature system.
The technical scheme adopted by the invention is as follows:
under different temperatures and temperature correction currents, conducting voltage drop of the whole parallel device or module is measured to obtain a three-dimensional database of temperature-temperature correction current-conducting voltage drop, specific test current is selected, and a temperature-conducting voltage drop temperature correction curve cluster related to current ratio under any specific test current is obtained according to a current ratio conversion formula. And then when the device works, measuring the voltage of the parallel device or the module according to the specific test current, substituting the voltage into a voltage-temperature curve cluster under different current ratios corresponding to each specific test current to obtain a series of temperature values under different current ratios under each specific test current, and then drawing and fitting to obtain a current ratio-temperature change curve. And finally, determining the peak junction temperature of the parallel devices or modules according to the current ratio-temperature curve intersection points under different specific test currents (not less than two).
The equipment for realizing the method comprises a module 1 to be tested with multiple chips connected in parallel, a parallel test fixture 2, a temperature box or a temperature control platform 3 and a test source table 4; the incubator or the temperature control platform 3 is used for heating the module 1, and the test source meter 4 is used for applying different currents to the module 1 to be tested and measuring the conduction voltage drop.
The invention is characterized in that the invention also comprises the following steps:
the method comprises the following steps: placing the module 1 on a parallel test fixture 2, then placing the module 1 and the parallel test fixture 2 on a temperature box or a temperature control platform 3, and heating the module 1 by using the temperature box or the temperature control platform 3;
step two: setting the initial temperature of the incubator or the temperature control platform 3 to enable the temperature of the module 1 to be stabilized at the set temperature of the incubator or the temperature control platform 3, applying temperature correction current according to a certain step length by using the test source meter 4 after the temperature is stabilized, and testing to obtain the conduction voltage drop of the module 1 under different temperature correction currents;
step three: changing the temperature of the temperature box or the temperature control platform 3 according to a certain step length, repeating the temperature correction current test in the step two, and measuring the conduction voltage drop of the module 1 at different temperatures and temperature correction currents;
step four: converting the temperature correcting current into a current ratio according to the specific test current (not less than two) and the number of chips connected in parallel in the module 1, and then drawing a voltage-temperature curve cluster based on the specific test current (not less than two) under different current ratios;
step five: applying normal working large current and specific test current (not less than two) to the module 1, and after the module works stably, disconnecting the working current to obtain the conduction voltage drop of the module 1 under the specific test current (not less than two);
step six: according to the conduction voltage drop of the module 1 based on specific test currents (not less than two), calibrating voltage-temperature curve clusters under different current ratios, acquiring corresponding current ratios and temperature values, and drawing current ratio-temperature curves under specific currents (not less than two);
step seven: and determining the peak junction temperature and the corresponding current ratio of the module to be tested 1 according to the current ratio-temperature curve intersection points under different specific test currents (not less than two).
The highest chip junction temperature of the module 1, namely the peak junction temperature, can be obtained according to the conduction voltage drop (not less than two) of the module 1 under specific current without measuring the electrical parameters of each chip in the module 1 to be measured;
in the device heating of the step one, discrete devices are placed on an incubator or a temperature control platform 3 in parallel through a parallel test fixture 2 for heating, and a multi-chip module is directly placed on the incubator or the temperature control platform 3 for heating;
the temperature correcting current in the step two is a small test current of the module 1 and is a main circuit total current of the module 1, and because the temperature correcting current is small, the power consumption is low, and the self-temperature rise of a device can be ignored;
step four, the specific conversion formula for converting the temperature correcting current into the current ratio according to the specific test current (a plurality of test currents) and the number of the parallel modules 1 is as follows:
wherein the current ratio is P, and the temperature correction current is IAWith a specific test current of IBThe number of parallel devices is N.
The method of the current ratio-temperature curve under specific current (not less than two) comprises the following steps: and substituting the conduction voltage drop value of the module 1 measured under the specific current into the voltage-temperature curve cluster under different current ratios corresponding to each specific test current to obtain a series of temperature values under different current ratios under each specific test current, and then drawing and fitting to obtain a current ratio-temperature change curve.
The invention has the beneficial effects that: the method has simple equipment and convenient operation, and can realize the measurement of the peak junction temperature of the parallel devices or modules without adding extra equipment on the basis of a mature small current drop method.
Drawings
FIG. 1 is a schematic diagram of a testing apparatus according to the present invention, in which: 1-parallel chip, 2-parallel test fixture, 3-incubator or constant temperature platform, 4-test source meter;
FIG. 2 is a flow chart of a method in accordance with the present invention;
FIG. 3 is a three-dimensional scatter plot of temperature-calibration current-conduction voltage drop;
FIG. 4 is a cluster of temperature-voltage temperature calibration curves for current ratios at 10mA test current;
FIG. 5 is a plot of current ratio versus temperature curve intersection for 10mA &20mA test currents;
Detailed Description
The present invention will be described in more detail below with reference to the accompanying drawings and specific embodiments.
Taking parallel connection of IGBT discrete devices as an example, the testing device related to the invention is shown in FIG. 1. The IGBT device testing device comprises an IGBT device 1, a parallel test fixture 2, an incubator 3 and a test source meter 4. The IGBT devices 1 to be tested are 2 insulated gate bipolar transistors in total, the type is IKW30N60H3, the packaging form is T0-247, the maximum working voltage is 600V, and the maximum working current is 30A. The incubator 3 employs Despatch900 series. Test source table 4 used a deb 1505A power device analyzer and a power source table.
The flow chart of the method of the invention is shown in fig. 2, and comprises the following steps:
the method comprises the following steps: the two IGBT devices 1 to be tested are inserted into the parallel test fixture and are placed into an incubator, and the three parallel ends of the devices on the parallel test fixture are externally connected to the test ports of the corresponding devices B1505A through high-temperature wires. The parallel devices are heated by an incubator, the heating temperature is increased by 5 ℃ from 30 ℃, namely the test temperature is 30 ℃, 35 ℃, … and 120 ℃.
Step two: when the temperature of the incubator reaches 30 ℃ and is stabilized for 10 minutes, the parallel devices are considered to be consistent with the temperature set by the incubator at the moment, and B1505A is utilized to provide a fixed grid voltage VGEKeeping the device gate on at 15V and providing a continuous temperature correction current I with a test range of 0-50mA and a step of 100uAAObtaining the corresponding conduction voltage drop V of different temperature correcting currents at the temperatureCE；
Step three: heating the incubator by 5 ℃ to reach a set value, repeating the step two, and sequentially obtaining temperature correction current I at 35 ℃, 40 ℃, … and 120 DEGACorresponding conducting voltage drop VCE(ii) a Finally, a temperature correction current-temperature-conduction voltage drop three-dimensional database is obtained;
step four: setting a test current IB1＝10mA,IB2Obtaining 100 temperature-conduction voltage drop curve clusters with the test current of 10mA and the current ratio of 1%, 2%, … and 100% under 20mA respectively according to a current ratio conversion formula;
step five: the method comprises the steps of utilizing a power source table to provide 10mA continuous test current for continuous working current ICE (internal Current emphasis) 40A of a parallel device, B1505A, disconnecting a power source when the device works stably, and utilizing B1505A to collect conduction voltage drop V of the parallel device under 10mACE1(ii) a Repeating the above operation to obtain the conduction voltage drop V of the parallel device under 20mACE2；
Step six: the obtained 10mA and 20mA test currents are corresponding to the conduction voltage drop VCE1And VCE2And substituting the obtained current ratio into each temperature-conduction voltage drop curve cluster to obtain the current ratio under the conditions of 10mA and 20mA and the current ratio of 1-100 percent-a temperature profile;
step seven: and finally, obtaining the peak junction temperature of the IGBT double-tube parallel device and the current ratio of the high-temperature chip at the moment according to the current ratio-temperature curve intersection point under the current ratio of 1% -100% under the test currents of 10mA and 20 mA.
Claims (7)
1. A nondestructive testing method for peak junction temperature of chips in a multi-chip parallel packaging module is disclosed, and a device for realizing the method comprises a tested multi-chip parallel switch module (1), a parallel test fixture (2), a temperature box or a temperature control platform (3) and a test source meter (4); the incubator or the temperature control platform (3) is used for heating the module (1), and the test source meter (4) is used for applying different currents to the module (1) to be tested and measuring conduction voltage drop; the method is characterized by comprising the following steps:
the method comprises the following steps: placing the module (1) on the device clamp (2), then placing the module (1) on the incubator or temperature control platform (3), and heating the module (1) by using the incubator or temperature control platform (3);
step two: setting the initial temperature of the incubator or the temperature control platform (3) to enable the temperature of the module (1) to be stabilized at the set temperature of the incubator or the temperature control platform (3), applying temperature correction currents according to certain step length by using the test source meter (4) after the temperature is stabilized, and testing to obtain the conduction voltage drop of the module (1) under different temperature correction currents;
step three: changing the temperature of the incubator or the temperature control platform (3) according to a certain step length, repeating the temperature correction current test in the step two, and measuring the conduction voltage drop of the module (1) under different temperatures and temperature correction currents;
step four: converting the temperature correcting current into a current ratio according to the number of the chips connected in parallel with the module (1) and the specific test current, and then drawing a voltage-temperature curve cluster based on the specific test current under different current ratios;
step five: applying normal working large current and specific test current to the module (1), and after working is stable, disconnecting the working current to obtain the conduction voltage drop of the module (1) under the specific test current;
step six: according to the conduction voltage drop of the module (1) based on the specific test current, calibrating voltage-temperature curve clusters under different current ratios, acquiring corresponding current ratios and temperature values, and drawing a current ratio-temperature curve under the specific current;
step seven: and determining the peak junction temperature and the corresponding current ratio of the tested multi-chip parallel switch module (1) according to the current ratio-temperature curve intersection point under different specific test currents.
2. The nondestructive testing method for the peak chip junction temperature in the multi-chip parallel packaging module according to claim 1, wherein the highest chip junction temperature, namely the peak junction temperature, of the tested multi-chip parallel switch-containing module (1) can be obtained according to the conduction voltage drop of the tested multi-chip parallel switch-containing module (1) under a specific current without measuring the electrical parameters of each chip in the tested multi-chip parallel switch-containing module (1).
3. The method of claim 1, wherein in the step one, the device heating is performed by placing discrete devices in parallel on the incubator or the temperature-controlled platform (3) through the parallel test fixture (2) and heating, and the multichip module is placed directly on the incubator or the temperature-controlled platform (3) and heating.
4. The nondestructive testing method for the peak chip junction temperature in the multi-chip parallel packaging module according to claim 1, wherein the temperature calibration current in the second step is a small current which does not cause the tested multi-chip parallel switch module (1) and is a main circuit total current of the tested multi-chip parallel switch module (1), and the temperature calibration current is small, so that the power consumption is low, and the self-temperature rise of the device is avoided.
5. The nondestructive testing method for the peak junction temperature of the chips in the multi-chip parallel packaging module according to claim 1, wherein the specific conversion formula for converting the temperature correcting current into the current ratio according to the specific test current and the number of the chips in the multi-chip parallel switching module (1) to be tested in parallel is as follows:
wherein the current ratio is P, and the temperature correction current is IAWith a specific test current of IBThe number of parallel devices is N.
6. The method of claim 1, wherein the method of the current ratio-temperature curve at a specific current in the sixth step is: and substituting the measured conduction voltage drop value of the tested multi-chip parallel switch module (1) under the specific current into the voltage-temperature curve cluster under different current ratios corresponding to each specific test current to obtain a series of temperature values under different current ratios under each specific test current, and then drawing and fitting to obtain a current ratio-temperature change curve.
7. The method of claim 1, wherein there are two test currents; the specific current is not less than two.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114217198A (en) * | 2021-12-07 | 2022-03-22 | 北京工业大学 | Short-pulse heavy-current-based SiC MOSFET module thermal resistance measurement method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114217198A (en) * | 2021-12-07 | 2022-03-22 | 北京工业大学 | Short-pulse heavy-current-based SiC MOSFET module thermal resistance measurement method |
| CN114217198B (en) * | 2021-12-07 | 2023-10-10 | 北京工业大学 | Short pulse-based high-current SiC MOSFET module thermal resistance measurement method |
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