CN112687220A - Shift register circuit and display panel - Google Patents
Shift register circuit and display panel Download PDFInfo
- Publication number
- CN112687220A CN112687220A CN202011547394.4A CN202011547394A CN112687220A CN 112687220 A CN112687220 A CN 112687220A CN 202011547394 A CN202011547394 A CN 202011547394A CN 112687220 A CN112687220 A CN 112687220A
- Authority
- CN
- China
- Prior art keywords
- signal
- pull
- subunit
- transistor
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 32
- 230000008054 signal transmission Effects 0.000 claims description 30
- 239000003990 capacitor Substances 0.000 claims description 18
- 238000010586 diagram Methods 0.000 description 26
- 238000000034 method Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- 230000001960 triggered effect Effects 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Images
Landscapes
- Logic Circuits (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The shift register circuit comprises a pull-up module, a first pull-up unit, a second pull-up unit and a control unit, wherein the first pull-up unit comprises a first pull-up subunit and a second pull-up subunit, a first input end of the first pull-up subunit is connected to a first control signal end, a first input end of the second pull-up subunit is connected to a second control signal end, second input ends of the first pull-up subunit and the second pull-up subunit are both connected to a pulse signal end, the first pull-up subunit is used for generating a pull-up signal when a first control signal of the first control signal end is a preset trigger signal, the second pull-up subunit is used for generating a pull-up signal when a second control signal of the second control signal end is a preset trigger signal, high and low levels of the first control signal and the second control signal are alternated, when one control signal is a high level signal, the other control signal is a low level signal. According to the embodiment of the application, the first pull-up unit can normally generate the pull-up signal.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to a shift register circuit and a display panel.
Background
With the development of display technology, display panels with thinner profile, lower cost and power consumption, faster response speed, better color purity and brightness, and higher contrast have been widely used in various electronic products.
In the related art, the display panel includes a shift register circuit, which is mainly used for scanning multi-level scan lines to scan a pixel array electrically connected to the scan lines by scanning the multi-level scan lines, so as to display a picture in cooperation with other circuit structures.
However, the pull-up module generating the pull-up signal in the shift register circuit is continuously influenced by the voltage of the dc voltage, so that the characteristics of the devices in the pull-up module drift, and the pull-up signal cannot be generated.
Disclosure of Invention
The embodiment of the application provides a shift register circuit and a display panel, and can solve the technical problem that a pull-up signal cannot be generated due to the fact that a pull-up module in the shift register circuit is continuously influenced by electric pressure and the characteristics of devices in the pull-up module drift.
In one aspect, an embodiment of the present application provides a shift register circuit, including:
the upward-pulling module comprises a first upward-pulling unit, the first upward-pulling unit comprises a first upward-pulling subunit and a second upward-pulling subunit, a first input end of the first upward-pulling subunit is connected to a first control signal end, a second input end of the first upward-pulling subunit is connected to a pulse signal end, a first input end of the second upward-pulling subunit is connected to a second control signal end, a second input end of the second upward-pulling subunit is connected to the pulse signal end, an output end of the first upward-pulling subunit and an output end of the second upward-pulling subunit are both connected to an output end of the first upward-pulling unit,
wherein the first pull-up subunit is configured to generate a pull-up signal according to a pulse signal of the pulse signal terminal and the first control signal when the first control signal received by the first control signal terminal is a preset trigger signal,
the second pull-up subunit is configured to generate a pull-up signal according to the pulse signal of the pulse signal end and the second control signal when the second control signal received by the second control signal end is a preset trigger signal,
the first control signal and the second control signal are both signals with alternating high and low levels, and in the period when one control signal is a high level signal, the other control signal is a low level signal.
In another aspect, an embodiment of the present application provides a display panel, including: the shift register circuit is provided.
In the shift register circuit and the display panel of the embodiment of the application, the pull-up module includes a first pull-up unit, the first pull-up unit includes a first pull-up subunit and a second pull-up subunit, the pull-up signal is generated during a period when the first control signal received by the first pull-up subunit is the preset trigger signal, and the pull-up signal is generated during a period when the second control signal received by the second pull-up subunit is the preset trigger signal. The first control signal and the second control signal are both signals with alternating high and low levels, and during the period when one control signal is a high level signal, the other control signal is a low level signal. Therefore, the first pull-up subunit and the second pull-up subunit can work alternately to output pull-up signals alternately, the influence of continuous electric pressure of direct-current voltage on the first pull-up subunit and the second pull-up subunit is avoided, characteristic drift of the first pull-up subunit and the second pull-up subunit can be prevented, and the first pull-up unit can normally generate the pull-up signals.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a shift register circuit in the related art.
Fig. 2 is a schematic diagram of an input signal of a pull-up module in a forward scan in the related art.
Fig. 3 is a schematic structural diagram of a first pull-up unit according to an embodiment of the present disclosure.
Fig. 4 is a schematic diagram of an input signal of a first pull-up unit according to an embodiment of the present disclosure.
Fig. 5 is a schematic structural diagram of a shift register circuit according to an embodiment of the present disclosure.
Fig. 6 is a schematic structural diagram of a first pull-up subunit according to an embodiment of the present disclosure.
Fig. 7 is a schematic structural diagram of another first pull-up subunit provided in the embodiment of the present application.
Fig. 8 is a schematic structural diagram of a second pull-up subunit according to an embodiment of the present application.
Fig. 9 is a schematic structural diagram of another second pull-up subunit provided in the embodiment of the present application.
Fig. 10 is a schematic structural diagram of another first pull-up unit according to an embodiment of the present application.
Fig. 11 is a schematic structural diagram of another first pull-up unit according to an embodiment of the present application.
Fig. 12 is a schematic structural diagram of another first pull-up unit according to an embodiment of the present application.
Fig. 13 is a schematic structural diagram of another first pull-up unit according to an embodiment of the present application.
Fig. 14 is a schematic structural diagram of another first pull-up unit according to an embodiment of the present application.
Fig. 15 is a schematic structural diagram of another first pull-up unit according to an embodiment of the present application.
Fig. 16 is a schematic structural diagram of another first pull-up unit according to an embodiment of the present application.
Fig. 17 is a schematic structural diagram of another first pull-up unit according to an embodiment of the present application.
Fig. 18 is a schematic structural diagram of another first pull-up unit according to an embodiment of the present application.
Fig. 19 is a schematic structural diagram of another first pull-up unit according to an embodiment of the present application.
Fig. 20 is a schematic structural diagram of another first pull-up unit according to an embodiment of the present application.
Fig. 21 is a schematic structural diagram of another shift register circuit according to an embodiment of the present disclosure.
Fig. 22 is a schematic diagram of simulation results provided in an embodiment of the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In order to realize the display of the display panel, the scanning signals are provided for the pixel array through the shift register circuit, and the display of the display panel is realized by matching with other circuit structures. Fig. 1 is a schematic structural diagram of a shift register circuit in the related art. As shown in fig. 1, the shift register circuit includes a pull-up module 102, a pull-down module 104, a reset module 106, and an output module 108. The four input terminals of the pull-up module 102 are respectively connected to the high-level signal terminal U2D, the low-level signal terminal D2U, the pulse signal terminal INF during forward scanning, and the pulse signal terminal INB during reverse scanning. An output terminal of the pull-up module 102 is coupled to a first input terminal of the reset module 106 and a first input terminal of the output module 108, respectively. Two input terminals of the pull-down module 104 are respectively connected to two reset signal terminals (RSTF and RSTB), and an output terminal of the pull-down module 104 is connected to a second input terminal of the reset module 106. An output of the reset module 106 is coupled to a second input of the output module 108.
Among them, the pull-up block 102 includes a transistor Tr13 and a transistor Tr14, and the transistor Tr13 operates in the forward direction scan and the transistor Tr14 operates in the reverse direction scan.
However, the pull-up module 102 is continuously influenced by the voltage stress (stress) of the dc voltage, which causes characteristic drift of devices in the pull-up module 102, and thus cannot generate a pull-up signal.
This technical problem is explained below with reference to fig. 2. In the following embodiments, the transistors turned on at a high level are taken as an example, but the transistors in the shift register circuit are not limited to being turned on at a high level or turned on at a low level.
Fig. 2 is a schematic diagram of an input signal of the pull-up module 102 in the forward direction scan in the related art.
As shown in fig. 2, at the time of forward scanning, in the case where the pulse signal received by the gate of the transistor Tr13 from the pulse signal terminal INF is at a high level, the transistor Tr13 is turned on, and then, the transistor Tr13 transmits a high-level signal of the high-level signal terminal U2D to the pull-up control node N2 a. The output module 108 outputs a signal according to the high level signal of the pull-up control node N2 a.
As can be seen from fig. 1 and 2, since the high signal terminal U2D continuously outputs a high signal, the transistor Tr13 continuously receives a high signal, and thus the transistor Tr13 is continuously subjected to the voltage (stress) of the dc voltage. This causes the characteristic drift of the transistor Tr13, which can not effectively pull the pull-up control node N2a high, and thus the output module 108 can not output normally.
In order to solve the above technical problem, an embodiment of the present application provides a shift register circuit and a display panel. The shift register circuit provided in the embodiment of the present application will be described first.
The shift register circuit comprises a pull-up module, and the pull-up module comprises a first pull-up unit. Fig. 3 is a schematic structural diagram of a first pull-up unit according to an embodiment of the present disclosure. As shown in fig. 3, the first pull-up unit 200 includes a first pull-up subunit 202 and a second pull-up subunit 204, a first input terminal of the first pull-up subunit 202 is connected to the first control signal terminal U2D1, a second input terminal of the first pull-up subunit 202 is connected to the pulse signal terminal INF, a first input terminal of the second pull-up subunit 204 is connected to the second control signal terminal U2D2, a second input terminal of the second pull-up subunit 204 is connected to the pulse signal terminal INF, and an output terminal of the first pull-up subunit 202 and an output terminal of the second pull-up subunit 204 are both connected to the output terminal N2a of the first pull-up unit.
The first pull-up subunit 202 is configured to generate a pull-up signal according to the pulse signal of the pulse signal terminal INF and the first control signal when the first control signal received from the first control signal terminal U2D1 is the preset trigger signal.
The second pull-up subunit 204 is configured to generate a pull-up signal according to the pulse signal of the pulse signal terminal INF and the second control signal when the second control signal received from the second control signal terminal U2D2 is the preset trigger signal.
The first control signal and the second control signal are both signals with alternating high and low levels, and during the period when one control signal is a high level signal, the other control signal is a low level signal.
The principle that the output terminal N2a of the first pull-up unit outputs a pull-up signal under the control of the first control signal and the second control signal will be described below with reference to fig. 4.
As shown in fig. 4, when the ith frame is scanned, the first control signal output by the first control signal terminal U2D1 is a high level signal, and at this time, the first pull-up subunit 202 is triggered to operate. The second control signal output by the second control signal terminal U2D2 is a low level signal, and the second pull-up subunit 204 does not operate. And when the first pull-up sub-unit 202 operates, the first pull-up sub-unit 202 outputs a pull-up signal of a high level according to the pulse signal of the pulse signal terminal INF and the first control signal. i can be any positive integer.
Similarly, when the (i + 1) th frame is scanned, the first control signal output by the first control signal terminal U2D1 is a low level signal, and the first pull-up subunit 202 does not operate. The second control signal output by the second control signal terminal U2D2 is a high level signal, which triggers the second pull-up subunit 204 to operate. And when the second pull-up sub-unit 204 operates, the second pull-up sub-unit 204 outputs a high-level pull-up signal according to the pulse signal of the pulse signal terminal INF and the second control signal.
The first control signal and the second control signal are both signals with alternating high and low levels, and during the period when one control signal is a high level signal, the other control signal is a low level signal. As such, the first pull-up sub-unit 202 and the second pull-up sub-unit 204 may be caused to alternately operate to alternately output a pull-up signal. For example, in fig. 4, the first pull-up subunit 202 outputs a pull-up signal when the ith frame scan is performed, and the second pull-up subunit 204 outputs a pull-up signal when the (i + 1) th frame scan is performed.
Thus, since the first pull-up sub-unit 202 and the second pull-up sub-unit 204 do not continuously operate, the first pull-up sub-unit 202 and the second pull-up sub-unit 204 are less affected by the voltage force of the dc voltage, which can prevent the characteristic drift of the first pull-up sub-unit 202 and the second pull-up sub-unit 204, thereby ensuring that the first pull-up unit can normally generate a pull-up signal.
As an example, the transistor Tr13 in fig. 1 may be replaced with the first pull-up unit described above, and the shift register circuit shown in fig. 5 may be obtained. In the shift register circuit shown in fig. 5, the first pull-up sub-unit 202 and the second pull-up sub-unit 204 in the first pull-up unit alternately operate to alternately output pull-up signals, so that characteristic drift of devices in the first pull-up unit can be prevented, and the first pull-up unit can normally generate pull-up signals.
Since one of the pull-up units in the shift register circuit, which generates the pull-up signal, is continuously affected by the high-level voltage during the period of performing the forward scan, characteristic drift occurs in the devices in the pull-up unit. In the time period of carrying out reverse scanning, the other pull-up unit which generates the pull-up signal in the shift register circuit receives a low-level signal, and the influence of a high-level voltage does not exist.
Accordingly, in one or more embodiments of the present application, the first pull-up unit may be a pull-up unit that generates a pull-up signal during a period in which the shift register circuit performs a forward scan. Similar to the function of the transistor Tr13 in fig. 1, the first pull-up unit may be used to generate a pull-up signal during a period of forward scanning.
In the embodiment of the present application, the first pull-up unit is a pull-up unit that generates a pull-up signal during forward scanning in the shift register circuit, and the first pull-up unit is prevented from being continuously affected by a high level voltage during the forward scanning.
In addition, the first pull-up unit is not a pull-up unit (such as the transistor Tr14 in fig. 1) that generates a pull-up signal during reverse scanning in the shift register circuit, that is, the pull-up unit that generates the pull-up signal during reverse scanning does not change, so that not only the shift register circuit is prevented from being changed too much, and the reliability of the shift register circuit during operation is ensured, but also the structure of the shift register circuit is prevented from being too complex.
In one or more embodiments of the present application, as shown in fig. 6, the first pull-up subunit 202 may include:
a first signal transmission device 2022 and a first signal generation device 2024, a first input terminal of the first signal transmission device 2022 is connected to the first control signal terminal U2D1, a second input terminal of the first signal transmission device 2022 is connected to the pulse signal terminal INF, an output terminal of the first signal transmission device 2022 is connected to a first input terminal of the first signal generation device 2024, a second input terminal of the first signal generation device 2024 is connected to the first control signal terminal U2D1, and an output terminal of the first signal generation device 2024 is connected to the output terminal N2a of the first pull-up sub-unit.
The first signal transmitting device 2022 is configured to transmit a pulse signal to the first signal generating device 2024 when the first control signal at the first control signal terminal U2D1 is a predetermined trigger signal (such as a high level signal or a low level signal), and the first signal generating device 2024 is configured to generate a pull-up signal according to the pulse signal transmitted by the first signal transmitting device 2022 and the first control signal at the first control signal terminal U2D1, where the pull-up signal is output to the output terminal N2a of the first pull-up sub-unit 202.
In this way, it is achieved that during periods when the second pull-up subunit 204 is inactive, a pull-up signal is generated by the first pull-up subunit 202. The first pull-up sub-unit 202 includes a first signal transmitting device 2022 and a first signal generating device 2024, the first signal transmitting device 2022 transmits a pulse signal to the first signal generating device 2024, and the first signal generating device 2024 generates a pull-up signal according to the pulse signal. It can be seen that the operation principle of the first signal transmission device 2022 and the first signal generation device 2024 for generating the pull-up signal is relatively simple, and no complicated signal processing is performed, so that the structures of the first signal transmission device 2022 and the first signal generation device 2024 are simple.
In one or more embodiments of the present application, as shown in fig. 7, the first signal transmitting device 2022 may include a first transistor Tr13-1, and the first signal generating device 2024 includes a second transistor Tr 13-2.
A gate of the first transistor Tr13-1 is connected to the first control signal terminal U2D1, a first pole of the first transistor Tr13-1 is connected to the pulse signal terminal INF, a second pole of the first transistor Tr13-1 is connected to a gate of the second transistor Tr13-2, a first pole of the second transistor Tr13-2 is connected to the first control signal terminal U2D1, and a second pole of the second transistor Tr13-2 serves as an output terminal of the first signal generating device.
The first transistor Tr13-1 and the second transistor Tr13-2 may be triggered at a low level or at a high level, and how to generate the pull-up signal through the first pull-up sub-unit 202 will be described below by taking the first transistor Tr13-1 and the second transistor Tr13-2 as an example of being triggered at a high level.
In case that the first control signal of the first control signal terminal U2D1 received at the gate of the first transistor Tr13-1 is a high level signal, the first transistor Tr13-1 is turned on, and the first transistor Tr13-1 transmits the pulse signal of the pulse signal terminal INF to the gate of the second transistor Tr 13-2.
When the pulse signal of the pulse signal terminal INF is a high-level signal, the second transistor Tr13-2 is turned on, and when the first control signal of the first control signal terminal U2D1 is a high-level signal, the second pole of the second transistor Tr13-2 outputs a pull-up signal of a high level. Thereby, a pull-up signal generation by the first pull-up subunit is achieved.
Since the first signal transmission device 2022 and the first signal generation device 2024 each use one transistor to implement their functions, the structure of the first pull-up subunit 202 formed by the first signal transmission device 2022 and the first signal generation device 2024 is simple.
In one or more embodiments of the present application, as shown in fig. 8, the second pull-up subunit 204 may include:
a second signal transmission device 2042 and a second signal generation device 2044, a first input end of the second signal transmission device 2042 is connected to the second control signal terminal U2D2, a second input end of the second signal transmission device 2042 is connected to the pulse signal terminal INF, an output end of the second signal transmission device 2042 is connected to a first input end of the second signal generation device 2044, a second input end of the second signal generation device 2044 is connected to the second control signal terminal U2D2, and an output end of the second signal generation device 2044 is connected to the output end of the second pull-up sub-unit 204.
The second signal transmission device 2042 is configured to transmit the pulse signal at the pulse signal terminal INF to the second signal generation device 2044 when the second control signal at the second control signal terminal U2D2 is the preset trigger signal, and the second signal generation device 2044 is configured to generate the pull-up signal according to the pulse signal and the second control signal transmitted by the second signal transmission device 2042.
In this way, it is achieved that during periods when the first pull-up subunit 202 is inactive, a pull-up signal is generated by the second pull-up subunit 204. The second pull-up sub-unit 204 includes a second signal transmission device 2042 and a second signal generation device 2044, the second signal transmission device 2042 transmits the pulse signal to the second signal generation device 2044, and then the second signal generation device 2044 generates a pull-up signal according to the pulse signal. As can be seen, the operating principle of the second signal transmission device 2042 and the second signal generation device 2044 for generating the pull-up signal is relatively simple, and no complex signal processing is performed, so that the second signal transmission device 2042 and the second signal generation device 2044 have simple structures.
In one or more embodiments of the present application, as shown in fig. 9, the second signal transmitting device 2042 may include a third transistor Tr13-3, and the second signal generating device 2044 includes a fourth transistor Tr 13-4.
A gate of the third transistor Tr13-3 is connected to the second control signal terminal U2D2, a first pole of the third transistor Tr13-3 is connected to the pulse signal terminal INF, a second pole of the third transistor Tr13-3 is connected to a gate of the fourth transistor Tr13-4, a first pole of the fourth transistor Tr13-4 is connected to the second control signal terminal U2D2, and a second pole of the fourth transistor Tr13-4 serves as an output terminal of the second signal generating device 2044.
The third transistor Tr13-3 and the fourth transistor Tr13-4 may be triggered by a low level or a high level, and it is described below how the pull-up signal is generated by the second pull-up sub-unit 204 by taking the third transistor Tr13-3 and the fourth transistor Tr13-4 as an example of being triggered by a high level.
In case that the second control signal of the second control signal terminal U2D2 received at the gate of the third transistor Tr13-3 is a high level signal, the third transistor Tr13-3 is turned on, and the third transistor Tr13-3 transmits the pulse signal of the pulse signal terminal INF to the gate of the fourth transistor Tr 13-4.
The fourth transistor Tr13-4 is turned on when the pulse signal of the pulse signal terminal INF is a high level signal, and then the second pole of the fourth transistor Tr13-4 outputs a pull-up signal of a high level when the second control signal of the second control signal terminal U2D2 is a high level signal. Thereby, generation of a pull-up signal by the second pull-up subunit 204 is achieved.
Since the second signal transmission device 2042 and the second signal generation device 2044 respectively use one transistor to implement their functions, the structure of the second pull-up subunit 204 formed by the second signal transmission device 2042 and the second signal generation device 2044 is relatively simple.
Note that the first poles of the first to fourth transistors Tr13-1 to Tr13-4 may be collectors, and the second poles of the first to fourth transistors Tr13-1 to Tr13-4 may be emitters.
Alternatively, the first poles of the first to fourth transistors Tr13-1 to Tr13-4 may be emitters, and the second poles of the first to fourth transistors Tr13-1 to Tr13-4 may be collectors.
It should also be noted that the above embodiments can be combined, for example, the embodiments of fig. 6 and fig. 8 are combined, and the first pull-up unit shown in fig. 10 is obtained. As shown in fig. 10, the first pull-up unit includes a first pull-up sub-unit 202 shown in fig. 6 and a second pull-up sub-unit 204 shown in fig. 8, and the first pull-up sub-unit 202 and the second pull-up sub-unit 204 alternately operate to alternately output a pull-up signal.
As another example, combining the embodiments of fig. 7 and 9, a first pull-up unit as shown in fig. 11 is obtained. As shown in fig. 11, the first pull-up unit includes a first pull-up sub-unit 202 shown in fig. 7 and a second pull-up sub-unit 204 shown in fig. 9, and the first pull-up sub-unit 202 and the second pull-up sub-unit 204 alternately operate to alternately output a pull-up signal.
Of course, the combination of the embodiments is not limited to the above combination, and is not limited thereto.
In one or more embodiments of the present application, as shown in fig. 12, the first pull-up unit may further include:
a first control subunit 206, having a first input terminal connected to the power supply terminal VGL, an output terminal connected to the first signal generating device 2024, the first control subunit 206 being configured to control the first pull-up subunit 202 not to operate during the operation of the second pull-up subunit 204.
Since the first control subunit 206 can control the first pull-up subunit 202 not to operate during the period when the second pull-up subunit 204 operates (i.e., during the period when the second pull-up subunit 204 outputs the pull-up signal), it is avoided that the first pull-up subunit 202 also outputs the pull-up signal during the period when the second pull-up subunit 204 outputs the pull-up signal, and it is ensured that the first pull-up unit can normally output the pull-up signal.
In one or more embodiments of the present application, as shown in fig. 13, the first control subunit 206 may include:
a fifth transistor Tr-5, a gate of the fifth transistor Tr-5 being connected to the second control signal terminal U2D2, a first pole of the fifth transistor Tr-5 being connected to the power supply terminal VGL, a second pole of the fifth transistor Tr-5 being connected to the first input terminal of the first signal generating device 2024. In fig. 13, a first input terminal of the first signal generating device 2024 is a gate of the second transistor Tr 13-2.
How the fifth transistor Tr-5 can control the first pull-up sub-unit 202 not to be operated during the operation of the second pull-up sub-unit 204 will be described.
When the second control signal of the second control signal terminal U2D2 is a high level signal, the second pull-up sub-unit 204 operates. Since the gate of the fifth transistor Tr-5 is also connected to the second control signal terminal U2D2, the fifth transistor Tr-5 is turned on during the operation of the second pull-up sub-unit 204, and the fifth transistor Tr-5 transmits a low-level signal of the power supply terminal VGL to the gate of the second transistor Tr13-2, thereby ensuring that the gate of the second transistor Tr13-2 is at a low level and preventing the second transistor Tr13-2 from being turned on. This realizes that the first pull-up subunit 202 does not operate while the second pull-up subunit 204 operates.
In the embodiment of the present application, the first control subunit 206 includes a fifth transistor Tr-5, and the first pull-up subunit 202 is controlled not to operate during the operation of the second pull-up subunit 204 by the fifth transistor Tr-5. Therefore, the structure of the first control subunit 206 is relatively simple, and the cost of the shift register circuit is avoided from being too high.
In one or more embodiments of the present application, as shown in fig. 14, the first control subunit 206 may include:
one end of the first capacitor C1, the first capacitor C1 is connected to the power supply terminal VGL, and the other end of the first capacitor C1 is connected to the first input terminal of the first signal generating device 2024. In fig. 14, a first input terminal of the first signal generating device 2024 is a gate of the second transistor Tr 13-2.
The following describes how the first capacitor C1 can control the first pull-up sub-unit 202 to be inactive during the operation of the second pull-up sub-unit 204.
During the operation of the second pull-up sub-unit 204, the power supply terminal VGL charges the first capacitor C1, such that a low level signal of the power supply terminal VGL is transmitted to the gate of the second transistor Tr13-2, thereby ensuring that the gate of the second transistor Tr13-2 is at a low level and preventing the second transistor Tr13-2 from being turned on. This realizes that the first pull-up subunit 202 does not operate while the second pull-up subunit 204 operates.
In the embodiment of the present application, the first control subunit 206 includes a first capacitor C1, and the first pull-up subunit 202 is controlled to be not operated during the operation of the second pull-up subunit 204 by the first capacitor C1. Therefore, the structure of the first control subunit 206 is relatively simple, and the cost of the shift register circuit is avoided from being too high.
In one or more embodiments of the present application, as shown in fig. 15, the first pull-up unit may further include:
a second control subunit 208, a first input terminal of which is connected to the power supply terminal VGL, an output terminal of the second control subunit 208 is connected to a first input terminal of the second signal generating device 2042, and the second control subunit 208 is configured to control the second pull-up subunit 204 not to operate during the operation of the first pull-up subunit 202.
Since the second control subunit 208 can control the second pull-up subunit 204 not to operate during the period when the first pull-up subunit 202 operates (i.e., during the period when the first pull-up subunit 202 outputs the pull-up signal), it can be avoided that the second pull-up subunit 204 also outputs the pull-up signal when the first pull-up subunit 202 outputs the pull-up signal, and it is ensured that the first pull-up unit can normally output the pull-up signal.
In one or more embodiments of the present application, as shown in fig. 16, the second control subunit 208 may include:
a sixth transistor Tr-6 having a gate electrode connected to the first control signal terminal U2D1, a first electrode connected to the power supply terminal VGL of the sixth transistor Tr-6, and a second electrode connected to the first input terminal of the second signal generating device of the sixth transistor Tr-6. In fig. 16, the first input terminal of the second signal generating device may be a gate of the fourth transistor Tr 13-4.
How the sixth transistor Tr-6 can control the second pull-up sub-unit 204 not to be operated during the operation of the first pull-up sub-unit 202 will be described.
When the first control signal of the first control signal terminal U2D1 is a high level signal, the first pull-up sub-unit 202 operates. Since the gate of the sixth transistor Tr-6 is also connected to the first control signal terminal U2D1, the sixth transistor Tr-6 is turned on during the operation of the first pull-up sub-unit 202, and the sixth transistor Tr-6 transmits a low-level signal of the power supply power source terminal VGL to the gate of the fourth transistor Tr13-4, thereby ensuring that the gate of the fourth transistor Tr13-4 is at a low level and preventing the gate of the fourth transistor Tr13-4 from being turned on. This realizes that the second pull-up subunit 204 does not operate while the first pull-up subunit 202 operates.
In the embodiment of the present application, the second control subunit 208 includes a sixth transistor Tr-6, and the second pull-up subunit 204 is controlled not to operate by the sixth transistor Tr-6 during the period when the first pull-up subunit 202 operates. Therefore, the structure of the second control subunit 208 is relatively simple, and the cost of the shift register circuit is avoided from being too high.
In one or more embodiments of the present application, as shown in fig. 17, the second control subunit 208 may include:
and a second capacitor C2, one end of the second capacitor C2 being connected to the power supply terminal VGL, and the other end of the second capacitor C2 being connected to the first input terminal of the second signal generating device. In fig. 17, the first input terminal of the second signal generating device may be a gate of the fourth transistor Tr 13-4.
The following describes how the second capacitor C2 can control the second pull-up sub-unit 204 to be inactive during the operation of the first pull-up sub-unit 202.
During the operation of the first pull-up sub-unit 202, the power supply terminal VGL charges the second capacitor C2, such that a low level signal of the power supply terminal VGL is transmitted to the gate of the fourth transistor Tr13-4, thereby ensuring that the gate of the fourth transistor Tr13-4 is at a low level and preventing the fourth transistor Tr13-4 from being turned on. This realizes that the second pull-up subunit 204 does not operate while the first pull-up subunit 202 operates.
In the embodiment of the present application, the second control subunit 208 includes a second capacitor C2, and the sixth second capacitor C2 can control the second pull-up subunit 204 not to operate during the operation of the first pull-up subunit 202. Therefore, the structure of the second control subunit 208 is relatively simple, and the cost of the shift register circuit is avoided from being too high.
It should be noted that the above embodiments can be combined, for example, the embodiments of fig. 12 and fig. 15 are combined to obtain the first pull-up unit shown in fig. 18. For another example, the embodiments of fig. 13 and 16 are combined to obtain the first pull-up unit shown in fig. 19. As another example, combining the embodiments of fig. 14 and 17 results in a first pull-up unit as shown in fig. 20. Of course, the combination of the embodiments is not limited to the above cases, and other combinations are also possible, for example, the combination of the embodiments in fig. 13 and 17, the combination of the embodiments in fig. 14 and 16, and so on.
Note that, the above description is made by taking a transistor which is turned on at a high level as an example, and therefore, the power supply terminal described above supplies a low level signal. On the other hand, if the transistors Tr3-1 to Tr3-4 are transistors turned on at a low level, the power supply terminal provides a high level signal.
In one or more embodiments of the present application, the pull-up module may further include:
and for the first pull-up unit and the second pull-up unit, one of the pull-up units is used for generating a pull-up signal in a forward scanning time period, and the other pull-up unit is used for generating a pull-up signal in a reverse scanning time period.
As shown in fig. 21, the pull-up module includes a second pull-up unit 300 in addition to the first pull-up unit 200, and in fig. 21, the second pull-up unit 300 is a transistor Tr 14.
In the embodiment of the present application, one of the first pull-up unit and the second pull-up unit is configured to generate a pull-up signal in a forward scanning period, and the other pull-up unit is configured to generate a pull-up signal in a reverse scanning period. Therefore, the shift register circuit can provide a pull-up signal not only in forward scanning but also in reverse scanning.
In order to better explain the embodiments of the present application, the signals output by the shift register circuits are simulated, and the simulation results are combined for explanation.
First, the timing of the simulation: 300 hertz (Hz) with Touch Panel Term (TP Term).
The simulated model is the shift register circuit shown in fig. 1 and the shift register circuit provided in the present application, respectively. Based on the shift register circuit shown in fig. 1 and the shift register circuit provided in the present application, simulation results are shown in table 1:
TABLE 1
FIG. 22 is a diagram illustrating simulation results according to an embodiment of the present application. Two solid lines shown in fig. 22 represent output signals of the shift register circuit shown in fig. 1 and output signals of the shift register circuit provided in the present application before Reliability Analysis (RA), and two dotted lines shown in fig. 22 represent output signals of the shift register circuit shown in fig. 1 and output signals of the shift register circuit provided in the present application after RA. Here, RA may be an analysis of the shift register circuit under high temperature, high pressure, and the like.
As can be seen from table 1 and fig. 22, the output signals of the shift register circuit shown in fig. 1 and the output signals of the shift register circuit provided in the present application are substantially coincident and have no significant difference before RA or after RA. Further, the rise time of the output signal of the shift register circuit shown in fig. 1 corresponds to the rise time of the output signal of the shift register circuit provided in the present application, and the fall time of the output signal of the shift register circuit shown in fig. 1 corresponds to the fall time of the output signal of the shift register circuit provided in the present application.
The present application also provides a display panel, including: the shift register circuit according to any one of the above embodiments. The display panel has the same technical effect as the shift register circuit, and the description is not repeated herein.
As described above, only the specific embodiments of the present application are provided, and it can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present application, and these modifications or substitutions should be covered within the scope of the present application.
Claims (14)
1. A shift register circuit, comprising:
the upward-pulling module comprises a first upward-pulling unit, the first upward-pulling unit comprises a first upward-pulling subunit and a second upward-pulling subunit, a first input end of the first upward-pulling subunit is connected to a first control signal end, a second input end of the first upward-pulling subunit is connected to a pulse signal end, a first input end of the second upward-pulling subunit is connected to a second control signal end, a second input end of the second upward-pulling subunit is connected to the pulse signal end, an output end of the first upward-pulling subunit and an output end of the second upward-pulling subunit are both connected to an output end of the first upward-pulling unit,
wherein the first pull-up subunit is configured to generate a pull-up signal according to a pulse signal of the pulse signal terminal and the first control signal when the first control signal received by the first control signal terminal is a preset trigger signal,
the second pull-up subunit is configured to generate a pull-up signal according to the pulse signal of the pulse signal end and the second control signal when the second control signal received by the second control signal end is a preset trigger signal,
the first control signal and the second control signal are both signals with alternating high and low levels, and in the period when one control signal is a high level signal, the other control signal is a low level signal.
2. The shift register circuit of claim 1, wherein the first pull-up subunit comprises:
a first signal transmission device and a first signal generation device, wherein a first input end of the first signal transmission device is connected to the first control signal end, a second input end of the first signal transmission device is connected to the pulse signal end, an output end of the first signal transmission device is connected to a first input end of the first signal generation device, a second input end of the first signal generation device is connected to the first control signal end, and an output end of the first signal generation device is connected to an output end of the first pull-up sub-unit;
wherein the first signal transmitting device is configured to transmit the pulse signal to the first signal generating device if the first control signal is the preset trigger signal,
the first signal generating device is used for generating a pull-up signal according to the pulse signal and the first control signal transmitted by the first signal transmitting device.
3. The shift register circuit according to claim 2, wherein the first signal transmission device includes a first transistor, the first signal generation device includes a second transistor,
the gate of the first transistor is connected to the first control signal terminal, the first pole of the first transistor is connected to the pulse signal terminal, the second pole of the first transistor is connected to the gate of the second transistor, the first pole of the second transistor is connected to the first control signal terminal, and the second pole of the second transistor is used as the output terminal of the first signal generating device.
4. The shift register circuit of claim 1, wherein the second pull-up subunit comprises:
a second signal transmission device and a second signal generation device, wherein a first input end of the second signal transmission device is connected to the second control signal end, a second input end of the second signal transmission device is connected to the pulse signal end, an output end of the second signal transmission device is connected to a first input end of the second signal generation device, a second input end of the second signal generation device is connected to the second control signal end, and an output end of the second signal generation device is connected to an output end of the second pull-up sub-unit;
wherein the second signal transmitting device is configured to transmit the pulse signal to the second signal generating device if the second control signal is the preset trigger signal,
the second signal generating device is used for generating a pull-up signal according to the pulse signal and the second control signal transmitted by the second signal transmitting device.
5. The shift register circuit according to claim 4, wherein the second signal transmission device includes a third transistor, the second signal generation device includes a fourth transistor,
a gate of the third transistor is connected to the second control signal terminal, a first pole of the third transistor is connected to the pulse signal terminal, a second pole of the third transistor is connected to a gate of the fourth transistor, a first pole of the fourth transistor is connected to the second control signal terminal, and a second pole of the fourth transistor is used as an output terminal of the second signal generating device.
6. The shift register circuit according to claim 2, wherein the first pull-up unit further comprises:
a first control subunit, a first input end of which is connected to a power supply terminal, an output end of which is connected to a first input end of the first signal generating device, and the first control subunit is configured to control the first pull-up subunit not to operate during an operation period of the second pull-up subunit.
7. The shift register circuit according to claim 6, wherein the first control subunit comprises:
a fifth transistor having a gate connected to the second control signal terminal, a first pole connected to the power supply terminal, and a second pole connected to the first input terminal of the first signal generating device.
8. The shift register circuit according to claim 6, wherein the first control subunit comprises:
and one end of the first capacitor is connected to the power supply end, and the other end of the first capacitor is connected to the first input end of the first signal generating device.
9. The shift register circuit according to claim 4, wherein the first pull-up unit further comprises:
a second control subunit, a first input end of which is connected to a power supply terminal, an output end of which is connected to the first input end of the second signal generating device, and the second control subunit is configured to control the second pull-up subunit not to operate during an operation period of the first pull-up subunit.
10. The shift register circuit according to claim 9, wherein the second control subunit comprises:
a sixth transistor having a gate connected to the first control signal terminal, a first pole connected to the power supply terminal, and a second pole connected to the first input terminal of the second signal generating device.
11. The shift register circuit according to claim 9, wherein the second control subunit comprises:
and one end of the second capacitor is connected to the power supply end, and the other end of the second capacitor is connected to the first input end of the second signal generating device.
12. The shift register circuit according to any one of claims 1 to 11, wherein the pull-up module further comprises:
and for the first pull-up unit and the second pull-up unit, one pull-up unit is used for generating a pull-up signal in a forward scanning time period, and the other pull-up unit is used for generating a pull-up signal in a reverse scanning time period.
13. The shift register circuit according to any one of claims 1 to 11, wherein the first pull-up unit is: and the pull-up unit generates a pull-up signal in a time period of forward scanning of the shift register circuit.
14. A display panel, comprising: a shift register circuit as claimed in any one of claims 1 to 13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011547394.4A CN112687220B (en) | 2020-12-24 | 2020-12-24 | Shift register circuit and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011547394.4A CN112687220B (en) | 2020-12-24 | 2020-12-24 | Shift register circuit and display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112687220A true CN112687220A (en) | 2021-04-20 |
| CN112687220B CN112687220B (en) | 2024-03-15 |
Family
ID=75451953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011547394.4A Active CN112687220B (en) | 2020-12-24 | 2020-12-24 | Shift register circuit and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112687220B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110234554A1 (en) * | 2010-03-26 | 2011-09-29 | Epson Imaging Devices Corporation | Shift register, scanning-line drive circuit, data-line drive circuit, electro-optical device, and electronic apparatus |
| EP2743930A1 (en) * | 2012-12-14 | 2014-06-18 | BOE Technology Group Co., Ltd. | Bidirectional shift register unit, gate driving circuit and display device |
| CN105405417A (en) * | 2014-09-05 | 2016-03-16 | 乐金显示有限公司 | Shift Register And Display Device Using The Same |
| CN107845403A (en) * | 2017-11-07 | 2018-03-27 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
| CN108806611A (en) * | 2018-06-28 | 2018-11-13 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit, display device and driving method |
| WO2020015547A1 (en) * | 2018-07-18 | 2020-01-23 | 京东方科技集团股份有限公司 | Shift register unit, driving method therefor, gate driving circuit and display device |
-
2020
- 2020-12-24 CN CN202011547394.4A patent/CN112687220B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110234554A1 (en) * | 2010-03-26 | 2011-09-29 | Epson Imaging Devices Corporation | Shift register, scanning-line drive circuit, data-line drive circuit, electro-optical device, and electronic apparatus |
| EP2743930A1 (en) * | 2012-12-14 | 2014-06-18 | BOE Technology Group Co., Ltd. | Bidirectional shift register unit, gate driving circuit and display device |
| CN105405417A (en) * | 2014-09-05 | 2016-03-16 | 乐金显示有限公司 | Shift Register And Display Device Using The Same |
| CN107845403A (en) * | 2017-11-07 | 2018-03-27 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
| CN108806611A (en) * | 2018-06-28 | 2018-11-13 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit, display device and driving method |
| WO2020015547A1 (en) * | 2018-07-18 | 2020-01-23 | 京东方科技集团股份有限公司 | Shift register unit, driving method therefor, gate driving circuit and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112687220B (en) | 2024-03-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104103253B (en) | Emission electrode scanning circuit, array base palte and display device | |
| US9257978B2 (en) | Multiplex driving circuit | |
| US10168977B2 (en) | Bidirectional scanning unit, driving method and gate driving circuit | |
| WO2017071377A1 (en) | Display drive method, display drive circuit, and display device, used for display panel | |
| US9779681B2 (en) | Shift register unit, gate driving circuit and display device | |
| CN108389554B (en) | Grid scanning driving circuit and liquid crystal display device | |
| KR102043534B1 (en) | GOA drive circuits and flat panel displays for flat panel displays | |
| US9613555B2 (en) | Pixel driving circuit including signal splitting circuits, driving method, display panel, and display device | |
| CN104361852A (en) | Shifting register, gate drive circuit and display device | |
| CN103456269A (en) | Shift register circuit | |
| CN101359107A (en) | Liquid crystal display device and driving method thereof | |
| US9612682B2 (en) | Touch panel and method for detecting the same | |
| US9727162B2 (en) | GOA driving circuit applied for flat panel display device and flat panel display device | |
| US9325309B2 (en) | Gate driving circuit and driving method thereof | |
| CN105047153A (en) | Driving circuit and display device | |
| US10673418B2 (en) | Level shifter circuit | |
| CN204029332U (en) | Emitting electrode sweep circuit, array base palte and display device | |
| CN112687220A (en) | Shift register circuit and display panel | |
| CN101324727B (en) | LCD and drive method thereof | |
| CN101154360B (en) | Image display system and method for driving display component | |
| CN109523971B (en) | Display panel drive circuit and display device | |
| CN108446055B (en) | Pixel detection circuit, driving method and touch display panel | |
| TWI649597B (en) | Display panel and gate drive | |
| CN106652949B (en) | Gate driving circuit and liquid crystal display device | |
| CN210378428U (en) | Control circuit and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |