TWI649597B - Display panel and gate drive - Google Patents

Abstract

A display panel includes at least one display block and a gate driving device. The display block includes N × N pixels to form a matrix of N columns and N rows. N is a positive integer greater than or equal to 3. The gate driving device is used to drive each of the N × N pixels according to a sequence. After the gate driving device drives a first pixel of the pixels located in the Kth column and the Nth row in the matrix, then the gate driving device drives the pixels located in the first column and the (N-K + 2) A second pixel of the row. K is a positive integer between 2 and N.

Description

Display panel and gate driving device

The embodiments described in this disclosure are related to a display-related technology, and particularly to a display panel and a gate driving device.

In display technology, block driving has been developed. In the related art, with the improvement of the resolution, the difference between the addressing frequency in the X direction and the addressing frequency in the Y direction will increase correspondingly. In this case, the stabilizing capacitor needs to be added to the gate drive circuit to achieve the purpose of voltage stabilization. However, the stabilizing capacitor is not conducive to narrowing the display panel. It can be seen that the existing display technology still has inconveniences and defects.

An embodiment of the present disclosure relates to a display panel. The display panel includes at least one display block and a gate driving device. The display block includes N × N pixels to form a matrix of N columns and N rows. N is a positive integer greater than or equal to 3. The gate driving device is used to drive each of the N × N pixels according to a sequence. When the gate driving device drives the pixels, After a first pixel in the Kth column and the Nth row in the matrix, the gate driving device then drives a second pixel in the pixels located in the first column (N-K + 2) th row in the matrix. K is a positive integer between 2 and N.

An embodiment of the present disclosure relates to a display panel. The display panel includes at least one display block and a first gate driving circuit. The first gate driving circuit is used to drive N row address lines of the display block. N is a positive integer greater than or equal to 4. The first gate driving circuit includes an N-level driving circuit. Each of the N-level driving circuits is used to output a displacement signal to drive a corresponding one of the row address lines. When a (N-1) th level driving circuit in the Nth level driving circuit outputs a displacement signal of the (N-1) th level driving circuit according to the displacement signal output by the previous level driving circuit, the (N-1) th level driving circuit Selectively outputting a displacement signal again according to the potential of a first driving signal and the displacement signal output by an N-th driving circuit in the N-level driving circuit.

An embodiment of the present disclosure relates to a gate driving device. The gate driving device is used to drive N address lines of a display panel. N is a positive integer greater than or equal to 4. The gate driving device includes an N-level driving circuit. Each of the N-level driving circuits includes a node and a first switching unit. The first switch unit transmits a clock signal to an output terminal of the first switch unit as a displacement signal according to the potential of the node to drive a corresponding one of the N address lines. A (N-1) -th level driving circuit in the N-level driving circuit includes a second switching unit, a third switching unit, and a fourth switching unit. The second switching unit is configured to transmit a first level voltage to a node of the (N-1) th driving circuit according to a displacement signal output by a (N-2) th driving circuit in the Nth driving circuit. The third switch unit has an input terminal and an output terminal, and A displacement signal output from an N-th level driving circuit in the driving circuit is turned on. An output terminal of the third switching unit is connected to a node of the (N-1) th stage driving circuit. The fourth switching unit is used for transmitting a second level voltage to the input terminal of the third switching unit according to a first driving signal. The second level voltage is opposite to the first level voltage, the first switching unit is turned on according to the first level voltage and turned off according to the second level voltage.

In summary, the display panel drives the pixels in the display block in a specific order, so that the addressing frequency in the X direction is the same as the addressing frequency in the Y direction. In this way, it is possible to avoid adding an additional voltage stabilizing capacitor to the display panel.

100‧‧‧ display panel

120‧‧‧Display block

140‧‧‧Gate driving device

140X‧‧‧Gate driving circuit

140Y‧‧‧Gate driving circuit

160‧‧‧Wireless Data Module

X1, X2, X3, X4, X5‧‧‧ line address lines

Y1, Y2, Y3, Y4, Y5‧‧‧column address lines

A‧‧‧Area

_{P 11 ~ P 15, P 21} ~ P 25, P 31 ~ P 35, P 41 ~ P 45, P 51 ~ P 55 ‧‧‧ pixels

D1, D2, D3, D4, D5‧‧‧ data cable

S1, S2‧‧‧‧ Switching unit

C0, C1, C2‧‧‧Capacitors

302, 304, 306, 308, 602, 604, 606, 608‧‧‧ drive circuit

ST1, ST2‧‧‧ driving signals

CK‧‧‧Clock signal

XCK‧‧‧clock signal

G _X (1), G _X (2), G _X (3), G _X (4), G _X (5), G _X (M), G _X (M-1), G _X (M + 1 ), G _X (N), G _Y (1), G _Y (2), G _Y (3), G _Y (4), G _Y (5) ‧‧‧ displacement signal

T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13

M1 ~ M17, SW1, SW2, SW3, SW4‧‧‧ switch unit

V1, V2‧‧‧level voltage

Q, N1‧‧‧node

3020, 3040, 3060, 3080‧‧‧ pull-down circuit

VGL‧‧‧Voltage

ST1_i, ST2_i, ST1_j, ST2_j‧‧‧ Control signals

ST2_y‧‧‧Signal

In order to make the above and other objects, features, advantages, and embodiments of the present disclosure more comprehensible, the description of the drawings is as follows: FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present disclosure; Fig. 2 is a detailed schematic diagram of a region in the display panel of Fig. 1; Figs. 3A to 3D are circuit diagrams of different stages of the gate driving circuit of the gate driving circuit of Fig. 1 according to an embodiment of the disclosure; Figure 4 is a timing chart of the driving direction in the X direction at the upper right; Figure 5 is a timing chart of the driving direction in the X direction at the lower left; Figures 6A to 6D are drawings according to an embodiment of the disclosure; FIG. 1 is a circuit diagram of the driving circuits of different stages in the gate driving circuit; FIG. 7 is a timing diagram of the Y direction in the lower left driving period; and FIG. 8 is a timing diagram of the Y direction in the upper right driving period.

The following is a detailed description with examples and the accompanying drawings, but the examples provided are not intended to limit the scope covered by this disclosure, and the description of the structure operation is not used to limit the order of its implementation, and any recombination of components The structure and the devices with the same effect are all the scope covered by this disclosure. In addition, the drawings are for illustrative purposes only, and are not drawn to the original dimensions. In order to facilitate understanding, the same elements or similar elements in the following description will be described with the same symbols.

The terms used throughout the specification and the scope of patent applications, unless otherwise specified, usually have the ordinary meaning of each term used in this field, in the content disclosed here, and in special content.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to (or coupled to)" another element, it can be directly on or in contact with the other element. Another element is connected (or coupled), or an intermediate element may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to (or coupled to)" another element, there are no intervening elements present. As used herein, "connected (or coupled)" may refer to physical and / or electrical connections (or electrically coupled).

Regarding the "first", "second", "third", etc. used in this article, they are not meant to specifically refer to the order or order, nor are they used to limit this disclosure. They are only used to distinguish the same technology. Elements or operations described by words.

Please refer to Figure 1. FIG. 1 is a diagram illustrating an embodiment according to the present disclosure. A schematic diagram of a display panel 100 is shown. In some embodiments, the display panel 100 includes at least one display block 120 and a gate driving device 140.

Taking the example in FIG. 1, the display panel 100 includes a plurality of display blocks 120. The gate driving device 140 is used to drive the display blocks 120. In some embodiments, the display panel 100 adopts a block driving technology. In these embodiments, the gate driving device 140 can synchronously drive the display blocks 120 to perform screen display.

In some embodiments, each display block 120 includes N × N pixels. These pixels form a matrix having N columns and N rows. In some embodiments, N is a positive integer greater than or equal to three.

In some embodiments, the gate driving device 140 may use a gate on array (GOA) technology, and the display panel 100 will have the advantage of narrowing, but is not limited to this GOA technology. In some embodiments, the gate driving device 140 includes a plurality of gate driving circuits 140X and a plurality of gate driving circuits 140Y. The gate driving circuits 140X and 140Y are used to drive pixels in the display blocks 120.

In some embodiments, if each display block 120 includes 5 × 5 pixels, each display block 120 further includes five row address lines X1 to X5 and five column address lines Y1 to Y5. The row address lines X1 to X5 are electrically coupled to the pixels in the display block 120 and the gate driving circuit 140X. The column address lines Y1 to Y5 are electrically coupled to the pixels in the display block 120 and the gate driving circuit 140Y. In this way, the gate driving circuit 140X and the gate driving circuit 140Y can respectively drive the row address lines X1 to X5 and the column address lines. Y1 ~ Y5, and then driving the pixels in the display block 120.

The numbers of the gate driving circuits, display blocks, row address lines, and column address lines described above are for example purposes only. Various numbers of gate drive circuits, display blocks, row address lines, and column address lines are within the scope of this disclosure.

Please refer to Figure 2. FIG. 2 is a detailed schematic diagram of an area A in the display panel 100 of FIG. 1. For ease of understanding, similar elements in FIG. 2 to those in FIG. 1 will be assigned the same reference numerals.

In some embodiments, the display panel 100 further includes at least one wireless data module 160 and a plurality of data lines D1 to D5. The wireless data module 160 is electrically coupled to the data lines D1 to D5. The data lines D1 to D5 are electrically coupled to the pixels in the display block 120. In some embodiments, the wireless data module 160 receives data signals through wireless transmission. The wireless data module 160 transmits the received data signals to corresponding pixels in the display block 120 through the data lines D1 to D5, so that the corresponding pixels display corresponding grayscale values. In some embodiments, the wireless data module 160 is implemented by an induction coil, but is not limited thereto. In other embodiments, various components capable of implementing the wireless data module 160 are within the scope of consideration of this disclosure.

Taking the second diagram as an example, the display block 120 includes 5 × 5 pixels. The display block 120 may include 25 pixels, that is, pixels P ₁₁ to P ₁₅ , pixels P ₂₁ to P ₂₅ , pixels P ₃₁ to P ₃₅ , pixels P ₄₁ to P _45, and pixels P ₅₁ to P ₅₅ . In some embodiments, the row address lines X1 to X5 and the column address lines Y1 to Y5 are arranged in an interlace manner (for example, a vertical manner) to form N × N nodes. The pixels are respectively disposed on the nodes to form a display matrix having N columns and N rows.

For ease of understanding, FIG. 2 only illustrates a detailed internal diagram of the pixel P11. In some embodiments, the pixel P11 includes a switching unit S1, a switching unit S2, and a capacitor C0.

The above-mentioned switch units each have a control terminal and two connection terminals. The capacitor C0 has two connection terminals. In some embodiments, the switching units are implemented by a thin film transistor TFT. In these embodiments, the two connection ends of any switch unit are a source terminal and a drain terminal, respectively, and the control terminal of the switch unit is a gate terminal. Various elements that enable these switching units are within the scope of this disclosure.

In some embodiments, the first connection terminal of the switching unit S1 is electrically coupled to the data line D1. The second connection terminal of the switching unit S1 is electrically coupled to the first connection terminal of the switching unit S2. The second connection terminal of the switching unit S2 is electrically coupled to the first connection terminal of the capacitor C0. The second connection terminal of the capacitor C0 is electrically coupled to a predetermined potential terminal (for example, a ground terminal). The row address line X1 is electrically coupled to the control terminal of the switching unit S1. In this way, the gate driving circuit 140X can output the displacement signal G _X (1) to the row address line X1 to turn on the switching unit S1. The column address line Y1 is electrically coupled to the control terminal of the switching unit S2. In this way, the gate driving circuit 140Y can output the displacement signal G _Y (1) to the column address line Y1 to turn on the switching unit S2. When the pixel P ₁₁ in the switch unit S1 and the switch unit S2 are turned on, the representative pixel P ₁₁ is driven. In this case, the wireless data module 160 can transmit the corresponding data signal to the first connection end of the switching unit S1 through the data line D1. The data signal is then transmitted to the first connection terminal of the capacitor C0 via the switch unit S1 and the switch unit S2 to charge the capacitor C0. In this way, the pixel P ₁₁ can display a corresponding gray level value according to the data signal.

Since the elements and driving methods of the remaining pixels are similar to those of the pixel P ₁₁ , they are not repeated here.

In some embodiments, the gate driving circuits 140X and 140Y drive the pixels in the display block 120 according to a sequence. In some embodiments, this sequence is "diagonal order" or "oblique order". For example, the driving order of the pixels in the display block 120 is pixel P ₁₁ , pixel P ₂₂ , pixel P ₃₃ , pixel P ₄₄ , pixel P ₅₅ , pixel P ₁₂ , pixel P ₂₃ , pixel P ₃₄ , pixel P ₄₅ , Pixel P ₁₃ , pixel P ₂₄ , pixel P ₃₅ , pixel P ₁₄ , pixel P ₂₅ , pixel P ₁₅ , pixel P ₂₁ , pixel P ₃₂ , pixel P ₄₃ , pixel P ₅₄ , pixel P ₃₁ , pixel P ₄₂ , pixel P ₅₃ , pixel P ₄₁ , pixel P ₅₂ , and pixel P ₅₁ .

Explained another way, the gate driving circuits 140X and 140Y first drive the pixels on the diagonal (eg, P ₁₁ , pixel P ₂₂ , pixel P ₃₃ , pixel P ₄₄ , pixel P ₅₅ ). Next, the gate driving circuits 140X and 140Y drive the pixels (for example: pixel P ₁₂ , pixel P ₂₃ , pixel P ₃₄ , pixel P ₄₅ , pixel P ₁₃ , pixel P ₂₄ , pixel P ₃₅₎ located at the upper right of the display block 120. (Pixel P ₁₄ , pixel P ₂₅ , pixel P ₁₅ ). Finally, the gate driving circuits 140X and 140Y drive the pixels (eg, pixel P ₂₁ , pixel P ₃₂ , pixel P ₄₃ , pixel P ₅₄ , pixel P ₃₁ , pixel P ₄₂ , pixel P ₅₃₎ located at the lower left of the display block 120. (Pixel P ₄₁ , pixel P ₅₂ , pixel P ₅₁ ). In some embodiments, after driving the pixels on the diagonal (such as the pixels described above), the pixels located at the lower left of the display block 120 (such as the pixels described above) can be driven. The pixels at the upper right of the display block 120 (such as the pixels described above) are not limited thereto.

To explain it another way, after the gate driving circuits 140X and 140Y drive the pixels (for example, pixel P ₁₁ ) in the i-th column and the j-th row, the gate driving circuits 140X and 140Y then drive the j + in the i + 1-th column. One row of pixels (for example: pixel P ₂₂ ). i and j are positive integers between 1 and (N-1). After the gate driving circuits 140X and 140Y drive the pixel (for example, pixel P ₂₂ ) in the i + 1th column and j + 1, the gate driving circuits 140X and 140Y then drive the i + 2 column and j + 2 rows Pixels (for example: pixel P ₃₃ ), and so on.

After the gate driving circuits 140X and 140Y are driven to the pixels (for example, pixel P ₅₅ ) located in the Kth and Nth rows according to the driving sequence described above, the gate driving circuits 140X and 140Y then drive the (N- K + 2) pixels (for example, pixel P ₁₂ ). K is a positive integer between 2 and N. Next, the gate driving circuits 140X and 140Y drive pixels (for example, pixel P ₂₃ ) located in the (1 + 1) th column (N-K + 2) + 1th row, and so on.

After the gate driving circuits 140X and 140Y are driven to the pixels (for example, pixel P ₁₅ ) located in the first column and the N row according to the driving sequence described above, the gate driving circuits 140X and 140Y then drive the pixels located in the second column and the first row. Pixels (for example: pixel P ₂₁ ). Then, the gate driving device 140 drives a pixel (for example, a pixel P ₃₂ ) located in the 2 + 1th column and the 1 + 1th row, and so on.

After the gate driving circuits 140X and 140Y drive the pixels (for example, the pixel P ₅₄ ) located in the Nth column and the N-1th row according to the driving sequence described above, the gate driving device 120 then drives the third column and the first row Pixels (for example: pixel P ₃₁ ), and so on.

With the above driving sequence, the pixels in the display block 120 will be driven in a “diagonal order” or a “slant order”.

For easy understanding, the driving of these pixels is divided into the X direction and the Y direction as described later. The X direction refers to how the gate driving circuit 140X drives the pixels through the row address lines X1 to X5 in a “diagonal order”. The Y direction refers to how the gate driving circuit 140Y drives the pixels through the column address lines Y1 to Y5 in a "diagonal order".

The following will first describe the X direction.

Please refer to Figures 3A to 3D. 3A to 3D are circuit diagrams of driving circuits of different stages in the gate driving circuit 140X of FIG. 1 according to an embodiment of the disclosure.

In some embodiments, the gate driving circuit 140X includes N-level driving circuits, and N is a positive integer greater than or equal to 3. For example, when N is equal to 3, the gate driving circuit 140X includes a driving circuit 302 (a first-level driving circuit), a driving circuit 306 (a second-level driving circuit), and a driving circuit 308 (a third-level driving circuit).

In some embodiments, the gate driving circuit 140X includes N-level driving circuits, and N is a positive integer greater than or equal to 4. For example, when N is equal to 4, the gate driving circuit 140X includes a driving circuit 302 (a first-level driving circuit), a driving circuit 304 (a second-level driving circuit), a driving circuit 306 (a third-level driving circuit), and a driving circuit. Circuit 308 (4th stage driving circuit). As another example, when N is equal to 5, the gate driving circuit 140X includes a driving circuit 302 (a first-level driving circuit), two driving circuits 304 (a second-level driving circuit and a third-level driving circuit), and a driving circuit 306 (Level 4 drive circuit) and drive circuit 308 (level 5 driving circuit). In other words, the drive circuit 302 is used to implement the first-stage drive circuit, the drive circuit 304 is used to implement the second-to-last-third-stage drive circuit, the drive circuit 306 is used to implement the second-to-last drive circuit, and the drive circuit 308 is used to implement The last stage drive circuit.

In some embodiments, the driving circuits of different stages are respectively used to output displacement signals to drive the corresponding row address lines. For example, the first-stage driving circuit is used to output the displacement signal G _X (1) to drive the row address line X1. The second-stage driving circuit is used to output the displacement signal G _X (2) to drive the row address line X2. The third-stage driving circuit is used to output the displacement signal G _X (3) to drive the row address line X3. The fourth-stage driving circuit is used to output the displacement signal G _X (4) to drive the row address line X4. The fifth stage driving circuit is used to output the displacement signal G _X (5) to drive the row address line X5.

Please refer to Figure 4. FIG. 4 is a timing chart of a driving period in the upper right direction in the X direction. The control signal ST1_i, the control signal ST2_i, the drive signal ST1, the drive signal ST2, and the displacement signals G _X (1) to G _X (5), the clock signal CK, and the clock signal XCK are shown in FIG. The phase clock signal XCK is called) timing diagram. Please refer to FIGS. 3A to 3D and FIG. 4 together.

In some embodiments, the driving circuit 302 in FIG. 3A is a first-level driving circuit in an N-level driving circuit. The driving circuit 302 is configured to output a displacement signal G _X (1) according to the driving signal ST1 and the driving signal ST2 to drive the row address line X1.

As shown in FIG. 3A, the driving circuit 302 includes a sixth switching unit M6, a seventh switching unit M7, an eighth switching unit M8, a first switching unit M1, a pull-down circuit 3020, and a capacitor C1. The sixth switching unit M6 has an input terminal and an output terminal. The seventh switching unit M7 has an input terminal and an output terminal. The eighth switching unit M8 has an input terminal and an output terminal. An input terminal of the sixth switching unit M6 is used to receive the level voltage V1. In some embodiments, the level voltage V1 has a high level. The sixth switching unit M6 is turned on according to the driving signal ST1. For example, the control terminal of the sixth switching unit M6 receives the driving signal ST1, so that the sixth switching unit M6 is turned on. An output terminal of the sixth switching unit M6 is electrically coupled to an input terminal of the seventh switching unit M7. The seventh switching unit M7 is turned on according to the driving signal ST2. For example, the control terminal of the seventh switching unit M7 receives the driving signal ST2, so that the seventh switching unit M7 is turned on. An output terminal of the seventh switching unit M7 and an output terminal of the eighth switching unit M8 are electrically coupled to the node Q. An input terminal of the eighth switching unit M8 is used to receive the level voltage V2. In some embodiments, the level voltage V2 has a low level. In some embodiments, the level voltage V2 is opposite to the level voltage V1. The eighth switching unit M8 is turned on according to the displacement signal G _X (2). For example, the control terminal of the eighth switching unit M8 receives the displacement signal G _X (2), so that the eighth switching unit M8 is turned on. The first switching unit M1 has an input terminal and an output terminal. An input terminal of the first switching unit M1 is used to receive a clock signal CK. The first switching unit M1 is turned on according to the voltage at the node Q. For example, the control terminal of the first switching unit M1 receives the voltage of the node Q, so that the first switching unit M1 is turned on. An output terminal of the first switching unit M1 is used to output a displacement signal G _X (1).

In some embodiments, the pull-down circuit 3020 includes a capacitor C2, a switching unit SW1, a switching unit SW2, a switching unit SW3, and a switching unit SW4. The first terminal of the capacitor C2 is used to receive the clock signal CK. Switching unit The first terminal of SW1 is coupled to the second terminal of the capacitor C2. The control terminal of the switching unit SW1 is coupled to the node Q. The second terminal of the switching unit SW1 is used to receive the voltage VGL. The first terminal of the switching unit SW2 is coupled to the node Q. The control terminal of the switching unit SW2 is coupled to the first terminal of the switching unit SW1. The second terminal of the switching unit SW2 is used to receive the voltage VGL. A first terminal of the switching unit SW3 is coupled to an output terminal of the first switching unit M1. The control terminal of the switching unit SW3 is coupled to the first terminal of the switching unit SW1. The second terminal of the switching unit SW3 is used to receive the voltage VGL. A first terminal of the switching unit SW4 is coupled to an output terminal of the first switching unit M1. The control terminal of the switch unit SW4 is used to receive the clock signal XCK. The second terminal of the switching unit SW4 is used to receive the voltage VGL.

In some embodiments, the driving circuit 302 further includes a ninth switching unit M9 and a tenth switching unit M10. The input terminal of the ninth switch unit M9 is used to receive the level voltage V1, and the output terminal of the ninth switch unit M9 is electrically coupled to the output terminal of the tenth switch unit M10 and the control terminal of the first switch unit M1. An input terminal of the tenth switching unit M10 is used to receive a signal ST2_y. The ninth switch unit M9 is used to control the signal ST1_i. For example, the control terminal of the ninth switch unit M9 is used to receive the control signal ST1_i and transmit the level voltage V1 to the control terminal of the first switch unit M1 (ie, node Q). . The tenth switching unit M10 is used to control the signal ST2_i. For example, the control terminal of the tenth switching unit M10 is used to receive the control signal ST2_i and transmit the signal ST2_y to the control terminal of the first switching unit M1.

Since the control signals ST1_i and ST2_i have low levels, the ninth switching unit M9 and the tenth switching unit M10 are turned off. In this way, the level voltage V1 and the signal ST2_y cannot pass through the ninth switch sheet, respectively. The element M9 and the tenth switching unit M10 are transmitted to the node Q.

At time T1, the driving signal ST1 has a high level. The sixth switching unit M6 is turned on according to the driving signal ST1 to transmit the level voltage V1 to the output terminal of the sixth switching unit M6. At time T1, the driving signal ST2 also has a high level. The seventh switching unit M7 is turned on according to the driving signal ST2 to transmit the level voltage V1 to the node Q. The capacitor C1 stores the level voltage V1 at the node Q. The first switching unit M1 is turned on according to the voltage at the node Q. The clock signal CK is transmitted to the output terminal of the first switching unit M1 through the first switching unit M1 to generate a displacement signal G _X (1). Since the clock signal CK has a high level at time T2, the displacement signal G _X (1) has a high level at time T2. As such, the row address line X1 will be driven.

Since the voltage at the node Q has a high level at time T2, the switching unit SW1 is turned on at time T2. The voltage VGL is transmitted to the control terminal of the switch unit SW2 and the control terminal of the switch unit SW3 through the switch unit SW1. In some embodiments, the voltage VGL has a low level. The switching unit SW2 and the switching unit SW3 are turned off according to the voltage VGL. In this case, the voltage at the node Q and the displacement signal G _X (1) are maintained at a high level.

At time T3, the displacement signal G _X (2) has a high level, so the eighth switching unit M8 is turned on. The level voltage V2 is transmitted to the node Q through the eighth switching unit M8. Since the level voltage V2 has a low level, the first switching unit M1 is turned off. Since the inverted clock signal XCK has a high level at time T3, the switching unit SW4 is turned on. The displacement signal G _X (1) is pulled down to the voltage VGL through the switch unit SW4. Therefore, the displacement signal G _X (1) has a low level at time T3.

In some embodiments, the driving circuit 304 in FIG. 3B is the M-th driving circuit in the N-level driving circuit, and M is a positive integer between 2 and (N-2). If the driving circuit 304 is a second-stage driving circuit, the driving circuit 304 outputs a displacement signal G _X (2) to drive the row address line X2. If the driving circuit 304 is a third-level driving circuit, the driving circuit 304 outputs a displacement signal G _X (3) to drive the row address line X3. And so on.

In some embodiments, the drive circuit 304 drives the displacement signal output circuit G _X based on a previous (M-1) outputs a displacement signal G _X (M). The driving circuit 304 further stops outputting the displacement signal G _X (M) based on the displacement signal G _X (M + 1) output by the next-stage driving circuit.

As shown in FIG. 3B, the driving circuit 304 includes a thirteenth switching unit M13, a fourteenth switching unit M14, a fifteenth switching unit M15, a sixteenth switching unit M16, a first switching unit M1, a pull-down circuit 3040, and a capacitor C1. In some embodiments, the driving circuit 304 is a second-stage driving circuit. The thirteenth switching unit M13 has an input terminal and an output terminal. The fourteenth switching unit M14 has an input terminal and an output terminal. The input terminal of the thirteenth switching unit M13 is used to receive the level voltage V1. An input terminal of the fourteenth switching unit M14 is used to receive the level voltage V2. An output terminal of the fourteenth switching unit M14 and an output terminal of the thirteenth switching unit M13 are electrically coupled to the node Q. The thirteenth switching unit M13 is used to transmit the level voltage V1 to the node Q according to the displacement signal G _X (M-1). The fourteenth switching unit M14 is used for transmitting the level voltage V2 to the node Q according to the displacement signal G _X (M + 1).

In some embodiments, the pull-down circuit 3040 includes a capacitor C2, The switching unit SW1, the switching unit SW2, the switching unit SW3, and the switching unit SW4. The first terminal of the capacitor C2 is used to receive a clock signal CK or an inverted clock signal XCK. A first terminal of the switching unit SW1 is coupled to a second terminal of the capacitor C2. The control terminal of the switching unit SW1 is coupled to the node Q. The second terminal of the switching unit SW1 is used to receive the voltage VGL. The first terminal of the switching unit SW2 is coupled to the node Q. The control terminal of the switching unit SW2 is coupled to the first terminal of the switching unit SW1. The second terminal of the switching unit SW2 is used to receive the voltage VGL. A first terminal of the switching unit SW3 is coupled to an output terminal of the first switching unit M1. The control terminal of the switching unit SW3 is coupled to the first terminal of the switching unit SW1. The second terminal of the switching unit SW3 is used to receive the voltage VGL. A first terminal of the switching unit SW4 is coupled to an output terminal of the first switching unit M1. The control terminal of the switch unit SW4 is used to receive the clock signal CK or the inverted clock signal XCK. The second terminal of the switching unit SW4 is used to receive the voltage VGL.

In some embodiments, the driving circuit 304 further includes a seventeenth switching unit M17. The seventeenth switching unit M17 is used to transmit the level voltage V2 to the control terminal of the first switching unit M1 according to the control signal ST2_i. Since the control signal ST2_i has a low level, the seventeenth switching unit M17 is turned off.

At time T2, taking the second-stage driving circuit as an example, the displacement signal G _X (1) has a high level, so the thirteenth switching unit M13 is turned on. The level voltage V1 is transmitted to the node Q through the thirteenth switching unit M13. The first switching unit M1 is turned on according to the voltage at the node Q. Then, the inverted clock signal XCK will be transmitted to the output terminal of the first switching unit M1 through the first switching unit M1 to generate a displacement signal G _X (2). Since the inverted clock signal XCK has a high level at time T3, the displacement signal G _X (2) has a high level at time T3. As such, the row address line X2 will be driven.

At time T4, since the displacement signal G _X (3) has a high level, the fourteenth switching unit M14 is turned on. The level voltage V2 is transmitted to the node Q through the fourteenth switching unit M14. Since the level voltage V2 has a low level, the first switching unit M1 is turned off. The clock signal CK has a high level at time T4, so the switching unit SW4 is turned on. The displacement signal G _X (2) is pulled down to the voltage VGL through the switch unit SW4. Therefore, the displacement signal G _X (2) has a low level at time T4.

In some embodiments, if the driving circuit 304 is a second-stage driving circuit, the first switching unit M1 is used to receive the inverted clock signal XCK, the switching unit SW4 is controlled by the clock signal CK, and the capacitor C2 is used to receive the inverted clock signal. Pulse signal XCK. If the driving circuit 304 is a third-level driving circuit, the first switch unit M1 is used to receive the clock signal CK, the switch unit SW4 is controlled by the inverted clock signal XCK, and the capacitor C2 is used to receive the clock signal CK.

Explained another way, in the driving circuit of the even stage, the first switch unit M1 is used to receive the inverted clock signal XCK, the switch unit SW4 is controlled by the clock signal CK, and the capacitor C2 is used to receive the inverted clock signal XCK. In the odd-numbered-stage driving circuit, the first switch unit M1 is used to receive the clock signal CK, the switch unit SW4 is controlled by the inverted clock signal XCK, and the capacitor C2 is used to receive the clock signal CK.

Explaining it another way, the inverted clock signal XCK and the clock signal CK are interchanged in the driving circuits of adjacent stages.

In some embodiments, the driving circuit 304 receives the driving signal ST1 according to the displacement signal G _X (M) and the displacement signal G _X (N), and selectively outputs the displacement signal G _X (M) again according to the potential of the driving signal ST1.

As shown in FIG. 3B, the fifteenth switching unit M15 has an input terminal and an output terminal. The sixteenth switching unit M16 has an input terminal and an output terminal. An input terminal of the fifteenth switching unit M15 is used to receive the driving signal ST1. The output terminal of the fifteenth switching unit M15 and the input terminal of the sixteenth switching unit M16 are electrically coupled to the node N1. The fifteenth switching unit M15 is used to transmit the driving signal ST1 to the node N1 according to the displacement signal G _X (M). The output terminal of the sixteenth switching unit M16 is electrically coupled to the node Q. The sixteenth switching unit M16 is turned on according to the displacement signal G _X (N) to transmit the driving signal ST1 to the node Q.

For example, when the driving circuit 304 is a second-stage driving circuit, when the displacement signal G _X (2) has a high level (for example, time T3), the driving signal ST1 having the high level is transmitted to the node N1. When the displacement signal G _X (5) of the last stage has a high level (for example, time T6), the driving signal ST1 located at the node N1 is transmitted to the node Q. The first switching unit M1 is turned on according to the high level of the driving signal ST1 transmitted to the node Q. The inverted clock signal XCK is transmitted to the output terminal of the first switching unit M1 through the first switching unit M1. Since the inverted clock signal XCK has a high level at time T7, the displacement signal G _X (2) has a high level at time T7. In other words, the displacement signal G _X (2) having a high level is output again.

If the driving circuit 304 is a third-stage driving circuit, since the clock signal CK has a high level at time T8, the displacement signal G _X (3) has a high level at time T8. Since the driving circuit 304 is a third-level driving circuit, the driving circuit 304 has operations similar to those described above, and thus will not be repeated here.

In some embodiments, the driving circuit 306 in FIG. 3C is the (N-1) th driving circuit in the N-level driving circuit. Explained another way, the driving circuit 306 is the penultimate driving circuit. Since N is equal to 5 in the embodiment of FIG. 1, the driving circuit 306 is a fourth-stage driving circuit. The driving circuit 306 is used for outputting the displacement signal G _X (4) to drive the row address line X4.

As shown in FIG. 3C, the driving circuit 306 includes a second switching unit M2, a third switching unit M3, a fourth switching unit M4, a first switching unit M1, a pull-down circuit 3060, and a capacitor C1. The third switching unit M3 has an input terminal and an output terminal. The fourth switching unit M4 has an input terminal and an output terminal. An input terminal of the second switching unit M2 is used to receive the level voltage V1. The second switching unit M2 is used to transmit the level voltage V1 to the node Q according to the displacement signal G _X (N-2). The output terminal of the third switching unit M3 is electrically coupled to the output terminal of the second switching unit M2 at the node Q. An input terminal of the third switching unit M3 is electrically coupled to an output terminal of the fourth switching unit M4. An input terminal of the fourth switching unit M4 is used to receive the level voltage V2. The fourth switching unit M4 is used to transmit the level voltage V2 to the input terminal of the third switching unit M3 according to the driving signal ST1. The third switching unit M3 is turned on according to the displacement signal G _X (N) to transmit the level voltage V2 to the node Q. The first switching unit M1 is turned on or off according to the voltage at the node Q.

In some embodiments, the pull-down circuit 3060 includes a capacitor C2, a switching unit SW1, a switching unit SW2, a switching unit SW3, and a switching unit SW4. The first terminal of the capacitor C2 is used to receive a clock signal CK or an inverted clock signal XCK. A first terminal of the switching unit SW1 is coupled to a second terminal of the capacitor C2. The control terminal of the switching unit SW1 is coupled to the node Q. The second terminal of the switching unit SW1 is used to receive the voltage VGL. The first terminal of the switching unit SW2 is coupled to the node Q. The control terminal of the switching unit SW2 is coupled to the first terminal of the switching unit SW1. The second terminal of the switching unit SW2 is used to receive the voltage VGL. A first terminal of the switching unit SW3 is coupled to an output terminal of the first switching unit M1. The control terminal of the switching unit SW3 is coupled to the first terminal of the switching unit SW1. The second terminal of the switching unit SW3 is used to receive the voltage VGL. A first terminal of the switching unit SW4 is coupled to an output terminal of the first switching unit M1. The control terminal of the switch unit SW4 is used to receive the clock signal CK or the inverted clock signal XCK. The second terminal of the switching unit SW4 is used to receive the voltage VGL.

In some embodiments, the driving circuit 306 further includes a fifth switching unit M5. The fifth switching unit M5 is used to transmit the level voltage V2 to the control terminal of the first switching unit M1 according to the control signal ST2_i. Since the control signal ST2_i has a low level, the fifth switching unit M5 is turned off.

At time T4, taking the fourth stage driving circuit as an example (N = 5), the displacement signal G _X (3) has a high level, so the second switching unit M2 is turned on. The level voltage V1 is transmitted to the node Q through the second switching unit M2. The first switching unit M1 is turned on according to the voltage at the node Q. The inverted clock signal XCK is transmitted to the output terminal of the first switching unit M1 through the first switching unit M1 to generate a displacement signal G _X (4). Since the inverted clock signal XCK has a high level at time T5, the displacement signal G _X (4) has a high level at time T5. As such, the row address line X4 will be driven.

At time T6, the driving signal ST1 and the displacement signal G _X (5) have a high level. The fourth switching unit M4 is turned on according to the driving signal ST1 and the third switching unit M3 is turned on according to the displacement signal G _X (5) to transmit the level voltage V2 to the node Q. Since the level voltage V2 has a low level, the first switching unit M1 is turned off. The clock signal CK has a high level at time T6, so the switching unit SW4 is turned on. The displacement signal G _X (4) is pulled down to the voltage VGL through the switch unit SW4. Therefore, the displacement signal G _X (4) has a low level at time T6.

In some embodiments, after the driving circuit 306 outputs the displacement signal G _X (N-1) according to the displacement signal G _X (N-2), the driving circuit 306 selects according to the potential of the driving signal ST1 and the displacement signal G _X (N). The output signal G _X (N-1) is output again.

For example, the driving circuit 306 outputs a high-level displacement signal G _X (4) at time T5. At time T6, since the driving signal ST1 and the displacement signal G _X (5) have a high level, the third switching unit M3 and the fourth switching unit M4 are turned on. The level voltage V2 is transmitted to the node Q through the third switching unit M3 and the fourth switching unit M4. The first switching unit M1 is turned off according to the potential at the node Q. The displacement signal G _X (4) is pulled down to the voltage VGL through the switch unit SW4. Since the displacement signal G _X (3), the displacement signal G _X (5), and the driving signal ST1 have low levels at time T7, the displacement signal G _X (4) is still pulled down to the voltage VGL by the pull-down circuit 3060 at time T7. That is, the driving circuit 306 stops outputting the displacement signal G _X (4) having a high level.

At time T9, since the driving signal ST1 has a low level, the fourth switching unit M4 is turned off. The first switching unit M1 is turned on according to the voltage at the node Q. The inverted clock signal XCK is transmitted to the output terminal of the first switching unit M1 through the first switching unit M1. Since the inverted clock signal XCK has a high level at time T10, the displacement signal G _X (4) has a high level at time T10.

In some embodiments, the driving circuit 308 in the 3D diagram is an N-th driving circuit in an N-level driving circuit. Explained another way, the driving circuit 308 is the last-stage driving circuit. Since N is equal to 5 in the embodiment of FIG. 1, the driving circuit 308 is a fifth-stage driving circuit. The driving circuit 308 is configured to output a displacement signal G _X (5) to drive the row address line X5.

As shown in FIG. 3D, the driving circuit 308 includes an eleventh switching unit M11, a twelfth switching unit M12, a first switching unit M1, a pull-down circuit 3080, and a capacitor C1. The eleventh switching unit M11 is used to transmit the level voltage V1 to the node Q according to the displacement signal G _X (N-1). The twelfth switching unit M12 is configured to transmit the level voltage V2 to the node Q according to the driving signal ST2.

In some embodiments, the pull-down circuit 3080 includes a capacitor C2, a switching unit SW1, a switching unit SW2, a switching unit SW3, and a switching unit SW4. The first terminal of the capacitor C2 is used to receive a clock signal CK or an inverted clock signal XCK. A first terminal of the switching unit SW1 is coupled to a second terminal of the capacitor C2. The control terminal of the switching unit SW1 is coupled to the node Q. The second terminal of the switching unit SW1 is used to receive the voltage VGL. The first terminal of the switching unit SW2 is coupled to the node Q. The control terminal of the switching unit SW2 is coupled to the first terminal of the switching unit SW1. The second terminal of the switching unit SW2 is used to receive the voltage VGL. A first terminal of the switching unit SW3 is coupled to an output terminal of the first switching unit M1. The control terminal of the switching unit SW3 is coupled to the first terminal of the switching unit SW1. The second terminal of the switching unit SW3 is used to receive the voltage VGL. A first terminal of the switching unit SW4 is coupled to an output terminal of the first switching unit M1. The control terminal of the switch unit SW4 is used to receive the clock signal CK or the inverted clock signal XCK. The second end of the switch unit SW4 is used for receiving Voltage VGL.

In some embodiments, after the driving circuit 308 outputs the displacement signal G _X (5), the driving circuit 308 stops outputting the displacement signal G _X (5) according to the driving signal ST2.

At time T5, the displacement signal G _X (4) has a high level, so the eleventh switching unit M11 is turned on. The level voltage V1 is transmitted to the node Q through the eleventh switching unit M11. The first switching unit M1 is turned on according to the voltage at the node Q. The clock signal CK is transmitted to the output terminal of the first switching unit M1 through the first switching unit M1 to generate a displacement signal G _X (5). Since the clock signal CK has a high level at time T6, the displacement signal G _X (5) has a high level at time T6. As such, the row address line X5 will be driven.

In addition, at time T7, the driving signal ST2 has a high level, so the twelfth switching unit M12 is turned on. The level voltage V2 is transmitted to the node Q through the twelfth switching unit M12. Since the level voltage V2 has a low level, the first switching unit M1 is turned off. The displacement signal G _X (5) is pulled down to the voltage VGL through the switch unit SW4. Therefore, the displacement signal G _X (5) has a low level at time T7. In other words, the displacement signal G _X (5) having a high level stops outputting at time T7.

With a similar operation, the row address line X2 is driven at time T7. Next, the row address line X3, the row address line X4, the row address line X5, the row address line X4, the row address line X5, and the row address line X5 will be sequentially driven. In this way, the driving in the X direction to the upper right can be completed.

Please refer to Figure 5. FIG. 5 is a timing chart of the driving period in the X direction in the lower left. The following only describes the more specific points in time, the rest The operation is similar to the aforementioned circuit operation.

At time T11, the control signal ST1_i has a high level. Therefore, the ninth switching unit M9 in FIG. 3A is turned on. The level voltage V1 turns on the first switching unit M1 through the ninth switching unit M9, so that the displacement signal G _X (1) has a high level at time T12 based on the clock signal CK.

At time T13, the control signal ST2_i has a high level. Therefore, the switch SW4 in FIG. 3C is turned on. The level voltage V2 turns off the first switching unit M1 through the fifth switching unit M5. Therefore, the displacement signal G _X (4) has a low level at time T13.

Please refer to Figures 6A to 6D. 6A to 6D are circuit diagrams of driving circuits of different stages in the gate driving circuit 140Y of FIG. 1 according to an embodiment of the disclosure.

In some embodiments, the gate driving circuit 140Y includes N-level driving circuits, and N is a positive integer greater than or equal to 3. For example, when N is equal to 3, the gate driving circuit 140Y includes a driving circuit 602, a driving circuit 606, and a driving circuit 608. In some embodiments, the gate driving circuit 140Y includes N-level driving circuits, and N is a positive integer greater than or equal to 4. For example, when N is equal to 4, the gate driving circuit 140Y includes a driving circuit 602, a driving circuit 604, a driving circuit 606, and a driving circuit 608.

In some embodiments, the driving circuits of different stages are respectively used to output displacement signals to drive corresponding column address lines. For example, the first-stage driving circuit is used to output the displacement signal G _Y (1) to drive the column address line Y1. The second-stage driving circuit is used for outputting the displacement signal G _Y (2) to drive the column address line Y2. The third-stage driving circuit is used to output the displacement signal G _Y (3) to drive the column address line Y3. The fourth stage driving circuit is used to output the displacement signal G _Y (4) to drive the column address line Y4. The fifth stage driving circuit is used to output the displacement signal G _Y (5) to drive the column address line Y5.

In some embodiments, the architecture of the driving circuit 602 in FIG. 6A is similar to the architecture of the driving circuit 302 in FIG. 3A, and both have similar operations. The architecture of the driving circuit 604 in FIG. 6B is similar to the architecture of the driving circuit 304 in FIG. 3B, and both have similar operations. The architecture of the driving circuit 606 of FIG. 6C is similar to that of the driving circuit 606 of FIG. 3C, and both have similar operations. The architecture of the driving circuit 608 in FIG. 6D is similar to the architecture of the driving circuit 308 in FIG. 3D, and both have similar operations.

For ease of understanding, similar elements will be assigned the same reference numerals. The following only describes the differences, and the rest is similar to the content of the foregoing embodiment. The ninth switching unit M9 in FIG. 6A is controlled by a control signal ST1_j, and the tenth switching unit M10 is controlled by a control signal ST2_j. The seventeenth switching unit M17 of FIG. 6B is controlled by a control signal ST2_j. The fifth switching unit M5 in FIG. 6C is controlled by a control signal ST2_j.

Please refer to Figure 7. FIG. 7 is a timing chart of a driving period in the Y direction in the lower left. In some embodiments, the driving in the Y direction on the lower left of the display block 120 in FIG. 2 is similar to the driving in the X direction on the upper right, so FIG. 7 is similar to FIG. 4. Please refer to Figure 8. FIG. 8 is a timing chart of the Y-direction driving period at the upper right. In some embodiments, the driving in the Y direction at the upper right of the display block 120 in FIG. 2 is similar to the driving in the X direction at the lower left, so FIG. 8 is similar to FIG. 5.

With the above configuration, the address frequency of the display panel 100 in the X direction The rate is the same as the addressing frequency in the Y direction. In this case, it is possible to avoid adding a stabilizing capacitor.

In summary, the display panel drives the pixels in the display block in a specific order, so that the addressing frequency in the X direction is the same as the addressing frequency in the Y direction. In this way, it is possible to avoid adding an additional voltage stabilizing capacitor to the display panel. Although this disclosure has been disclosed as above in the form of implementation, it is not intended to limit this disclosure. Any person with ordinary knowledge in the field can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure The scope of protection shall be determined by the scope of the attached patent application.

Claims (18)

A display panel includes: at least one display block including N × N pixels to form a matrix of N columns and N rows, where N is a positive integer greater than or equal to 3; and a gate driver A device for driving each of the N × N pixels according to a sequential order; wherein when the gate driving device drives a first pixel of the pixels located in the Kth column and the Nth row of the matrix, the next The gate driving device drives a second pixel of the pixels located in the first column and the (N-K + 2) row of the matrix, where K is a positive integer between 2 and N. The display panel according to claim 1, wherein the gate driving device comprises: a first gate driving circuit, which is electrically coupled to a plurality of row address lines connected to the pixels, and is used for driving the row address lines. And a second gate driving circuit electrically coupled to a plurality of column address lines connected to the pixels and used to drive the column address lines; wherein when the gate driving device drives the first pixel, the first A gate driving circuit sends a first displacement signal to an address line in one of the Nth rows, and the second gate driving circuit sends a second displacement signal to an address line in one of the Kth columns. The display panel according to claim 1, wherein after the gate driving device drives a third pixel in the pixels located in the i-th column and the j-th row of the matrix, the gate driving device then drives the pixels located in the pixels A fourth pixel in the i + 1th column and the j + 1th row in the matrix, i is a positive integer between 1 and (N-1), and j is a positive integer between 1 and (N-1). The display panel according to claim 1, wherein when the fifth pixel of the pixels located in the first column and the Nth row of the matrix is driven, the gate driving device then drives the pixels located in the matrix. A sixth pixel in the second column and the first row. The display panel according to claim 1, further comprising: a wireless data module for wirelessly receiving a plurality of data signals to the pixels. The display panel according to claim 1, wherein the display panel includes a plurality of the display blocks. A display panel includes: at least one display block; and a first gate driving circuit for driving N row address lines of the at least one display block, where N is a positive integer greater than or equal to 4, and the first The gate driving circuit includes: N-level driving circuits, each for outputting a displacement signal to drive a corresponding one of the row address lines, wherein when a (N-1) -th level driving circuit in the N-level driving circuit is based on After the displacement signal output by the previous stage driving circuit is used to output the displacement signal of the (N-1) th stage driving circuit, the (N-1) th stage driving circuit is based on the potential of a first driving signal and the Nth stage driving The displacement signal output by an N-th stage driving circuit in the circuit selectively outputs the displacement signal again. The display panel according to claim 7, wherein a first-level driving circuit in the N-level driving circuit drives and outputs the displacement signal of the first-level driving circuit according to the first driving signal and a second driving signal. The display panel according to claim 7, wherein after the N-th driving circuit outputs the displacement signal, the N-th driving circuit stops outputting the displacement signal of the N-th driving circuit according to a second driving signal. The display panel according to claim 7, wherein an M-level driving circuit in the N-level driving circuit outputs the displacement signal of the M-level driving circuit according to the displacement signal output by the previous-level driving circuit, and drives according to the next level The displacement signal output by the circuit stops outputting the displacement signal of the M-th level driving circuit, and the M-th level driving circuit is further based on the displacement signal output by the M-th level driving circuit and the displacement signal of the N-th level driving circuit. To receive the first driving signal and selectively output the displacement signal of the M-th driving circuit again according to the potential of the received first driving signal, where M is between 2 and (N-2) Positive integer. The display panel according to claim 7, further comprising: a second gate driving circuit for driving N column address lines of the at least one display block, wherein the column address lines are perpendicular to the row address lines N × N nodes are staggered, and each node is provided with a pixel to form a matrix of N columns and N rows. The second gate driving circuit includes: N-level driving circuits, each for outputting a displacement signal to drive A corresponding one of the column addressing lines, wherein after the pixel in the first column and the Nth row in the matrix is driven, according to the displacement signal output by the Nth stage driving circuit in the first gate driving circuit, A second-stage driving circuit of the N-stage driving circuit of the second gate-driving circuit outputs the displacement signal of the second-stage driving circuit of the second-gate driving circuit to drive a second column of the matrix. Addressing line. A gate driving device for driving N addressing lines of a display panel, where N is a positive integer greater than or equal to 4, the gate driving device includes: N-level driving circuits, each of which includes a node and a first switch Unit, the first switch unit transmits a clock signal to an output terminal of the first switch unit as a displacement signal to drive a corresponding one of the N addressing lines according to the potential of the node, wherein the N-level drive A (N-1) -level driving circuit in the circuit includes: a second switching unit for converting a first standard according to the displacement signal output from a (N-2) -level driving circuit in the N-level driving circuit; A bit voltage is transmitted to the node of the (N-1) th stage driving circuit; a third switching unit having an input end and an output end and according to the displacement output by an Nth level driving circuit in the Nth level driving circuit The signal is turned on, wherein the output terminal of the third switching unit is connected to the node of the (N-1) th driving circuit; and a fourth switching unit is used to set a second level according to a first driving signal. The voltage is transmitted to the output of the third switching unit. End, wherein the second voltage level to the first level voltage inverter, the first switching unit according to the first level voltage according to the ON and OFF the second voltage level. The gate driving device according to claim 12, wherein the (N-1) -stage driving circuit further includes a fifth switching unit for transmitting the second level voltage to a second control signal according to a second control signal. A control terminal of the first switch unit. The gate driving device according to claim 12, wherein a first-level driving circuit in the N-level driving circuit includes a sixth switching unit for transmitting the first level voltage according to the first driving signal. To an output terminal of the sixth switch unit; a seventh switch unit having an input terminal and an output terminal and conducting according to a second driving signal, wherein the input terminal of the seventh switch unit is connected to the sixth switch unit The output end of the seventh switching unit is connected to the node of the first-level driving circuit; and an eighth switching unit is configured to output the second-level driving circuit in the N-level driving circuit according to the output of the second-level driving circuit. The displacement signal is used to transmit the second level voltage to the node of the first-stage driving circuit. The gate driving device according to claim 14, wherein the first-stage driving circuit further includes a ninth switching unit for transmitting the first level voltage to the first switch according to a first control signal. A control end of the unit; and a tenth switch unit, configured to transmit a first signal to the control end of the first switch unit according to a second control signal. The gate driving device according to claim 12, wherein the N-th driving circuit in the N-level driving circuit includes: an eleventh switching unit for responding to the displacement output by the (N-1) -level driving circuit A signal to transmit the first level voltage to the node of the N-th level driving circuit; and a twelfth switching unit for transmitting the second level voltage to the Nth level according to the second driving signal This node drives the stage. The gate driving device according to claim 12, wherein an M-level driving circuit in the N-level driving circuit includes: a thirteenth switching unit, according to an (M-1) th in the N-level driving circuit; The displacement signal output from the stage driving circuit is used to transmit the first level voltage to the node of the M-th driving circuit; a fourteenth switching unit is used according to a (M + 1) The displacement signal output by the driving circuit of level) is used to transmit the second level voltage to the node of the driving circuit of level M; and a fifteenth switching unit is used according to the displacement signal output from the driving circuit of level M. To transmit the first driving signal to an output terminal of the fifteenth switching unit; and a sixteenth switching unit having an input terminal and an output terminal and to be turned on according to the displacement signal output by the N-th stage driving circuit , Wherein the input terminal of the sixteenth switching unit is connected to the output terminal of the fifteenth switching unit, and the output terminal of the sixteenth switching unit is connected to the node of the M-th level driving circuit, where M is between A positive integer between 2 and (N-2). The gate driving device according to claim 17, wherein the M-th level driving circuit further includes: a seventeenth switching unit for transmitting the second level voltage to the first level according to a second control signal A control terminal of the switching unit.