CN112673643A - Image quality circuit, image processing apparatus, and signal feature detection method - Google Patents
Image quality circuit, image processing apparatus, and signal feature detection method Download PDFInfo
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- CN112673643A CN112673643A CN202080004669.1A CN202080004669A CN112673643A CN 112673643 A CN112673643 A CN 112673643A CN 202080004669 A CN202080004669 A CN 202080004669A CN 112673643 A CN112673643 A CN 112673643A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/391—Resolution modifying circuits, e.g. variable screen formats
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/426—Internal components of the client ; Characteristics thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/431—Generation of visual interfaces for content selection or interaction; Content or additional data rendering
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/20—Circuitry for controlling amplitude response
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/66—Transforming electric information into light information
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/20—Adaptations for transmission via a GHz frequency band, e.g. via satellite
Abstract
Provided are an image quality circuit, an image processing device, and a signal feature detection method, which can realize more precise feature detection of a signal having a large number of pixels while maintaining the circuit scale. The image quality circuit comprises: a down-conversion unit that down-converts an input first signal into a second signal having a lower resolution than the first signal; and a feature detection unit that detects a feature of a third signal, the third signal being a signal having a lower resolution than the first signal and being input by a system different from a system in which the first signal is input, the feature detection unit detecting the feature of the second signal down-converted by the down-conversion unit.
Description
The present application claims priority of japanese patent application having application number 2019 and 170854, entitled "picture quality circuit, image processing apparatus, and signal characteristic detection method" filed in 19/9/2019, the entire contents of which are incorporated herein by reference.
Technical Field
Embodiments of the present invention relate to an image quality circuit, an image processing apparatus, and a signal feature detection method.
Background
Conventionally, there is disclosed a technique of performing feature detection of an image signal and performing various kinds of processing using the feature detection result. For example, the following techniques are known: an actual Dynamic range (Dynamic range) of the content is confirmed by detecting a histogram (histogram) obtained based on the luminance levels of the pixels of the image signal and displaying the histogram.
Prior art documents
Patent document
Patent document 1: japanese laid-open patent publication No. 8-23460
Disclosure of Invention
In recent years, 4K/8K satellite broadcasting on a new frequency band (left-handed wave) has started. However, such 4K/8K satellite broadcasting has the following problems: in order to perform feature detection (e.g., detection of a histogram) of the 8K broadcast signal (7680 × 4320), a ram (random Access memory) for storing data 4 times as large as that of the 4K broadcast signal (3840 × 2160) is required.
The present invention has been made in view of the above circumstances, and an object thereof is to provide an image quality circuit, an image processing apparatus, and a signal feature detection method that can realize feature detection of a signal having a large number of pixels with higher definition while maintaining a circuit scale.
The image quality circuit of the embodiment of the application is provided with: a down-conversion unit that down-converts an input first signal into a second signal having a lower resolution than the first signal; and a feature detection unit that detects a feature of a third signal, the third signal being a signal having a lower resolution than the first signal and being input by a system different from a system in which the first signal is input, the feature detection unit detecting the feature of the second signal down-converted by the down-conversion unit.
Drawings
Fig. 1 is a block diagram showing a configuration of an image processing apparatus according to a first embodiment;
FIG. 2 is a diagram showing an example of the configuration of an image decoder and a signal processing unit;
fig. 3 is a diagram showing an example of the configuration of an image decoder and a signal processing unit according to a second embodiment.
Description of the reference numerals
11 … digital television receiver, 51 … picture quality circuit, 60 … histogram detection section, 65 … control section, 73 … down conversion section.
Detailed Description
(first embodiment)
Fig. 1 is a block diagram showing a configuration of an image processing apparatus according to a first embodiment. In the present embodiment, the description will be made by applying the digital television receiver 11 as an example of an image processing apparatus. In the present embodiment, the digital television receiver 11 is applied as an example of an image processing apparatus, but the present invention is not limited to this, and may be a set-top box, a HDD recorder, or the like.
As shown in fig. 1, the digital television receiver 11 includes an image display unit 14, a speaker 15, an operation unit 16, a light receiving unit 18, a broadcast signal input terminal 48, a broadcast signal input terminal 53, an output terminal 63, an output terminal 64, a tuner 49, a tuner 54, a PSK demodulator 50, an OFDM demodulator 55, an image decoder 70, a signal processing unit 51 as an image quality circuit, an audio processing unit 59, a graphic processing unit 58, an image processing unit 62, an OSD signal generating unit 61, a control unit 65, and the like.
The broadcast signal input terminal 48 and the broadcast signal input terminal 53 are connected to the BS/CS digital broadcast receiving antenna 47 and the terrestrial broadcast receiving antenna 52, respectively. The light receiving unit 18 receives a signal output from the remote controller 17.
The control unit 65 controls the operations of the respective units in the digital television receiver 11. The control unit 65 includes a cpu (central Processing unit)69, a rom (read Only memory)66, a ram (random Access memory)67, and a nonvolatile memory 68. The ROM66 stores control programs for execution by the CPU 69. The nonvolatile memory 68 stores various setting information and control information. The CPU69 loads a command group and data necessary for processing into the RAM67 to execute the processing.
The control unit 65 receives operation information from the operation unit 16 or operation information from the remote controller 17 received by the light receiving unit 18. The control unit 65 controls each unit reflecting the operation content.
The BS/CS digital broadcast receiving antenna 47 receives digital satellite television broadcast signals (including 4K/8K satellite broadcasts). The BS/CS digital broadcast receiving antenna 47 outputs the received digital satellite television broadcast signals (including 4K/8K satellite broadcasts) to a tuner 49 for digital satellite broadcasts via an input terminal 48. The tuner 49 selects a broadcast signal of a channel selected by the user from the broadcast signals. The tuner 49 outputs the broadcast signal after the channel selection to the PSK demodulator 50. A psk (phase Shift keying) demodulator 50 demodulates the broadcast signal whose channel is selected by the tuner 49 into a digital video signal and an audio signal. The PSK demodulator 50 outputs the demodulated digital video signal and audio signal to the video decoder 70.
The terrestrial broadcast receiving antenna 52 receives a terrestrial digital television broadcast signal. The terrestrial broadcast receiving antenna 52 outputs a terrestrial digital television broadcast signal to the tuner 54 via the input terminal 53. The tuner 54 selects a broadcast signal of a channel selected by the user from the broadcast signals. The tuner 54 outputs the broadcast signal after the channel selection to the OFDM demodulator 55. An ofdm (orthogonal Frequency Division multiplexing) demodulator 55 demodulates the broadcast signal of which the channel is selected by the tuner 54 into a digital image signal and an audio signal. The OFDM demodulator 55 outputs the demodulated digital image signal and audio signal to the image decoder 70.
The image decoder 70 decodes an image signal subjected to image coding using a moving image compression standard such as MPEG2, h.264/MPEG-4AVC, or h.265(ISO/IEC23008-2HEVC), and outputs the decoded image signal to the signal processing unit 51.
The signal processing unit 51 performs predetermined digital signal processing on the digital image signal and the audio signal decoded by the image decoder 70. The signal processing unit 51 outputs the image signal and the audio signal subjected to the predetermined digital signal processing to a graphic (graphic) processing unit 58 and an audio processing unit 59.
The graphics processing unit 58 superimposes an OSD signal such as a menu generated by the OSD (on Screen display) signal generating unit 61 on the digital image signal output from the signal processing unit 51. The graphic processing unit 58 outputs the image signal superimposed with the OSD signal to the image processing unit 62. The graphic processing unit 58 may selectively output the image signal output from the signal processing unit 51 and the OSD signal output from the OSD signal generating unit 61.
The image processing unit 62 converts the input digital image signal into an analog image signal that can be displayed on the image display unit 14. The image processing unit 62 outputs the analog image signal to the image display unit 14. The image display unit 14 displays an image based on the input analog image signal. The image processing unit 62 may also output the analog image signal to the outside via the output terminal 63.
The audio processing unit 59 converts the input digital audio signal into an analog audio signal that can be reproduced by the speaker 15. The audio processing unit 59 outputs the analog audio signal to the speaker 15. The speaker 15 plays sound based on the input analog sound signal. The audio processing unit 59 may also lead out the analog audio signal to the outside via the output terminal 64.
The signal processing unit 51 includes a histogram detection unit 60 as a feature detection unit for detecting the features of the signal. In the signal processing unit 51, a luminance signal (Y) based on, for example, the luminance level of a pixel among the image signals to be processed is input to the histogram detection unit 60. The histogram detection unit 60 generates a histogram from the luminance signal (Y). In the image processing unit 62, the image signal is displayed based on the histogram generated by the histogram detection unit 60.
Here, the image decoder 70 and the signal processing unit 51 will be described in detail.
Fig. 2 is a diagram showing an example of the configuration of the image decoder 70 and the signal processing unit 51. As shown in fig. 2, the image decoder 70 includes an 8K decoder 56 and a 4K decoder 57.
The signal processing unit 51 includes an 8K image quality circuit 71, a 4K image quality circuit 72, an 8K → 4K Down converter (Down converter)73, a 4K → 8K UP converter (UP converter)74, a change-over switch SW75, a change-over switch SW76, and a change-over switch SW 77.
The 8K image quality circuit 71 includes a first image quality circuit 711, an image quality control circuit 712, and a second image quality circuit 713, and executes various image quality processes for the 8K signal.
The 4K image quality circuit 72 includes a first image quality circuit 721, an image quality control circuit 722, a second image quality circuit 723, and a histogram detection unit 60, and executes various image quality processes performed on the 4K signal. The first image quality circuit 721 performs an operation having no influence on the feature detection of the signal. One of the feature detections of the signal is a histogram detection in the histogram detection unit 60, which indicates a luminance distribution based on the luminance level of the pixel of the signal.
Note that the feature detection of the signal is not limited to the histogram detection indicating the luminance distribution, and may be the histogram detection indicating the color distribution, or the like.
The 8K broadcast signal (7680 × 4320) as the first signal is converted into a component signal (8K signal) by the 8K decoder 56. The component signal and the 8K signal from the external input terminal (not shown) are switched by the switch SW75 and input to the 8K picture quality circuit 71 through the switch SW 77.
The 8K broadcast signal and the 8K signal from the external input terminal are switched by the switch SW75 and input to the 8K → 4K down-converter 73.
The 8K → 4K down-converter 73 down-converts the 8K broadcast signal, the 8K signal from the external input terminal, into a 4K signal (second signal), and outputs the down-converted signal to the changeover switch SW 76. The signal obtained by down-conversion means a signal obtained by converting a signal having a large number of pixels of the original signal into a signal having a small number of pixels.
On the other hand, the 4K broadcast signal (3840 × 2160) as the third signal is converted into a component signal (4K signal) by the 4K decoder 57. The component signal is switched by a switch SW76 with a 4K signal from an external input terminal (not shown) and a 4K signal from an 8K → 4K down-converter 73, and is input to the 4K picture quality circuit 72.
The 4K broadcast signal input to the 4K picture quality circuit 72 is up-converted into an 8K signal by the 4K → 8K up-converter 74 after various picture quality processes are performed by the 4K picture quality circuit 72. The 8K image signal obtained by the up-conversion is subjected to various image quality processes by the 8K image quality circuit 71 via the changeover switch SW77 and is displayed on the image display unit 14.
The 4K signal down-converted by the 8K → 4K down-converter 73 is switched by the switch SW76 and is input to the 4K picture quality circuit 72. The down-converted 4K signal input to the 4K image quality circuit 72 is subjected to histogram detection by the histogram detection unit 60 after passing through the first image quality circuit 721 of the 4K image quality circuit 72.
Since the feature of the histogram of the 8K signal is not different from the feature of the histogram of the 4K signal obtained by down-conversion, the feature of the histogram of the 4K signal obtained by down-conversion is used instead of the feature of the histogram of the 8K signal in the present embodiment.
The histogram detection unit 60 inputs the histogram detection result to the control unit 65. The control unit 65 controls the OSD signal generation unit 61 to generate data based on the histogram detection result, and inputs the generated data to the graphics processing unit 58. The graphic processing unit 58 outputs an image signal obtained by superimposing an OSD signal, which is data generated by the OSD signal generating unit 61 based on the histogram detection result, on the digital image signal output from the signal processing unit 51 to the image processing unit 62. The image processing unit 62 outputs the image signal to the image display unit 14. The image display unit 14 displays an image based on the input image signal. The user can confirm the actual dynamic range of the content by viewing the histogram display of the content graphically displayed on the image display unit 14.
The control unit 65 outputs a feedback signal for the image quality control of the 8K signal of the 8K image quality circuit 71 corresponding to the histogram detection result to the image quality control circuit of the 8K image quality circuit 71. The feedback signal is the same as the feedback signal for the image quality control of the 4K signal for the 4K image quality circuit 72 corresponding to the histogram detection result.
As described above, according to the image quality circuit and the image processing apparatus of the first embodiment, the 8K signal is down-converted from 8K to 4K, and is input to the 4K image quality circuit 72 as a 4K signal. Thus, feature detection (e.g., histogram detection) for the 8K signal is not required, and feature detection (e.g., histogram detection) for the 8K signal can be realized while maintaining the circuit scale of feature detection (e.g., histogram detection) for the 4K signal.
Further, according to the image processing apparatus of the first embodiment, the result of the feature detection (for example, histogram detection) for the 8K signal can be notified (displayed) in the same manner as the result of the feature detection (for example, histogram detection) for the 4K signal.
Further, according to the image processing apparatus of the first embodiment, the feedback signal for the image quality control of the 8K signal to the 8K image quality circuit 71 and the feedback signal for the image quality control of the 4K signal to the 4K image quality circuit 72 corresponding to the feature detection result (for example, the histogram detection result) are the same.
The 4K signal down-converted by the 8K → 4K down-converter 73 also includes a signal converted into a format used in an interface of a general television and capable of being output to the outside. The 4K signal down-converted by the 8K → 4K down-converter 73 also includes a signal converted into a format for other purposes such as recording to the hdd (hard Disk drive).
In the configuration of the first embodiment, the positions of the 8K image quality circuit 71 and the 4K image quality circuit 72 and the position of the 4K → 8K up-converter 74 are not limited to the positions shown in fig. 2.
(second embodiment)
Next, a second embodiment will be explained.
The second embodiment is different from the first embodiment in that, when the content does not correspond to the Dynamic HDR in which the Meta information (Meta information) is recorded, the 8K signal is down-converted from 8K to 4K and is input to the 4K image quality circuit 72 as a 4K signal. In the following description of the second embodiment, the same portions as those of the first embodiment will be omitted, and portions different from those of the first embodiment will be described.
Fig. 3 is a diagram showing an example of the configuration of the image decoder 70 and the signal processing unit 51 according to the second embodiment.
In recent years, contents corresponding to Dynamic HDR in which meta information such as a luminance range per scene (scene) or per frame is recorded have been developed. Such meta information is attached in the form of an information area (AVInfo) of HDMI (registered trademark), a decoded SEI signal, and the like. In addition, an image processing apparatus that receives such content corresponding to Dynamic HDR has also been developed.
As shown in fig. 3, the signal processing unit 51 of the digital television receiver 11 includes a meta information extracting unit 80. The meta information extraction section 80 extracts meta information (luminance range per scene or per frame, etc.) from the component signal obtained by converting the received content (4K broadcast signal) by the 4K decoder 57. The meta information extracting unit 80 extracts meta information (a luminance range per scene or frame, etc.) from the 4K signal from the external input terminal (not shown) and the 4K signal from the 8K → 4K down converter 73.
The control unit 65 of the digital television receiver 11 feeds back data based on the meta information extracted by the meta information extraction unit 80 to the image quality control circuit 712 of the 8K image quality circuit 71 and the image quality control circuit 722 of the 4K image quality circuit 72 to perform image quality control.
However, the content (8K broadcast signal) does not correspond to the Dynamic HDR, and the above-described meta information (luminance range per scene or per frame, etc.) cannot be acquired in some cases.
Therefore, in the digital television receiver 11 according to the present embodiment, when the content (8K broadcast signal) does not correspond to the Dynamic HDR, the histogram detection unit 60 of the 4K image quality circuit 72 performs histogram detection on the 4K signal down-converted by the 8K → 4K down-converter 73.
The histogram detection unit 60 inputs the histogram detection result to the control unit 65. The control unit 65 converts the histogram detection result into a form of meta information used in association with the Dynamic HDR, and feeds back data based on the meta information to the image quality control circuit 712 of the 8K image quality circuit 71 and the image quality control circuit 722 of the 4K image quality circuit 72 to perform image quality control.
As described above, according to the image quality circuit and the image processing apparatus of the second embodiment, when the content does not correspond to the Dynamic HDR in which the meta information is recorded, the 8K signal is down-converted from 8K to 4K and is input to the 4K image quality circuit 72 as a 4K signal. Thus, even when the content does not correspond to the Dynamic HDR in which the meta information is recorded, it is not necessary to perform feature detection (e.g., histogram detection) for the 8K signal, and feature detection (e.g., histogram detection) for the 8K signal can be realized while maintaining the circuit scale for performing feature detection (e.g., histogram detection) for the 4K signal.
In the image processing apparatus according to the second embodiment, the control unit 65 can more easily realize high image quality by converting the feature detection (for example, histogram detection) result into the form of meta information used in association with the Dynamic HDR.
Several embodiments of the present application have been described, but these embodiments are presented as examples and are not intended to limit the scope of the application. These new embodiments may be implemented in other various forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the present application. These embodiments and modifications thereof are included in the scope and gist of the present application, and are included in the invention described in the claims and the scope equivalent thereto.
Claims (5)
1. An image quality circuit, comprising:
a down-conversion unit that down-converts an input first signal into a second signal having a lower resolution than the first signal; and
a feature detection unit that detects a feature of a third signal, which is a signal having a lower resolution than the first signal and is input from a system different from the system in which the first signal is input,
the feature detection unit detects a feature of the second signal down-converted by the down-conversion unit.
2. The picture quality circuit according to claim 1, wherein,
the feature detection unit detects a histogram of luminance levels of pixels based on a signal as the feature detection.
3. An image processing apparatus includes:
the picture quality circuit according to claim 1 or 2; and
a control part for controlling the image quality circuit, wherein,
the control unit notifies the feature detection result detected by the feature detection unit of the image quality circuit.
4. The image processing apparatus according to claim 3,
the control unit outputs a feedback signal for controlling the image quality of the first signal based on a feature detection result detected by the feature detection unit of the image quality circuit.
5. A signal feature detection method in an image quality circuit,
the signal feature detection method comprises the following steps:
down-converting an input first signal into a second signal having a lower resolution than the first signal; and
performing feature detection of a third signal, which is a signal input by a system different from a system in which the first signal is input and having a lower resolution than the first signal,
in the feature detection of the third signal, feature detection of the second signal having been down-converted is performed.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019170854A JP7232160B2 (en) | 2019-09-19 | 2019-09-19 | IMAGE QUALITY CIRCUIT, VIDEO PROCESSING DEVICE, AND SIGNAL FEATURE DETECTION METHOD |
| JP2019-170854 | 2019-09-19 | ||
| PCT/CN2020/111831 WO2021052138A1 (en) | 2019-09-19 | 2020-08-27 | Image quality circuit, image processing apparatus, and signal feature detection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112673643A true CN112673643A (en) | 2021-04-16 |
| CN112673643B CN112673643B (en) | 2023-05-05 |
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| CN202080004669.1A Active CN112673643B (en) | 2019-09-19 | 2020-08-27 | Image quality circuit, image processing apparatus, and signal feature detection method |
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| JP (1) | JP7232160B2 (en) |
| CN (1) | CN112673643B (en) |
| WO (1) | WO2021052138A1 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP7232160B2 (en) | 2023-03-02 |
| CN112673643B (en) | 2023-05-05 |
| JP2021048534A (en) | 2021-03-25 |
| WO2021052138A1 (en) | 2021-03-25 |
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