Disclosure of Invention
The invention provides an interconnection micro-welding point, a chip and a welding method of the chip, which aim to solve the problems in the background technology.
In order to achieve the purpose, the invention is realized by the following technical scheme:
the invention provides an interconnection micro-welding spot which comprises a first copper layer, a first barrier layer, a first tin layer, a second barrier layer and a second copper layer, wherein the first barrier layer is arranged on the first copper layer, the first tin layer is arranged on the first barrier layer, the second barrier layer is arranged on the second copper layer, the second tin layer is arranged on the second barrier layer, and the first tin layer and the second tin layer are bonded into a whole in a welding state.
Optionally, the first barrier layer is at least one of a nickel layer, a gold layer, or a silver layer.
Optionally, the second barrier layer is at least one of a nickel layer, a gold layer, or a silver layer.
Optionally, the thickness of the nickel layer, the gold layer, or the silver layer is greater than or equal to 2 um.
Optionally, the material of the first copper layer and/or the second copper layer comprises zinc.
The present application also provides, as a general inventive concept, a chip including the interconnection micro-pad as described above.
As a general inventive concept, the present application also provides a soldering method of interconnecting micro pads, including:
forming a first copper layer and a second copper layer;
electroplating a first barrier layer on the first copper layer and a second barrier layer on the second copper layer;
electroplating a first tin layer on the first barrier layer, and electroplating a second tin layer on the second barrier layer;
bonding the first tin layer and the second tin layer together.
Optionally, said bonding said first tin layer and said second tin layer together comprises:
and bonding the first tin layer and the second tin layer in set bonding time by adopting hot-press welding based on preset temperature.
Optionally, the preset temperature is higher than the melting point of tin, and the bonding time is 5-20 s.
Has the advantages that:
the invention provides an interconnection micro-welding point, a chip and a welding method of the chip, wherein the interconnection micro-welding point comprises a first copper layer, a first barrier layer, a first tin layer, a second barrier layer and a second copper layer, the first barrier layer is arranged on the first copper layer, the first tin layer is arranged on the first barrier layer, the second barrier layer is arranged on the second copper layer, the second tin layer is arranged on the second barrier layer, and the first tin layer and the second tin layer are bonded into a whole in a welding state. Therefore, the holes between the interconnection micro welding points can be inhibited through the first barrier layer and the second barrier layer, and the influence on a chip structure caused by the fact that the holes are diffused into cracks can be prevented.
Detailed Description
The technical solutions of the present invention are described clearly and completely below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the present invention provides an interconnection micro solder joint, which includes a first copper layer 1, a first barrier layer 2, a first tin layer 3, a second tin layer 4, a second barrier layer 5 and a second copper layer 6, wherein the first barrier layer 2 is disposed on the first copper layer 1, the first tin layer 3 is disposed on the first barrier layer 2, the second barrier layer 5 is disposed on the second copper layer 6, the second tin layer 4 is disposed on the second barrier layer 5, and in a soldering state, the first tin layer 3 and the second tin layer 4 are bonded together.
In this embodiment, the material of the first copper layer 1 and the second copper layer 6 is copper (Cu), and the material of the first tin layer 3 and the second tin layer 4 is (Sn). It should be noted that two ends of the interconnection micro solder joint are connected to two chips, for example, the first copper layer 1, the first barrier layer 2, and the first tin layer 3 are disposed on a first chip, the second tin layer 4, the second barrier layer 5, and the second copper layer 6 are disposed on a second chip, and when packaging, the first tin layer 3 and the second tin layer 4 are bonded together, so that the two chips can be integrated.
The interconnection micro welding points can inhibit holes between the interconnection micro welding points through the first barrier layer 2 and the second barrier layer 5, and can prevent cracks from diffusing to influence the chip structure.
Optionally, the first barrier layer 2 is at least one of a nickel layer, a gold layer, or a silver layer.
That is, the material of the first barrier layer 2 may be nickel (Ni), gold (Au), silver (Ag), or a combination of any two or three of these, which is only exemplary and not limiting, and alternatively, in other possible embodiments, the material of the first barrier layer 2 may be appropriately adjusted, but any modification thereof is within the protection scope of the embodiments of the present application.
Since the diffusion coefficient and solubility of Ni, Au in the solder are very low at the same bonding temperature, in this embodiment, interdiffusion of Sn and Cu can be prevented by providing the first barrier layer 2, formation of an intermediate compound (IMC) between the first copper layer 1 and the first tin layer 3 can be prevented, generation of voids can be prevented, and a durable conductive surface can be provided for packaging of the chip.
Optionally, the second barrier layer 5 is at least one of a nickel layer, a gold layer, or a silver layer.
That is, the material of the second barrier layer 5 may be nickel (Ni), gold (Au), silver (Ag), or any two or a combination of three of these materials, which is only exemplary and not limiting, and alternatively, in other possible embodiments, the material of the second barrier layer 5 may be appropriately adjusted, but any modification thereof is within the protection scope of the embodiments of the present application.
In this embodiment, the formation of an intermediate compound (IMC) between the second copper layer 6 and the second tin layer 4 can be prevented by providing the second barrier layer 5, preventing the formation of voids.
Optionally, the thickness of the nickel layer, gold layer, or silver layer is greater than or equal to 2 um. Specifically, the thickness is determined according to the size of the interconnection micro-pad, for example, when the diameter of the interconnection micro-pad is 15-100um, the thickness of the first barrier layer 2 or the second barrier layer 5 can be 2 um.
Alternatively, in another possible embodiment, the material of the first copper layer 1 and/or the second copper layer 6 comprises zinc. That is, zinc (Zn) may be added to the material of the first copper layer 1, or may be added to the material of the second copper layer 6, or may be added to both the material of the first copper layer 1 and the material of the second copper layer 6, so that the generation of an intermediate compound (IMC) between the first copper layer 1 and the first tin layer 3, or between the second copper layer 6 and the second tin layer 4 may be prevented.
Embodiments of the present application also provide a chip including the interconnection micro solder joint as described above. Since the technical solution of this embodiment includes all technical solutions of the above embodiments, at least all technical effects of the above embodiments can be achieved, and details are not repeated here.
The embodiment of the application further provides a chip welding method, which comprises the following steps:
forming a first copper layer 1 and a second copper layer 6;
electroplating a first barrier layer 2 on the first copper layer 1 and a second barrier layer 5 on the second copper layer 6;
electroplating a first tin layer 3 on the first barrier layer 2, and electroplating a second tin layer 4 on the second barrier layer 5;
the first tin layer 3 and the second tin layer 4 are bonded to one body.
It should be noted that, the growth rate of the intermediate compound IMC of the existing Cu-Sn-Cu interconnection structure is faster along with the initial thickness and the bonding temperature, and the growth rate of IMC can be reduced after the Ni layer is added in the middle of the Cu/Sn layer by adopting the above method.
Alternatively, in another possible embodiment, the first barrier layer 2 and the second barrier layer 5 can be prepared by electroplating, magnetron sputtering, CVD (chemical vapor deposition), or the like. This is by way of example only and not by way of limitation.
Specifically, bonding the first tin layer 3 and the second tin layer 4 together includes:
the first tin layer 3 and the second tin layer 4 are bonded within a set bonding time based on a preset temperature by using thermocompression bonding.
Specifically, the welding spot bonding method can use hot-press welding, the temperature of the bonding welding spot is higher than the melting point of the Sn welding spot, the bonding gap is preferably that the upper welding spot and the lower welding spot are completely contacted and do not overflow Sn, and the bonding time can be 5 s-20 s.
The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.