CN112670267A - Interconnection micro-welding point, chip and welding method of chip - Google Patents
Interconnection micro-welding point, chip and welding method of chip Download PDFInfo
- Publication number
- CN112670267A CN112670267A CN202011496479.4A CN202011496479A CN112670267A CN 112670267 A CN112670267 A CN 112670267A CN 202011496479 A CN202011496479 A CN 202011496479A CN 112670267 A CN112670267 A CN 112670267A
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- layer
- tin
- copper
- barrier layer
- chip
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- 238000003466 welding Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 62
- 229910052718 tin Inorganic materials 0.000 claims description 66
- 239000010949 copper Substances 0.000 claims description 64
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 62
- 229910052802 copper Inorganic materials 0.000 claims description 54
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 53
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 26
- 239000010931 gold Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 14
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 12
- 229910052759 nickel Inorganic materials 0.000 claims description 12
- 229910052709 silver Inorganic materials 0.000 claims description 12
- 239000004332 silver Substances 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 11
- 238000009713 electroplating Methods 0.000 claims description 10
- 238000005476 soldering Methods 0.000 claims description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 3
- 230000008018 melting Effects 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 3
- 239000011701 zinc Substances 0.000 claims description 3
- 229910052725 zinc Inorganic materials 0.000 claims description 3
- 238000012536 packaging technology Methods 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910000765 intermetallic Inorganic materials 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910018082 Cu3Sn Inorganic materials 0.000 description 1
- 229910020888 Sn-Cu Inorganic materials 0.000 description 1
- 229910019204 Sn—Cu Inorganic materials 0.000 description 1
- AFJJOQJOZOLHGT-UHFFFAOYSA-N [Cu].[Cu].[Sn] Chemical compound [Cu].[Cu].[Sn] AFJJOQJOZOLHGT-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention relates to the packaging technology of electronic components and discloses an interconnection micro-welding spot, a chip and a welding method of the chip. Therefore, the holes between the interconnection micro welding points can be inhibited through the first barrier layer and the second barrier layer, and the influence on a chip structure caused by the fact that the holes are diffused into cracks can be prevented.
Description
Technical Field
The invention relates to the packaging technology of electronic components, in particular to an interconnection micro-welding point, a chip and a welding method of the chip.
Background
With the continuous progress of the packaging technology of electronic components, three-dimensional integrated packages have become more popular, and the three-dimensional integrated packages have advantages on system performance, including small overall size, heterogeneous integration, and significant reduction of system integration cost and power consumption. Therefore, the pitch size of the pads for flip chip bonding should be reduced.
Typically, copper (Cu) stud bumps having a height of several microns and having tin (Sn) or tin-copper (Sn-Ag) caps are used in flip chip bonding. Flip chip bonding of copper/tin (Cu/Sn) or tin/silver (Sn-Ag) pillar micro-bumps forms copper-tin-copper (Cu-Sn-Cu) interconnect structures. Cu is formed at the interface of copper-tin (Cu-Sn) or tin-copper (Sn-Cu)6Sn5And Cu3Sn interfacial Intermetallics (IMCs), which are also present in conventional solder bump interconnects. However, the tin (Sn) layer thickness of copper/tin (Cu/Sn) pillar interconnect pads is much less than that of conventional pads. Thus, the interface containing the brittle IMC in a copper/tin (Cu/Sn) pillar interconnect pad constitutes a significant portion of the interconnect micro-pad. Cu3Formation of Sn layer accompanied by Cu/Cu3The formation of Sn interfacial voids, which can degrade the mechanical properties of the columnar interconnects.
Therefore, it is an urgent problem to eliminate the voids between the interconnected micro-pads.
Disclosure of Invention
The invention provides an interconnection micro-welding point, a chip and a welding method of the chip, which aim to solve the problems in the background technology.
In order to achieve the purpose, the invention is realized by the following technical scheme:
the invention provides an interconnection micro-welding spot which comprises a first copper layer, a first barrier layer, a first tin layer, a second barrier layer and a second copper layer, wherein the first barrier layer is arranged on the first copper layer, the first tin layer is arranged on the first barrier layer, the second barrier layer is arranged on the second copper layer, the second tin layer is arranged on the second barrier layer, and the first tin layer and the second tin layer are bonded into a whole in a welding state.
Optionally, the first barrier layer is at least one of a nickel layer, a gold layer, or a silver layer.
Optionally, the second barrier layer is at least one of a nickel layer, a gold layer, or a silver layer.
Optionally, the thickness of the nickel layer, the gold layer, or the silver layer is greater than or equal to 2 um.
Optionally, the material of the first copper layer and/or the second copper layer comprises zinc.
The present application also provides, as a general inventive concept, a chip including the interconnection micro-pad as described above.
As a general inventive concept, the present application also provides a soldering method of interconnecting micro pads, including:
forming a first copper layer and a second copper layer;
electroplating a first barrier layer on the first copper layer and a second barrier layer on the second copper layer;
electroplating a first tin layer on the first barrier layer, and electroplating a second tin layer on the second barrier layer;
bonding the first tin layer and the second tin layer together.
Optionally, said bonding said first tin layer and said second tin layer together comprises:
and bonding the first tin layer and the second tin layer in set bonding time by adopting hot-press welding based on preset temperature.
Optionally, the preset temperature is higher than the melting point of tin, and the bonding time is 5-20 s.
Has the advantages that:
the invention provides an interconnection micro-welding point, a chip and a welding method of the chip, wherein the interconnection micro-welding point comprises a first copper layer, a first barrier layer, a first tin layer, a second barrier layer and a second copper layer, the first barrier layer is arranged on the first copper layer, the first tin layer is arranged on the first barrier layer, the second barrier layer is arranged on the second copper layer, the second tin layer is arranged on the second barrier layer, and the first tin layer and the second tin layer are bonded into a whole in a welding state. Therefore, the holes between the interconnection micro welding points can be inhibited through the first barrier layer and the second barrier layer, and the influence on a chip structure caused by the fact that the holes are diffused into cracks can be prevented.
Drawings
FIG. 1 is a schematic structural diagram of an interconnect microcoad in accordance with a preferred embodiment of the present invention.
Reference numerals:
1. a first copper layer; 2. a first barrier layer; 3. a first tin layer; 4. a second tin layer; 5. a second barrier layer; 6. a second copper layer.
Detailed Description
The technical solutions of the present invention are described clearly and completely below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the present invention provides an interconnection micro solder joint, which includes a first copper layer 1, a first barrier layer 2, a first tin layer 3, a second tin layer 4, a second barrier layer 5 and a second copper layer 6, wherein the first barrier layer 2 is disposed on the first copper layer 1, the first tin layer 3 is disposed on the first barrier layer 2, the second barrier layer 5 is disposed on the second copper layer 6, the second tin layer 4 is disposed on the second barrier layer 5, and in a soldering state, the first tin layer 3 and the second tin layer 4 are bonded together.
In this embodiment, the material of the first copper layer 1 and the second copper layer 6 is copper (Cu), and the material of the first tin layer 3 and the second tin layer 4 is (Sn). It should be noted that two ends of the interconnection micro solder joint are connected to two chips, for example, the first copper layer 1, the first barrier layer 2, and the first tin layer 3 are disposed on a first chip, the second tin layer 4, the second barrier layer 5, and the second copper layer 6 are disposed on a second chip, and when packaging, the first tin layer 3 and the second tin layer 4 are bonded together, so that the two chips can be integrated.
The interconnection micro welding points can inhibit holes between the interconnection micro welding points through the first barrier layer 2 and the second barrier layer 5, and can prevent cracks from diffusing to influence the chip structure.
Optionally, the first barrier layer 2 is at least one of a nickel layer, a gold layer, or a silver layer.
That is, the material of the first barrier layer 2 may be nickel (Ni), gold (Au), silver (Ag), or a combination of any two or three of these, which is only exemplary and not limiting, and alternatively, in other possible embodiments, the material of the first barrier layer 2 may be appropriately adjusted, but any modification thereof is within the protection scope of the embodiments of the present application.
Since the diffusion coefficient and solubility of Ni, Au in the solder are very low at the same bonding temperature, in this embodiment, interdiffusion of Sn and Cu can be prevented by providing the first barrier layer 2, formation of an intermediate compound (IMC) between the first copper layer 1 and the first tin layer 3 can be prevented, generation of voids can be prevented, and a durable conductive surface can be provided for packaging of the chip.
Optionally, the second barrier layer 5 is at least one of a nickel layer, a gold layer, or a silver layer.
That is, the material of the second barrier layer 5 may be nickel (Ni), gold (Au), silver (Ag), or any two or a combination of three of these materials, which is only exemplary and not limiting, and alternatively, in other possible embodiments, the material of the second barrier layer 5 may be appropriately adjusted, but any modification thereof is within the protection scope of the embodiments of the present application.
In this embodiment, the formation of an intermediate compound (IMC) between the second copper layer 6 and the second tin layer 4 can be prevented by providing the second barrier layer 5, preventing the formation of voids.
Optionally, the thickness of the nickel layer, gold layer, or silver layer is greater than or equal to 2 um. Specifically, the thickness is determined according to the size of the interconnection micro-pad, for example, when the diameter of the interconnection micro-pad is 15-100um, the thickness of the first barrier layer 2 or the second barrier layer 5 can be 2 um.
Alternatively, in another possible embodiment, the material of the first copper layer 1 and/or the second copper layer 6 comprises zinc. That is, zinc (Zn) may be added to the material of the first copper layer 1, or may be added to the material of the second copper layer 6, or may be added to both the material of the first copper layer 1 and the material of the second copper layer 6, so that the generation of an intermediate compound (IMC) between the first copper layer 1 and the first tin layer 3, or between the second copper layer 6 and the second tin layer 4 may be prevented.
Embodiments of the present application also provide a chip including the interconnection micro solder joint as described above. Since the technical solution of this embodiment includes all technical solutions of the above embodiments, at least all technical effects of the above embodiments can be achieved, and details are not repeated here.
The embodiment of the application further provides a chip welding method, which comprises the following steps:
forming a first copper layer 1 and a second copper layer 6;
electroplating a first barrier layer 2 on the first copper layer 1 and a second barrier layer 5 on the second copper layer 6;
electroplating a first tin layer 3 on the first barrier layer 2, and electroplating a second tin layer 4 on the second barrier layer 5;
the first tin layer 3 and the second tin layer 4 are bonded to one body.
It should be noted that, the growth rate of the intermediate compound IMC of the existing Cu-Sn-Cu interconnection structure is faster along with the initial thickness and the bonding temperature, and the growth rate of IMC can be reduced after the Ni layer is added in the middle of the Cu/Sn layer by adopting the above method.
Alternatively, in another possible embodiment, the first barrier layer 2 and the second barrier layer 5 can be prepared by electroplating, magnetron sputtering, CVD (chemical vapor deposition), or the like. This is by way of example only and not by way of limitation.
Specifically, bonding the first tin layer 3 and the second tin layer 4 together includes:
the first tin layer 3 and the second tin layer 4 are bonded within a set bonding time based on a preset temperature by using thermocompression bonding.
Specifically, the welding spot bonding method can use hot-press welding, the temperature of the bonding welding spot is higher than the melting point of the Sn welding spot, the bonding gap is preferably that the upper welding spot and the lower welding spot are completely contacted and do not overflow Sn, and the bonding time can be 5 s-20 s.
The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.
Claims (9)
1. The interconnection micro-welding spot is characterized by comprising a first copper layer, a first barrier layer, a first tin layer, a second barrier layer and a second copper layer, wherein the first barrier layer is arranged on the first copper layer, the first tin layer is arranged on the first barrier layer, the second barrier layer is arranged on the second copper layer, the second tin layer is arranged on the second barrier layer, and the first tin layer and the second tin layer are bonded into a whole in a welding state.
2. The interconnect microbump of claim 1, wherein the first barrier layer is at least one of a nickel layer, a gold layer, or a silver layer.
3. The interconnect microbump of claim 1, wherein the second barrier layer is at least one of a nickel layer, a gold layer, or a silver layer.
4. The interconnect microbump of claim 2 or 3, wherein the nickel layer, the gold layer or the silver layer has a thickness greater than or equal to 2 um.
5. The interconnect microbump of claim 1, wherein the material of the first copper layer and/or the second copper layer includes zinc.
6. A chip comprising the interconnect micropad of any of claims 1-5.
7. A method of die bonding, comprising:
forming a first copper layer and a second copper layer;
electroplating a first barrier layer on the first copper layer and a second barrier layer on the second copper layer;
electroplating a first tin layer on the first barrier layer, and electroplating a second tin layer on the second barrier layer;
bonding the first tin layer and the second tin layer together.
8. The soldering method according to claim 7, wherein the bonding the first tin layer and the second tin layer to one body comprises:
and bonding the first tin layer and the second tin layer in set bonding time by adopting hot-press welding based on preset temperature.
9. Soldering method according to claim 8, characterised in that the predetermined temperature is higher than the melting point of tin and the bonding time is 5-20 s.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011496479.4A CN112670267A (en) | 2020-12-17 | 2020-12-17 | Interconnection micro-welding point, chip and welding method of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011496479.4A CN112670267A (en) | 2020-12-17 | 2020-12-17 | Interconnection micro-welding point, chip and welding method of chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112670267A true CN112670267A (en) | 2021-04-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011496479.4A Pending CN112670267A (en) | 2020-12-17 | 2020-12-17 | Interconnection micro-welding point, chip and welding method of chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112670267A (en) |
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2020
- 2020-12-17 CN CN202011496479.4A patent/CN112670267A/en active Pending
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Effective date of registration: 20240126 Address after: East, 2nd floor, building C, Lugu high level Talents Innovation and entrepreneurship Park, 1698 Yuelu West Avenue, Changsha hi tech Development Zone, Hunan 410000 Applicant after: Changsha Anmuquan Intelligent Technology Co.,Ltd. Country or region after: China Address before: 410083 Hunan province Changsha Lushan Road No. 932 Applicant before: CENTRAL SOUTH University Country or region before: China Applicant before: Changsha Anmuquan Intelligent Technology Co.,Ltd. |
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