CN112670198B - Wafer testing method, device, equipment and storage medium - Google Patents
Wafer testing method, device, equipment and storage medium Download PDFInfo
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- CN112670198B CN112670198B CN202011536753.6A CN202011536753A CN112670198B CN 112670198 B CN112670198 B CN 112670198B CN 202011536753 A CN202011536753 A CN 202011536753A CN 112670198 B CN112670198 B CN 112670198B
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Abstract
The application discloses a method, a device, equipment and a storage medium for testing a wafer, wherein the method comprises the following steps: acquiring a test key coordinate of a target wafer; acquiring abnormal coordinates of a target wafer, wherein the abnormal coordinates are coordinates counted according to a test result of the same wafer as the target wafer; determining a target measurement area on a coordinate map of the target wafer according to the test key coordinates and the abnormal coordinates, wherein the target measurement area comprises the test key coordinates and overlapped coordinates in the abnormal coordinates and the coordinate map; and carrying out wafer test on the target measurement area. According to the method and the device, the target measurement area is determined on the coordinate map of the target wafer according to the test key coordinate and the abnormal coordinate, the probe of the wafer test equipment is controlled, and the wafer test is performed on the target measurement area on the target wafer on the slide stage of the wafer test equipment.
Description
Technical Field
The present application relates to the field of integrated circuit manufacturing technologies, and in particular, to a method, an apparatus, a device, and a storage medium for testing a wafer.
Background
Wafer test (WAT), such as Wafer Acceptance Test (WAT), is an electrical measurement performed on a semiconductor device on a wafer after the integrated circuit process flow is finished, and is used to check whether the process flow at each stage meets the standard, and test items include device characteristic test, capacitance test, contact resistance test, breakdown test, and the like.
In the related art, a wafer testing method is to place the wafer on a stage, and contact the wafer with a probe (probe) to detect each chip (die) on the wafer. However, since the number of chips on a wafer (especially, a wafer with a size of 8 inches or more) is large, it takes a long time to inspect each chip on the wafer, which results in low manufacturing efficiency of the integrated circuit.
Disclosure of Invention
The application provides a method, a device, equipment and a storage medium for testing a wafer, which can solve the problem that the method for testing the wafer provided by the related technology consumes long time.
In one aspect, an embodiment of the present application provides a method for testing a wafer, including:
acquiring a test key (test key) coordinate of a target wafer;
acquiring abnormal coordinates of the target wafer, wherein the abnormal coordinates are counted according to the test result of the wafer which is the same as the target wafer;
determining a target measurement area on a coordinate map of the target wafer according to the test key coordinates and the abnormal coordinates, wherein the target measurement area comprises the test key coordinates and overlapped coordinates in the abnormal coordinates and the coordinate map;
and controlling a probe of the wafer test equipment to perform wafer test on the target measurement area on the target wafer on the slide holder of the wafer test equipment.
Optionally, the wafer test is a wafer acceptance test.
Optionally, the target wafer is a wafer with a diameter greater than 8 inches.
In another aspect, an embodiment of the present application provides a device for testing a wafer, including:
the acquisition module is used for acquiring the test key coordinates of the target wafer; acquiring abnormal coordinates of the target wafer, wherein the abnormal coordinates are calculated according to the test result of the wafer same as the target wafer;
the generation module is used for determining a target measurement area on a coordinate map of the target wafer according to the test key coordinates and the abnormal coordinates, wherein the target measurement area comprises the test key coordinates and overlapped coordinates in the abnormal coordinates and the coordinate map;
and the test module is used for controlling a probe of the wafer test equipment and carrying out wafer test on the target measurement area on the target wafer positioned on the slide stage of the wafer test equipment.
Optionally, the wafer test is a wafer acceptance test.
Optionally, the target wafer is a wafer with a diameter greater than 8 inches.
On the other hand, an embodiment of the present application provides a wafer testing apparatus, including;
the wafer carrying table is used for placing a target wafer when the target wafer is tested;
a probe for contacting the target wafer to test the target wafer;
a control system comprising a processor and a memory, the memory having stored therein at least one instruction or program that is loaded and executed by the processor to implement a method of testing a wafer as described in any of the above.
In another aspect, an embodiment of the present application provides a computer-readable storage medium, where at least one instruction is stored in the storage medium, and the instruction is loaded and executed by a processor to implement the method for testing a wafer as described in any one of the above.
The technical scheme at least comprises the following advantages:
the target measurement area is determined on the coordinate map of the target wafer according to the test key coordinate and the abnormal coordinate, the probe of the wafer test equipment is controlled, and the wafer test is carried out on the target measurement area on the target wafer on the slide stage of the wafer test equipment.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a wafer test apparatus provided in an exemplary embodiment of the present application;
FIG. 2 is a flow chart of a method for testing a wafer according to an exemplary embodiment of the present disclosure;
fig. 3 is a block diagram of an apparatus for testing a wafer according to an exemplary embodiment of the present disclosure.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and operate, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, which shows a schematic diagram of a wafer testing apparatus provided in an exemplary embodiment of the present application, as shown in fig. 1, the wafer testing apparatus includes:
and a stage 110 for placing the target wafer 101 during testing of the target wafer 101.
And probes 120 for contacting the target wafer 101 to test it.
A control system 130 comprising a processor 131 and a memory 132, the processor 131 and the memory 132 being connected by a bus 133 or other means, the memory 132 having stored therein at least one instruction or program that is loaded by the processor 131 and executed by any of the following wafer test methods.
Referring to fig. 2, a flowchart of a method for testing a wafer according to an exemplary embodiment of the present application is shown, where the method is performed by the wafer testing apparatus in the embodiment of fig. 1, and the method includes:
Wherein the test key coordinates are measurement coordinates in a test key pattern on the target wafer. Optionally, the wafer test in the embodiment of the present application is a wafer acceptance test; optionally, the target wafer in the embodiment of the present application is a wafer with a diameter greater than 8 inches (for example, it may be a wafer with a diameter of 12 inches).
The historical measurement record of the wafer same as the target wafer can be obtained, historical abnormal coordinates (namely the measurement coordinates of the chip which cannot pass the wafer test) are obtained, an abnormal coordinate library is established according to the historical abnormal coordinates, and the abnormal coordinates of the target wafer can be obtained by calling the abnormal coordinate library.
The coordinate map of the target wafer stores the measurement coordinates of all the graphs on the target wafer, the coordinate overlapped with the abnormal coordinate in the coordinate map and the test key coordinate are used as a target measurement area, and the test time of the target wafer is reduced because the number of the test coordinates of the target measurement area is less than that of the test coordinates in the coordinate map.
And controlling the probe to sequentially contact each test coordinate in the target measurement area on the target wafer, and carrying out wafer test to obtain a test result.
In summary, in the embodiment of the present application, the probe of the wafer test apparatus is controlled by determining the target measurement area on the coordinate map of the target wafer according to the test key coordinate and the abnormal coordinate, so as to perform the wafer test on the target measurement area on the target wafer on the stage of the wafer test apparatus.
Referring to fig. 3, a block diagram of a wafer testing apparatus provided in an exemplary embodiment of the present application is shown, which may be implemented as the control system 130 in the embodiment of fig. 1 through software, hardware or a combination of the two. The device includes:
an obtaining module 310, configured to obtain a test key coordinate of a target wafer; and acquiring abnormal coordinates of the target wafer, wherein the abnormal coordinates are the coordinates counted according to the test result of the same wafer as the target wafer.
The generating module 320 is configured to determine a target measurement area on a coordinate map of the target wafer according to the test key coordinates and the abnormal coordinates, where the target measurement area includes the test key coordinates and overlapped coordinates in the abnormal coordinates and the coordinate map.
The testing module 330 is configured to control a probe of the wafer testing apparatus to perform a wafer test on a target measurement area on a target wafer located on a stage of the wafer testing apparatus.
Optionally, the wafer test is a wafer acceptance test.
Optionally, the target wafer is a wafer having a diameter greater than 8 inches.
The present application further provides a computer-readable storage medium, in which at least one instruction, at least one program, a set of codes, or a set of instructions is stored, and the at least one instruction, the at least one program, the set of codes, or the set of instructions is loaded and executed by the processor to implement the method for testing a wafer according to any of the above embodiments.
The application also provides a computer program product, which when running on a computer, causes the computer to execute the wafer testing method provided by the above method embodiments.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (8)
1. A method for testing a wafer, comprising:
acquiring a test key coordinate of a target wafer;
acquiring abnormal coordinates of the target wafer, wherein the abnormal coordinates are calculated according to the test result of the wafer same as the target wafer;
determining a target measurement area on a coordinate map of the target wafer according to the test key coordinates and the abnormal coordinates, wherein the target measurement area comprises the test key coordinates and overlapped coordinates in the abnormal coordinates and the coordinate map;
and controlling a probe of the wafer test equipment to perform wafer test on the target measurement area on the target wafer on the slide holder of the wafer test equipment.
2. The method of claim 1, wherein the wafer test is a wafer acceptance test.
3. The method of claim 2, wherein the target wafer is a wafer having a diameter greater than 8 inches.
4. An apparatus for testing a wafer, comprising:
the acquisition module is used for acquiring the test key coordinates of the target wafer; acquiring abnormal coordinates of the target wafer, wherein the abnormal coordinates are counted according to the test result of the wafer which is the same as the target wafer;
a generating module, configured to determine a target measurement area on a coordinate map of the target wafer according to the test key coordinates and the abnormal coordinates, where the target measurement area includes the test key coordinates and overlapped coordinates in the abnormal coordinates and the coordinate map;
and the test module is used for controlling a probe of the wafer test equipment and carrying out wafer test on the target measurement area on the target wafer on the slide holder of the wafer test equipment.
5. The apparatus of claim 4, wherein the wafer test is a wafer acceptance test.
6. The apparatus of claim 5, wherein the target wafer is a wafer having a diameter greater than 8 inches.
7. A wafer test apparatus, comprising:
the wafer carrying table is used for placing a target wafer when the target wafer is tested;
a probe for contacting the target wafer to test the target wafer;
a control system comprising a processor and a memory, the memory having stored therein at least one instruction or program that is loaded and executed by the processor to implement a method of testing a wafer as claimed in any one of claims 1 to 3.
8. A computer-readable storage medium having stored thereon at least one instruction, which is loaded and executed by a processor to implement a method for testing a wafer as claimed in any one of claims 1 to 3.
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| CN202011536753.6A CN112670198B (en) | 2020-12-23 | 2020-12-23 | Wafer testing method, device, equipment and storage medium |
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| CN202011536753.6A CN112670198B (en) | 2020-12-23 | 2020-12-23 | Wafer testing method, device, equipment and storage medium |
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| CN112670198B true CN112670198B (en) | 2022-07-05 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807212A (en) * | 2018-08-09 | 2018-11-13 | 德淮半导体有限公司 | Crystal round test approach and wafer tester |
| CN111398785A (en) * | 2020-05-26 | 2020-07-10 | 上海华虹宏力半导体制造有限公司 | Chip testing method, device and storage medium |
| CN111524823A (en) * | 2020-04-10 | 2020-08-11 | 上海华虹宏力半导体制造有限公司 | Equipment detection method and test wafer |
| CN111815565A (en) * | 2020-06-11 | 2020-10-23 | 上海华虹宏力半导体制造有限公司 | Wafer back side detection method and device and storage medium |
| CN111983412A (en) * | 2020-07-21 | 2020-11-24 | 深圳安博电子有限公司 | Monitoring system, monitoring method, monitoring terminal and storage medium |
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- 2020-12-23 CN CN202011536753.6A patent/CN112670198B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807212A (en) * | 2018-08-09 | 2018-11-13 | 德淮半导体有限公司 | Crystal round test approach and wafer tester |
| CN111524823A (en) * | 2020-04-10 | 2020-08-11 | 上海华虹宏力半导体制造有限公司 | Equipment detection method and test wafer |
| CN111398785A (en) * | 2020-05-26 | 2020-07-10 | 上海华虹宏力半导体制造有限公司 | Chip testing method, device and storage medium |
| CN111815565A (en) * | 2020-06-11 | 2020-10-23 | 上海华虹宏力半导体制造有限公司 | Wafer back side detection method and device and storage medium |
| CN111983412A (en) * | 2020-07-21 | 2020-11-24 | 深圳安博电子有限公司 | Monitoring system, monitoring method, monitoring terminal and storage medium |
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