CN112668667B - Layout file scanning method - Google Patents
Layout file scanning method Download PDFInfo
- Publication number
- CN112668667B CN112668667B CN202110088414.4A CN202110088414A CN112668667B CN 112668667 B CN112668667 B CN 112668667B CN 202110088414 A CN202110088414 A CN 202110088414A CN 112668667 B CN112668667 B CN 112668667B
- Authority
- CN
- China
- Prior art keywords
- array
- cell
- cell unit
- character string
- cell units
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000003491 array Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention provides a scanning method of a layout file, which comprises the following steps: constructing a first array and a second array; providing a layout file, scanning the layout file to obtain all CELL units, putting all the CELL units into the first array, wherein each CELL unit has an identifier; executing a character string operation instruction to change the second array into an array character string, putting all CELL units in the first array into the array character string one by one, and before putting one CELL unit into the array character string each time, matching the identification of the CELL unit to be put with the identification of the existing CELL unit in the array character string, if the matching fails, putting the CELL unit into the array character string; the invention improves the scanning efficiency of the layout file.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a method for scanning layout files.
Background
The layout contains the physical information data related to devices such as the size of the devices, the topology definition of each layer and the like, and is a bridge for manufacturing the integrated circuit from the design trend. The designed integrated circuit layout data is converted into a data format which can be read by an integrated circuit manufacturer. Currently, the industry standard data format mainly includes a universal data stream format (GENERAL DATA STREAM, GDS), and almost all integrated circuit layout design software can read and write GDS files. The GDS file contains all the information of the layout, including libraries and all the units, and retains the hierarchical structure and process layer information in the design. Namely, the GDS file is a file format of the circuit layout, and the content of the layout can be opened and seen through the integrated circuit layout design software.
Integrated circuit manufacturers need to scan the GDS file provided by the customer to list the CELL units of different IP numbers in the GDS file to enable subsequent customers to charge the user for the CELL units of different IP numbers. The GDS file is provided with a plurality of CELL units, the same CELL units exist, each CELL unit is provided with an IP number, the names and the IP numbers of the same CELL units are the same, and the names and the IP numbers of different CELL units are different. In order to find out all CELL units with different IP numbers, in the prior art, step-by-step scanning is adopted to compare all CELL units one by one, each scanned CELL unit is compared with the previous scanned CELL unit one by one to judge whether the CELL unit is the same as the previous scanned CELL unit or not, and each CELL unit scanned by the method needs to be compared with the previous scanned CELL unit one by one, so that the calculation amount is large, the scanning time is long, and the scanning efficiency is low.
Disclosure of Invention
The invention aims to provide a scanning method of a layout file, which is used for improving the scanning efficiency of the layout file.
In order to achieve the above object, the present invention provides a method for scanning a layout file, including:
constructing a first array and a second array;
Providing a layout file, scanning the layout file to obtain all CELL units, putting all the CELL units into the first array, wherein each CELL unit has an identifier;
Executing a character string operation instruction to change the second array into an array character string, putting all CELL units in the first array into the array character string one by one, and matching the identification of the CELL unit to be put with the identification of the existing CELL unit in the array character string before putting one CELL unit into the array character string each time; if the matching is failed, the CELL units are put into the array character strings, and if the matching is successful, the CELL units are not put into the array character strings until the storage of all the CELL units is completed.
Optionally, the layout file is a GDS file.
Optionally, the CELL unit is a circuit module in the layout file.
Optionally, the identification includes a name of the CELL unit.
Optionally, each CELL unit has an IP number, the same name and IP number of the CELL unit are the same, and different names and IP numbers of the CELL units are different.
Optionally, whether the matching is successful or not is judged by the names of the CELL units and the names of the CELL units existing in the array character string, if the names of the CELL units and the names of the CELL units existing in the array character string are the same, the matching is successful, and if the names of the CELL units and the names of the CELL units existing in the array character string are different, the matching is failed.
Optionally, a Match instruction is used to Match the identifier of the CELL unit to be placed with the identifier of the existing CELL unit in the array string.
Optionally, when the CELL unit is placed in the array character, the CELL unit is matched with an array character string formed after the CELL unit is stored last time.
Optionally, when the first array and the second array are constructed, the first array and the second array are both null arrays.
Optionally, the layout file is scanned using integrated circuit layout design software.
In the method for scanning the layout file, provided by the invention, a first array and a second array are constructed; providing a layout file, scanning the layout file to obtain all CELL units, putting all CELL units into a first array, wherein each CELL unit has an identifier; executing a character string operation instruction to change the second array into an array character string, putting all CELL units in the first array into the array character string one by one, and matching the identification of the CELL unit to be put with the identification of the existing CELL unit in the array character string before putting one CELL unit into the array character string each time; if the matching fails, the CELL units are put into the array character string, if the matching is successful, the CELL units are not put into the array character string until the storage of all the CELL units is completed, so that the CELL units in the array character string are different CELL units and have uniqueness; the invention carries out one-time matching judgment on the CELL unit and the array character string, judges whether the array character string has the unit same as the CELL unit or not, does not need repeated circulation to compare one by one, greatly shortens the scanning time and improves the scanning rate of the layout file.
Drawings
Fig. 1 is a flowchart of a method for scanning a layout file according to an embodiment of the present invention.
Detailed Description
The scanning method of the layout file comprises the steps of adopting a FOR circulation mode to scan all CELL units step by step, taking 10 CELL units as an example, firstly scanning the 1 st CELL unit, and storing the 1 st CELL unit into an array because the 1 st CELL unit is definitely the only CELL unit in the first scanning and no repeated CELL unit exists; scanning the 2 nd CELL unit, comparing the identification of the 2 nd CELL unit with the identification of the 1 st CELL unit at the moment to judge whether the identification is the same, if so, not putting the identification into an array, and if not, putting the identification into the array; scanning the 3 rd CELL unit, comparing the identification of the 3 rd CELL unit with the identification of the 1 st CELL unit and the identification of the 2 nd CELL unit one by one at the moment to judge whether the identification is the same, if the identification is the same, not putting the identification into an array, and if the identification is different, putting the identification into the array; scanning the 4 th CELL unit, comparing the identification of the 4 th CELL unit with the identification of the 1 st CELL unit, the identification of the 2 nd CELL unit and the identification of the 3 rd CELL unit one by one to judge whether the identification is the same, if the identification is the same, not putting the identification into an array, and if the identification is different, putting the identification into the array; and sequentially scanning the 5 th CELL unit until the 10 th CELL unit, and then scanning the 10 th CELL unit, wherein the identification of the 10 th CELL unit, the identification of the 1 st CELL unit and the identification of the 2 nd CELL unit until the identification of the 9 th CELL unit are compared one by one to judge whether the identification is the same, if the identification is the same, the identification is not put into an array, and if the identification is different, the identification is put into the array, so that the scanning of the 10 CELL units is completed. From the above, it will be found that the more the number of times that the CELL CELLs need to be compared one by one, the longer the scanning time, and when the number of CELL CELLs is larger, the scanning time is greatly increased and the scanning efficiency is low.
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 1 is a flowchart of a method provided in this embodiment. The present embodiment provides a method for scanning a layout file, so as to improve the scanning efficiency of the layout file, please refer to fig. 1, including:
step S1: constructing a first array and a second array;
Step S2: providing a layout file, scanning the layout file to obtain all CELL units, putting all CELL units into a first array, wherein each CELL unit has an identifier;
Step S3: executing a character string operation instruction to change the second array into an array character string, putting all CELL units in the first array into the array character string one by one, and matching the identification of the CELL unit to be put with the identification of the existing CELL unit in the array character string before putting one CELL unit into the array character string each time; if the matching is failed, the CELL units are put into the array character string, and if the matching is successful, the CELL units are not put into the array character string until the storage of all the CELL units is completed.
The following describes the method for scanning the layout file provided in this embodiment in detail.
Step S1 is executed: a first array and a second array are constructed.
Specifically, two arrays are constructed, namely a first array and a second array, and the constructed first array and second array are empty arrays.
Step S2 is executed: providing a layout file, scanning the layout file to obtain all CELL units, putting all CELL units into a first array, and each CELL unit is provided with an identifier.
Specifically, a layout file is provided, the layout file is a GDS file, the GDS file contains all information of the layout, wherein the information comprises a library and all CELL units, the GDS file can be opened through integrated circuit layout design software to display the layout information, and the CELL units are circuit modules in the layout file. Each CELL unit has an identifier, the identifier comprises the name of the CELL unit, each CELL unit has an IP number, the names and the IP numbers of the same CELL units are the same, and the names and the IP numbers of different CELL units are different. The IP number of the CELL unit provides payment basis for the subsequent user who needs to use the CELL unit, how many different CELL units are used is represented by how many IP numbers, and how many different CELL units need to be paid, so the purpose of scanning is to obtain different sets of CELL units so as to ensure the uniqueness of the CELL units in the sets.
After the layout file is opened through the integrated circuit layout design software, executing a program to scan the layout file so as to obtain all CELL units, wherein the CELL units comprise the same CELL unit and different CELL units, putting all the CELL units into a first array, and after all the CELL units are put into the first array, the first array only comprises all the CELL units.
Step S3 is executed: executing a character string operation instruction to change the second array into an array character string, putting all CELL units in the first array into the array character string one by one, and matching the identification of the CELL unit to be put with the identification of the existing CELL unit in the array character string before putting one CELL unit into the array character string each time; if the matching is failed, the CELL units are put into the array character string, and if the matching is successful, the CELL units are not put into the array character string until the storage of all the CELL units is completed.
Specifically, since it is not known whether the first array has the same CELL units, it is necessary to process all CELL units in the first array to ensure that the CELL units in the set are unique. And executing a string operation instruction to change the second array into an array string, putting all CELL units in the first array into the array string one by one, executing a Match instruction before putting the CELL units into the array string each time, matching the identification of the CELL units to be put with the identification of the existing CELL units in the array string once, and judging whether the array string has the same units as the CELL unit identifications to be put.
Matching is carried out through the names of the CELL units, the matching is successful if the names of the CELL units are the same, and the matching is failed if the names of the CELL units are different. If the matching is failed, the CELL units are put into the array character string, if the matching is successful, the CELL units are not put into the array character string, and the storage of the next CELL units is sequentially executed until all the CELL units are matched and stored, and at the moment, the CELL units in the array character string are different CELL units and have uniqueness. In the present embodiment, the matching is performed by the name of the CELL unit, but the present invention is not limited thereto, and other identifiers of the CELL unit may be used.
The scanning process is the execution process of the method, the method can adopt SKILL language, C language or other languages to carry out programming design to form a program file, and then the program file is imported into a path of the integrated circuit layout design software to run the program, thereby realizing the scanning mode. The invention carries out one-time matching judgment on the CELL unit and the array character string, judges whether the array character string has the unit same as the CELL unit or not, does not need repeated FOR circulation FOR comparison one by one, greatly shortens the scanning time and improves the scanning rate of the layout file.
In order to more clearly know the scanning method of the layout file provided by the invention, 10 CELL units are assumed to be arranged in one layout file. Firstly, opening a layout file through integrated circuit layout design software, executing a scanning program, and firstly listing the 10 CELL units from the layout file to be put into a first array, wherein whether the CELL units in the first array have uniqueness is not determined.
Changing the second group into an array character string by adopting a character string operation instruction, executing a Match instruction on the 1 st CELL unit and the array character string, judging whether the 1 st CELL unit and the array character string are successfully matched, wherein the array character string is empty, and putting the 1 st CELL unit into the array character string, wherein the array character string comprises the 1 st CELL unit; and executing matching of the next CELL unit, executing a Match instruction on the array character string after the 2 nd CELL unit and the last CELL unit, judging whether the array character string after the 2 nd CELL unit and the last CELL unit are successfully matched, judging whether the 2 nd CELL unit and the 1 st CELL unit are successfully matched through one-time matching, if the matching is failed, putting the 2 nd CELL unit into the array character string after the last CELL unit, wherein the array character string comprises the 1 st CELL unit and the 2 nd CELL unit, and if the matching is successful, not putting the 2 nd CELL unit into the array character string.
And sequentially executing the matching storage of the 3 rd CELL unit, the 4 th CELL unit and the 5 th CELL unit to the 10 th CELL unit, and matching the CELL unit with an array character string formed after the CELL unit is stored last time when the CELL unit is put into the array character. And when the 10 th CELL unit is matched and stored, executing a Match instruction on the 10 th CELL unit and the array character string formed after the last CELL unit is stored, and judging whether the 10 th CELL unit and the array character string formed after the last CELL unit are successfully matched or not. If the array character string formed after the last CELL storage contains 5 CELL units, executing a matching judgment to judge whether the 10 th CELL unit is matched with the CELL units in the array character string formed after the last CELL storage, if the matching is failed, placing the 10 th CELL unit into the array character string formed after the last CELL storage, at the moment, the array character string contains 6 CELL units, if the matching is successful, not placing the 10 th CELL unit into the array character string, and at the moment, completing the scanning of the 10 th CELL unit to extract all different CELL units from the 10 CELL units so as to ensure the uniqueness of the CELL units in the set.
In summary, in the method for scanning the layout file provided by the invention, a first array and a second array are constructed; providing a layout file, scanning the layout file to obtain all CELL units, putting all CELL units into a first array, wherein each CELL unit has an identifier; executing a character string operation instruction to change the second array into an array character string, putting all CELL units in the first array into the array character string one by one, and matching the identification of the CELL unit to be put with the identification of the existing CELL unit in the array character string before putting one CELL unit into the array character string each time, if the matching fails, putting the CELL unit into the array character string, if the matching succeeds, not putting the CELL unit into the array character string until the storage of all CELL units is completed, so that the CELL units in the array character string are different and have uniqueness; the invention carries out one-time matching judgment on the CELL unit and the array character string, judges whether the array character string has the unit same as the CELL unit or not, does not need repeated circulation to compare one by one, greatly shortens the scanning time and improves the scanning rate of the layout file.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (7)
1. The scanning method of the layout file is characterized by comprising the following steps:
constructing a first array and a second array;
Providing a layout file, wherein the layout file is a GDS file, scanning the layout file to obtain all CELL units, putting all the CELL units into the first array, wherein each CELL unit is provided with an identifier, the identifier comprises the name of the CELL unit, each CELL unit is provided with an IP number, the names and the IP numbers of the same CELL units are the same, and the names and the IP numbers of different CELL units are different;
Executing a character string operation instruction to change the second array into an array character string, putting all CELL units in the first array into the array character string one by one, and matching the identification of the CELL unit to be put with the identification of the existing CELL unit in the array character string before putting one CELL unit into the array character string each time; if the matching is failed, the CELL units are put into the array character strings, and if the matching is successful, the CELL units are not put into the array character strings until the storage of all the CELL units is completed.
2. The method of scanning a layout file according to claim 1, wherein said CELL unit is a circuit module in said layout file.
3. The method of claim 1, wherein the matching is determined to be successful by the names of the CELL units and the names of the CELL units existing in the array character string, if the names of the CELL units and the names of the CELL units existing in the array character string are the same, the matching is successful, and if the names of the CELL units and the names of the CELL units existing in the array character string are different, the matching is failed.
4. The method of claim 1, wherein a Match instruction is used to Match the identification of the CELL to be placed with the identification of the CELL existing in the array string.
5. The method for scanning layout file according to claim 1 or 4, wherein when said CELL unit is placed in said array character, said CELL unit is matched with an array character string formed after the last time said CELL unit is placed in said CELL unit.
6. The method for scanning a layout file according to claim 1, wherein when the first array and the second array are constructed, the first array and the second array are both null arrays.
7. The method of claim 1, wherein the layout file is scanned using integrated circuit layout design software.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110088414.4A CN112668667B (en) | 2021-01-22 | 2021-01-22 | Layout file scanning method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110088414.4A CN112668667B (en) | 2021-01-22 | 2021-01-22 | Layout file scanning method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112668667A CN112668667A (en) | 2021-04-16 |
| CN112668667B true CN112668667B (en) | 2024-05-14 |
Family
ID=75414240
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110088414.4A Active CN112668667B (en) | 2021-01-22 | 2021-01-22 | Layout file scanning method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112668667B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013106989A1 (en) * | 2012-01-16 | 2013-07-25 | 中国科学院北京基因组研究所 | Method and device for matching character strings |
| CN103309882A (en) * | 2012-03-13 | 2013-09-18 | 北京启明星辰信息技术股份有限公司 | Method and system for matching character strings under multiple modes |
| CN105574246A (en) * | 2015-12-14 | 2016-05-11 | 上海华虹宏力半导体制造有限公司 | IP module merging method of layout |
| CN106156380A (en) * | 2015-03-31 | 2016-11-23 | 展讯通信（上海）有限公司 | A kind of layout editing method and system |
| CN106855894A (en) * | 2015-12-09 | 2017-06-16 | 展讯通信（上海）有限公司 | The method and device of the positional information of memory cell in a kind of acquisition memory |
| CN107239500A (en) * | 2017-05-03 | 2017-10-10 | 成都国腾实业集团有限公司 | A kind of character string matching method and system |
| CN109471960A (en) * | 2018-11-13 | 2019-03-15 | 深圳市景旺电子股份有限公司 | The method and device of intelligent recognition PCB data tool layer name |
| CN110442756A (en) * | 2019-06-27 | 2019-11-12 | 平安科技（深圳）有限公司 | Data verification method, device, computer equipment and storage medium |
| CN110866373A (en) * | 2019-11-19 | 2020-03-06 | 北京华大九天软件有限公司 | Method and device for quickly matching layout units |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008116807A1 (en) * | 2007-03-26 | 2008-10-02 | Sagantec Israel Ltd | Semiconductor layout scanning method and system |
-
2021
- 2021-01-22 CN CN202110088414.4A patent/CN112668667B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013106989A1 (en) * | 2012-01-16 | 2013-07-25 | 中国科学院北京基因组研究所 | Method and device for matching character strings |
| CN103309882A (en) * | 2012-03-13 | 2013-09-18 | 北京启明星辰信息技术股份有限公司 | Method and system for matching character strings under multiple modes |
| CN106156380A (en) * | 2015-03-31 | 2016-11-23 | 展讯通信（上海）有限公司 | A kind of layout editing method and system |
| CN106855894A (en) * | 2015-12-09 | 2017-06-16 | 展讯通信（上海）有限公司 | The method and device of the positional information of memory cell in a kind of acquisition memory |
| CN105574246A (en) * | 2015-12-14 | 2016-05-11 | 上海华虹宏力半导体制造有限公司 | IP module merging method of layout |
| CN107239500A (en) * | 2017-05-03 | 2017-10-10 | 成都国腾实业集团有限公司 | A kind of character string matching method and system |
| CN109471960A (en) * | 2018-11-13 | 2019-03-15 | 深圳市景旺电子股份有限公司 | The method and device of intelligent recognition PCB data tool layer name |
| CN110442756A (en) * | 2019-06-27 | 2019-11-12 | 平安科技（深圳）有限公司 | Data verification method, device, computer equipment and storage medium |
| CN110866373A (en) * | 2019-11-19 | 2020-03-06 | 北京华大九天软件有限公司 | Method and device for quickly matching layout units |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112668667A (en) | 2021-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101339534B (en) | Software test apparatus and test method | |
| US8392884B2 (en) | Test case automatic generation method for testing proactive GSM application on SIM cards | |
| JP5379711B2 (en) | Computer-implemented method, system, and computer program for verifying correctness of execution history, including multiple operations executed in parallel on data structure | |
| US8151248B1 (en) | Method and system for software defect management | |
| CN103809989B (en) | The method that operating system occurs reading complete kernel daily record under core collapse case | |
| CN109726105A (en) | Test data building method, device, equipment and storage medium | |
| CN103399814B (en) | The method and device of automatic test | |
| CN110347590A (en) | The interface testing control method and device of operation system | |
| CN103713958A (en) | Method and equipment for synchronizing graphical user interface operation between machines with different languages | |
| CN111615688A (en) | Assertion verification code binding method and device | |
| CN112668667B (en) | Layout file scanning method | |
| CN107957871A (en) | A kind of front and back end synchronization canonical method of calibration based on JSR303 | |
| US7885985B2 (en) | System and method for building a datastore for storing and retrieving regression testing data for a complex application | |
| CN112433935A (en) | Test method, test device, electronic equipment and storage medium | |
| TWI611291B (en) | Computer program product for automatically generating software test data and method thereof | |
| US20080189095A1 (en) | Method and tool for generating simulation case for ic device | |
| US8000451B1 (en) | System and method for managing network switch transaction dependencies | |
| US7299447B2 (en) | Method of testing a mapping of an electrical circuit | |
| CN113672260A (en) | CPU initialization method for processor | |
| CN102279798A (en) | Software testing method and system based on point function driving | |
| CN114443375A (en) | Test method and device, electronic device and computer readable storage medium | |
| US11874764B2 (en) | Method and system for guaranteeing game quality by using artificial intelligence agent | |
| CN115495388B (en) | Chip verification method, device, equipment and medium for AI reasoning chip | |
| CN115796166B (en) | Regular expression testing method and system for intelligent logistics control system | |
| CN116861829B (en) | Method for locating errors in logic system design and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |