CN112652348B - NAND Flash chip power-down protection circuit and protection method - Google Patents
NAND Flash chip power-down protection circuit and protection method Download PDFInfo
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- 238000004146 energy storage Methods 0.000 claims abstract description 107
- 238000001514 detection method Methods 0.000 claims abstract description 42
- 239000003990 capacitor Substances 0.000 claims description 28
- 238000012544 monitoring process Methods 0.000 claims description 8
- 238000005520 cutting process Methods 0.000 claims description 3
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- 238000010586 diagram Methods 0.000 description 3
- 238000007726 management method Methods 0.000 description 3
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
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Abstract
The invention provides a power-down protection circuit and a power-down protection method for a NAND Flash chip, wherein the power-down protection circuit is connected with a system power supply, a DC-DC converter of the NAND Flash chip and a NAND Flash chip controller; the power-down protection circuit includes: the switching control circuit, the system power supply voltage detection circuit and the energy storage power supply voltage detection circuit. Compared with the prior art, the scheme adopts a mode of combining software and hardware, realizes power-down protection by combining a power-down protection circuit, a capacitance electric quantity detection mechanism and a command execution optimization mechanism, has more flexible and accurate power-down protection process, and can ensure the integrity of data to the greatest extent.
Description
Technical Field
The invention belongs to the technical field of data storage, and relates to a power-down protection circuit and a protection method for a NAND Flash chip.
Background
The development of computers has been accompanied by continuous updating of storage technologies, which play an increasingly important role and gradually become a bottleneck restricting the overall performance of the computer. In particular to the times of the rising of big data and cloud storage, the performance requirements of the system on the memory are higher and higher. The NAND Flash is outstanding as a memory, has the advantages of low production and manufacturing cost, large storable capacity, high anti-seismic and anti-magnetic performance of a storage medium, high read-write speed, nonvolatile data and the like.
In general, an SSD solid state disk is formed by a plurality of NAND Flash chips and a NAND Flash controller as a medium for data storage. However, in system level applications, there is a chance that the power supply will be unstable and even power will be lost. When the NAND Flash chip is in programming operation, power is turned off, the programmed data before the power is turned off is correct, the data which is not programmed cannot be ensured, and the NAND Flash chip is possibly still in a 1 state; when the NAND Flash chip is powered down in the erase operation, the erase is not guaranteed to be complete, i.e. some cells may be left in the "0" state. These all result in chip read errors after the NAND Flash chip is powered up again. A power-down protection mechanism is necessary to protect the data.
Currently, a large capacitor is mainly added on a board-level system, and the large capacitor is used as a power supply to continuously supply power after the power supply is powered down, so that the NAND Flash chip normally works for a period of time, but the NAND Flash controller continuously operates the NAND Flash chip according to the original command sequence to perform data programming/erasing/reading operation, or marks corresponding data blocks needing to be operated, and the NAND Flash chip is powered up again to perform operation.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the power-down protection circuit and the protection method for the NAND Flash chip are provided, and the NAND Flash chip can normally finish operation under the condition that the power supply of a system is unstable or power is off.
In order to solve the technical problems, the invention adopts the following technical scheme:
the invention provides a power-down protection circuit of a NAND Flash chip, which is used for connecting a system power supply with a DC-DC converter of the NAND Flash chip and connecting with a controller of the NAND Flash chip; the power-down protection circuit includes:
the energy storage power supply is used as a standby power supply and is used for supplying power to the NAND Flash chip under the condition that the system power supply is unstable or is powered off;
the switch control circuit is used for controlling the system power supply, the energy storage power supply and the access among the NAND Flash chips, and switching the power supply to supply power for the NAND Flash chips;
the system power supply voltage detection circuit is connected with the system power supply and is used for monitoring the voltage value of the system power supply and comparing whether the output voltage of the system power supply is smaller than a preset threshold voltage or not;
and the energy storage power supply voltage detection circuit is connected with the energy storage power supply and is used for monitoring the voltage value of the energy storage power supply and comparing whether the output voltage of the energy storage power supply is smaller than a preset threshold voltage.
Further, the switch control circuit includes a first switch control unit and a second switch control unit:
the first switch control unit is used for connecting a power supply path of the system power supply to the NAND Flash chip and providing the power supply path when the energy storage power supply needs to be charged;
the second switch control unit is used for connecting a power supply channel of the system power supply to the NAND Flash chip and disconnecting the power supply channel when the energy storage power supply needs to be charged;
the NAND Flash chip is powered by the system power supply when the first switch control unit and the second switch control unit are simultaneously closed, the NAND Flash chip is powered by the energy storage power supply when the first switch control unit is opened and the second switch control unit is closed, and the energy storage power supply is charged by the system power supply when the first switch control unit is closed and the second switch control unit is opened.
Further, the NAND Flash chip controller comprises a Cap_FALL port and a Power_FALL port;
the Cap_FALL port is connected to the energy storage power supply voltage detection circuit and is used for outputting a pulse signal after the voltage value of the energy storage power supply is reduced to a preset threshold voltage and notifying the NAND Flash chip controller that the electric quantity of the energy storage power supply is insufficient at the moment;
the power_FALL port is connected to the system Power supply voltage detection circuit and is used for outputting a pulse signal when the Power supply voltage is lower than a preset threshold voltage, and notifying the NAND Flash chip controller that the system Power supply voltage is in an unstable state and has the risk of unexpected Power failure.
Further, the system power supply voltage detection circuit and the energy storage power supply voltage detection circuit are both power supply management chips, and the energy storage power supply is a super capacitor.
The invention provides a NAND Flash chip power-down protection method based on the NAND Flash chip power-down protection circuit, which is characterized by comprising the following steps of:
the switch control circuit is in a closed state, the system power supply voltage detection circuit detects a power failure event of the system power supply, and after the power failure event of the system power supply is detected, a power supply path between the DC-DC converter of the NAND Flash chip and the system power supply is cut off;
after a power supply channel of the DC-DC converter and the external power supply is disconnected, the energy storage power supply supplies power to the NAND Flash chip, the voltage value of the energy storage power supply is monitored through the energy storage power supply voltage detection circuit, and the NAND Flash controller is informed of insufficient electric quantity of the energy storage power supply after the voltage value of the energy storage power supply is reduced to a preset threshold voltage;
and after receiving the information of insufficient electric quantity of the energy storage power supply, the NAND Flash controller marks a block which still does not execute the command, and then re-executes the command after the system resumes power supply.
Further, the system power supply voltage detection circuit detects a power failure event of the system power supply, and after detecting the power failure event of the system power supply, cutting off a power supply path between the DC-DC converter of the NAND Flash chip and the system power supply comprises:
presetting a system power supply threshold voltage;
the system Power supply voltage detection circuit detects the voltage value of the system Power supply, and when detecting that the voltage of the system Power supply is lower than the threshold voltage, the power_FALL port outputs a pulse signal;
after the NAND Flash controller detects the pulse signal, the first switch control unit is disconnected, and the energy storage power supply is adopted to continuously supply power to the NAND Flash chip.
Further, the system power supply voltage detection circuit detects a power-down event of the system power supply, and after detecting the power-down event of the system power supply, the system power supply voltage detection circuit further includes:
the NAND Flash controller evaluates the command execution time required by a command to be executed, and compares the command execution time with the expected power supply time of the energy storage power supply, wherein the command to be executed comprises a programming command, an erasing command and a reading command;
when the required power supply time is smaller than the expected power supply time of the energy storage power supply, all commands to be executed are executed in sequence;
and executing the command according to the priority level when the required power supply time is greater than the expected power supply time of the energy storage power supply.
Further, the priority order of the priority level execution commands is program command > read command > erase command.
Further, the power-down protection method further comprises the following steps:
the system periodically checks the electric quantity of the energy storage power supply, charges the energy storage power supply through the system under the condition that the electric quantity of the energy storage power supply is insufficient, and records the electric quantity of the energy storage power supply and the time for which the energy storage power supply can normally supply power through the NAND Flash controller.
Further, the power-down protection circuit charges the energy storage power supply through the system power supply by closing the first switch control unit and opening the second switch control unit.
Compared with the prior art, the invention has the beneficial effects that:
(1) The power-down protection is realized by combining software and hardware, and the integrity of data is ensured to the greatest extent.
(2) And a power-down protection circuit containing an energy storage power supply is adopted to continuously supply power to the NAND Flash chip after the system is powered down.
(3) The electric quantity of the energy storage power supply is monitored regularly, and misjudgment of the system on the power supply time of the capacitor due to aging of the capacitor is prevented.
(4) The longest time-consuming erase instruction is placed at the lowest priority, ensuring that there is enough time for the program operation to ensure data integrity.
Drawings
The following details the specific construction of the present invention with reference to the accompanying drawings
FIG. 1 is a schematic diagram of a system power supply circuit of the present invention;
FIG. 2 is a schematic diagram of a charging circuit of the energy storage power supply of the present invention;
FIG. 3 is a schematic diagram of a power supply circuit of the energy storage power supply of the present invention;
fig. 4 is a schematic flow chart of a power-down protection method of the chip of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
Example 1
Referring to fig. 1-3, the invention provides a power-down protection circuit of a NAND Flash chip, wherein the power-down protection circuit is connected with a system power supply, a DC-DC converter of the NAND Flash chip and a NAND Flash chip controller; the power-down protection circuit includes:
the energy storage power supply is used as a standby power supply and supplies power to the NAND Flash chip under the condition that the system power supply is unstable or is powered off;
the switch control circuit is used for controlling the system power supply, the energy storage power supply and the access among the NAND Flash chips, and switching the power supply to supply power for the NAND Flash chips;
the system power supply voltage detection circuit is connected with the system power supply and is used for monitoring the voltage value of the system power supply and comparing whether the output voltage of the system power supply is smaller than a preset threshold voltage or not;
and the energy storage power supply voltage detection circuit is connected with the energy storage power supply and is used for monitoring the voltage value of the energy storage power supply and comparing whether the output voltage of the energy storage power supply is smaller than a preset threshold voltage.
The switch control circuit comprises a first switch control unit S1 and a second switch control unit S2, the first switch control unit S1 and the second switch control unit S2 are in a closed state under the normal working condition, a system power supply directly supplies power to the NAND Flash chip, and after a power failure event occurs, the first switch control unit is disconnected, the second switch control unit is closed, and the energy storage power supply supplies power to the NAND Flash chip.
It should be noted that, the NAND Flash chip controller includes a cap_fail port and a power_fail port, where:
and the Cap_FALL port is connected to the energy storage power supply voltage detection circuit and is used for outputting a pulse signal after the voltage value of the energy storage power supply is reduced to a preset threshold voltage to inform the NAND Flash chip controller that the electric quantity of the energy storage power supply is insufficient at the moment.
And the power_FALL port is connected with the system Power supply voltage detection circuit and is used for outputting a pulse signal when the Power supply voltage is lower than a preset threshold voltage to inform the NAND Flash chip controller that the Power supply voltage is in an unstable state and the risk of unexpected Power failure exists.
The specific power failure monitoring process comprises the following steps: the system Power supply voltage detection circuit is a Power supply management chip, monitors the voltage value of the system Power supply, when detecting that the voltage of the system Power supply is lower than a preset threshold voltage Va, proves that the system is in an unstable state at the moment and even has accidental Power failure risk, the power_FALL port outputs a pulse signal, and after the NAND Flash controller detects that the power_FALL port is the pulse signal, the first switch control unit S1 is disconnected, the energy storage Power supply is adopted to continuously supply Power to the NAND Flash, and in the embodiment, the energy storage Power supply is a super capacitor Cap.
The energy storage power supply voltage detection circuit is also a power supply management chip, monitors the voltage value of the super capacitor Cap, and after the voltage value of the super capacitor is reduced to a preset threshold voltage Vb, the Cap_FALL outputs a pulse signal to inform the NAND Flash controller that the electric quantity of the super capacitor Cap is insufficient at the moment.
Generally, the service life of an SSD solid state disk can reach years or even decades, while a capacitor belongs to a lossy type product, and the electric quantity of the capacitor becomes smaller over time. In order to prevent the error judgment of the system on the electric quantity of the current super capacitor Cap from generating, and the control of the NAND Flash controller on the command is deviated when the system is powered off, the invention increases a capacitor electric quantity detection mechanism to detect the electric quantity of the super capacitor Cap.
The system can periodically detect the electric quantity of the super capacitor Cap through the energy storage power supply voltage detection circuit, when the electric quantity of the super capacitor Cap is insufficient, the switch S1 is closed, the switch S2 is opened, and the super capacitor Cap is charged through the system power supply, as shown in fig. 2. After a power failure event occurs in the system, the switch S1 is opened, the switch S2 is closed, power is supplied to the NAND Flash chip through the super capacitor, and when the detection power supply voltage detection circuit detects that the capacity and the electric quantity are insufficient, the Cap_FALL sends out a pulse signal to inform the NAND Flash chip controller that the energy storage power supply is insufficient at the moment.
The power-down protection circuit provided by the invention adopts the capacitor as the energy storage element, but the capacity is limited by the capacity, and the capacity is limited by the system board, so that the capacity is limited, and the power can be continuously supplied for a period of time. Therefore, when the power supply of the system is powered down and the super capacitor is used for supplying power, only a part of commands can be processed. The invention increases the command execution optimization mechanism, so that the system can ensure the integrity of the data in a limited time.
When the system Power supply is powered down, after the NAND Flash controller receives a power_FALL pulse signal, the NAND Flash controller firstly evaluates all commands to be executed, such as command execution time required by programming, erasing and reading commands, compares the command execution time with the expected Power supply time of the super capacitor Cap, and executes all commands to be executed in sequence if the command execution time is smaller than the expected Power supply time of the super capacitor Cap; if the power supply time is longer than the expected power supply time of the super capacitor Cap, executing the command according to the programming > reading > erasing priority level.
The NAND Flash controller firstly executes programming operation, writes data into corresponding units, secondly executes reading operation, and finally executes erasing instruction. Because the erase operation takes longer than the program and read operations in the program, erase, and read commands, the priority of the erase operation is the lowest, ensuring that there is enough time to perform the program operation and ensuring the integrity of the data.
After the NAND Flash controller receives the Cap_FALL pulse signal, it means that the capacity of the super capacitor Cap is insufficient, at this time, a block which has not executed the command is marked, and the command is executed again after the system is powered on.
Example 2
The invention also provides a NAND Flash chip power-down protection method based on the NAND Flash chip power-down protection circuit, which is shown in FIG. 4 and comprises the following steps:
s10, the switch control circuit is in a closed state, the system power supply voltage detection circuit detects a power failure event of the system power supply, and after the power failure event of the system power supply is detected, a power supply path between the DC-DC converter of the NAND Flash chip and the system power supply is cut off.
S20, after a power supply channel of the DC-DC converter and the external power supply is disconnected, the energy storage power supply supplies power to the NAND Flash chip, the voltage value of the energy storage power supply is monitored through the energy storage power supply voltage detection circuit, and after the voltage value of the energy storage power supply is reduced to a preset threshold voltage, the NAND Flash controller is informed of the insufficient electric quantity of the energy storage power supply.
S30, after receiving the information of insufficient electric quantity of the energy storage power supply, the NAND Flash controller marks a block which still does not execute the command, and re-executes the command after the system resumes power supply.
Step S10, detecting a power failure event of a system power supply by a system power supply voltage detection circuit, and after detecting the power failure event of the system power supply, cutting off a power supply path between a DC-DC converter of the NAND Flash chip and the system power supply, wherein the power supply path comprises:
presetting a system power supply threshold voltage; the system Power supply voltage detection circuit detects the voltage value of a system Power supply, and when detecting that the voltage of the system Power supply is lower than the threshold voltage, the power_FALL port outputs a pulse signal; after the NAND Flash controller detects the pulse signal, the first switch control unit is disconnected, and the energy storage power supply is adopted to continuously supply power to the NAND Flash chip.
After the system power supply voltage detection circuit detects a power failure event of the system power supply, the NAND Flash controller evaluates the command execution time required by a command to be executed, and compares the command execution time with the estimated power supply time of the energy storage power supply, wherein the command to be executed comprises programming, erasing and reading commands; when the required power supply time is smaller than the expected power supply time of the energy storage power supply, all commands to be executed are executed in sequence; and when the required power supply time is longer than the expected power supply time of the energy storage power supply, executing the commands according to the priority level, wherein the priority order of the priority level execution commands is that the programming command is more than the reading command is more than the erasing command.
Further, the power-down protection method provided by the invention further comprises the following steps:
the system can periodically check the electric quantity of the energy storage power supply through the voltage detection circuit of the energy storage power supply, and record the electric quantity of the energy storage power supply and the time for which the energy storage power supply can normally supply power through the NAND Flash controller; under the condition that the electric quantity of the super capacitor is insufficient, the energy storage power supply is charged through the system power supply by closing the first switch control unit and opening the second control unit.
From the above description, the beneficial effects of the invention are as follows:
(1) The power-down protection is realized by combining software and hardware, and the integrity of data is ensured to the greatest extent.
(2) And a power-down protection circuit containing an energy storage power supply is adopted to continuously supply power to the NAND Flash chip after the system is powered down.
(3) The electric quantity of the energy storage power supply is monitored regularly, and misjudgment of the system on the power supply time of the capacitor due to aging of the capacitor is prevented.
(4) Placing the longest time-consuming erase command at the lowest priority, ensuring that there is enough time for the programming operation to ensure the integrity of the data; the first and second … … are only names thereof, and do not represent differences in importance and position.
Here, upper, lower, left, right, front, and rear represent only their relative positions and do not represent their absolute positions.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present invention.
Claims (8)
1. The power-down protection circuit of the NAND Flash chip is characterized by being used for connecting a system power supply with a DC-DC converter of the NAND Flash chip and connecting a NAND Flash controller; the power-down protection circuit includes:
the energy storage power supply is used as a standby power supply and is used for supplying power to the NAND Flash chip under the condition that the system power supply is unstable or is powered off;
the switch control circuit is used for controlling the system power supply, the energy storage power supply and the access between the NAND Flash chips, switching the power supply to supply power for the NAND Flash chips and providing a power supply access when the energy storage power supply needs to be charged;
the system power supply voltage detection circuit is connected with the system power supply and is used for monitoring the voltage value of the system power supply and comparing whether the output voltage of the system power supply is smaller than a preset threshold voltage or not;
the energy storage power supply voltage detection circuit is connected with the energy storage power supply and used for monitoring the voltage value of the energy storage power supply and comparing whether the output voltage of the energy storage power supply is smaller than a preset threshold voltage or not;
the NAND Flash controller is used for: evaluating the command execution time required by a command to be executed, and comparing the command execution time with the expected power supply time of the energy storage power supply, wherein the command to be executed comprises programming, erasing and reading commands;
when the required power supply time is smaller than the expected power supply time of the energy storage power supply, all commands to be executed are executed in sequence;
executing the command according to the priority level when the required power supply time is longer than the expected power supply time of the energy storage power supply; the priority order of the priority level execution command is a programming command, a reading command and an erasing command, and the erasing command takes the longest time;
and after receiving the information of insufficient electric quantity of the energy storage power supply sent by the energy storage power supply voltage detection circuit, marking the block which still does not execute the command, and re-executing the command after the system is powered back.
2. The NAND Flash chip power down protection circuit of claim 1, wherein the switch control circuit comprises a first switch control unit and a second switch control unit:
the first switch control unit is used for connecting a power supply path between the system power supply and the NAND Flash chip and providing the power supply path when the energy storage power supply needs to be charged;
the second switch control unit is used for connecting a power supply channel between the system power supply and the NAND Flash chip and disconnecting the power supply channel when the energy storage power supply needs to be charged;
the NAND Flash chip is powered by the system power supply when the first switch control unit and the second switch control unit are simultaneously closed, the NAND Flash chip is powered by the energy storage power supply when the first switch control unit is opened and the second switch control unit is closed, and the energy storage power supply is charged by the system power supply when the first switch control unit is closed and the second switch control unit is opened.
3. The NAND Flash chip Power down protection circuit of claim 2, wherein the NAND Flash controller comprises a cap_fail port and a power_fail port, wherein:
the Cap_FALL port is connected to the energy storage power supply voltage detection circuit and is used for outputting a pulse signal after the voltage value of the energy storage power supply is reduced to a preset threshold voltage to inform the NAND Flash controller that the electric quantity of the energy storage power supply is insufficient at the moment;
the power_FALL port is connected to the system Power supply voltage detection circuit and is used for outputting a pulse signal when the voltage value of the system Power supply is lower than a preset threshold voltage, and notifying the NAND Flash controller that the system Power supply voltage is in an unstable state and has the risk of unexpected Power failure.
4. The NAND Flash chip power-down protection circuit of claim 2, wherein the system power supply voltage detection circuit and the energy storage power supply voltage detection circuit are both power management chips, and the energy storage power supply is a super capacitor.
5. A NAND Flash chip power-down protection method based on the NAND Flash chip power-down protection circuit of any one of claims 1 to 4, characterized in that the NAND Flash chip power-down protection method comprises:
the method comprises the steps that a switch control circuit is in a closed state, a system power supply voltage detection circuit detects a power failure event of a system power supply, and after the power failure event of the system power supply is detected, a power supply path between a DC-DC converter of the NAND Flash chip and the system power supply is cut off through the switch control circuit; the switch control circuit is also used for providing a power supply path when the energy storage power supply needs to be charged;
the NAND Flash controller evaluates the command execution time required by a command to be executed, and compares the command execution time with the estimated power supply time of the energy storage power supply, wherein the command to be executed comprises programming, erasing and reading commands;
when the required power supply time is smaller than the expected power supply time of the energy storage power supply, all commands to be executed are executed in sequence;
executing the command according to the priority level when the required power supply time is longer than the expected power supply time of the energy storage power supply; the priority order of the priority level execution command is a programming command, a reading command and an erasing command, and the erasing command takes the longest time;
after the power supply paths of the DC-DC converter and the system power supply are disconnected, the energy storage power supply is used for supplying power to the NAND Flash chip;
monitoring the voltage value of the energy storage power supply through the energy storage power supply voltage detection circuit, and notifying the NAND Flash controller that the electric quantity of the energy storage power supply is insufficient after the voltage value of the energy storage power supply is reduced to a preset threshold voltage;
and after receiving the information of insufficient electric quantity of the energy storage power supply, the NAND Flash controller marks a block which still does not execute the command, and then re-executes the command after the system resumes power supply.
6. The NAND Flash chip power-down protection method of claim 5, wherein the system power supply voltage detection circuit detects a power-down event of a system power supply, and after detecting the power-down event of the system power supply, cutting off a power supply path between the DC-DC converter of the NAND Flash chip and the system power supply comprises:
presetting a system power supply threshold voltage;
the system Power supply voltage detection circuit detects the voltage value of the system Power supply, and when detecting that the voltage of the system Power supply is lower than the threshold voltage, the power_FALL port of the NAND Flash controller outputs a pulse signal;
after the NAND Flash controller detects the pulse signal, the first switch control unit of the switch control circuit is disconnected, and the energy storage power supply is adopted to continuously supply power to the NAND Flash chip.
7. The NAND Flash chip power-down protection method of claim 5, further comprising:
the system periodically checks the electric quantity of the energy storage power supply, charges the energy storage power supply through the system power supply under the condition that the electric quantity of the energy storage power supply is insufficient, and records the electric quantity of the energy storage power supply and the time for which the energy storage power supply can normally supply power through the NAND Flash controller.
8. The NAND Flash chip power-down protection method of claim 5, wherein the energy storage power supply is charged via the system power supply by closing a first switch control unit of the NAND Flash controller, opening a second switch control unit of the NAND Flash controller.
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