CN111581012B - Solid state disk - Google Patents
Solid state disk Download PDFInfo
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- CN111581012B CN111581012B CN201910116039.2A CN201910116039A CN111581012B CN 111581012 B CN111581012 B CN 111581012B CN 201910116039 A CN201910116039 A CN 201910116039A CN 111581012 B CN111581012 B CN 111581012B
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- flash memory
- channel
- memory chip
- write
- controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1446—Point-in-time backing up or restoration of persistent data
- G06F11/1456—Hardware arrangements for backup
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1446—Point-in-time backing up or restoration of persistent data
- G06F11/1458—Management of the backup or restore process
Abstract
The invention discloses a solid state disk which comprises a controller, a random access memory cache buffer, a channel converter module, a main flash memory chip module and a backup flash memory chip. When the flash memory chip in the main flash memory chip module enters a write protection state due to a specific failure event, the controller can gradually and dispersedly write the used storage data volume in the flash memory chip into the respective residual unused storage space in the rest flash memory chips which do not enter the write protection state through the cache buffer of the random access memory, and then the conduction position of the channel converter corresponding to the flash memory chip is converted, so that the rest flash memory chips which do not enter the write protection state can not be written into the storage data in the flash memory chip, and the backup flash memory chip is written into the flash memory chip through the cache buffer of the random access memory.
Description
Technical Field
The present invention relates to a solid state disk, and more particularly, to a solid state disk with improved backup effect of stored data when a flash memory module in the solid state disk fails.
Background
Solid State Disk (Solid State Disk, solid State Drive, SSD for short) uses Flash memory (Flash memory) to store data, which is completely different from the traditional hard Disk that uses magnetic technology to store data, and the mainstream Solid State Disk product in the market stores data by using Flash memory such as NAND Flash. Compared with the traditional hard disk, the solid state hard disk has many advantages, such as silence, shock resistance, power saving, high efficiency and good heat dissipation. In addition, the solid state disk reduces the mechanical tracking time, and the cost for accessing any stored address is equal, i.e. the input/output performance is much faster than that of the traditional hard disk.
However, the solid state disk has several inherent technical problems, including inefficient write-in times, susceptibility to read disturbance, irrecoverability in damage, and drop-out speed. In the aspect of low efficiency of writing times, each electric brake on the flash memory has certain limitation of writing times, and the flash memory can not be written into a read-only state after the service life is over; regarding the read disturb problem, the flash memory may cause the content of the memory cells close to each other in the same sector to change (become a write operation) with multiple reads, which is called read disturb. The read count threshold that causes the read disturb phenomenon is between the read count threshold of the sector erased to avoid the read disturb problem, and the flash memory controller usually calculates the total read count from the sector erased last time, when the count value exceeds the set target value threshold, the affected sector is copied to a new sector, and then the original sector is erased and released to the sector recovery area. The original sector will behave as a new sector after the erase operation. If the flash memory controller has no real-time intervention, a read disturb Error will occur, and if the Error is too many to be repaired by an Error Check and Correction (Error Check and Correction) mechanism, a possible data loss will accompany; regarding the irrecoverable problem during damage, when flash memory particles which are used for storing data are damaged, the existing data recovery technology cannot recover the data in the damaged chip, and on the contrary, the traditional mechanical hard disk can also recover a lot of data through the data recovery technology; the speed drop problem is because the speed of the solid state disk decreases with the number of writes, and also decreases when the solid state disk is nearly full.
The technical problem of the solid state disk mainly arises from the characteristics of the NAND flash memory itself, and solid state disk manufacturers generally improve the above problems by using an Over-Provisioning mechanism as a Garbage collection (Garbage collection), an ECC or other data protection technique, and a Wear Leveling mechanism, but the above solid state disk problem solving mechanism still has room for improvement.
Disclosure of Invention
The main objective of the present invention is to provide a solid state disk, so that when a main flash memory chip inside the solid state disk enters a write protection state due to a specific failure event, the whole solid state disk can still keep normal operation.
To achieve the foregoing objective, the present invention provides a solid state disk, which includes a controller, a ram cache buffer, a channel converter module, a main flash memory module, and a backup flash memory chip. The controller is electrically connected to a random access memory cache buffer for buffering data read and/or written by the solid state disk. The channel converter module comprises a plurality of channel converters, wherein any one of the channel converters is provided with a first connecting end, a second connecting end and a third connecting end, the first connecting end is electrically connected with the controller, the channel converter is controlled at a first channel conduction position or a second channel conduction position by the controller, when the channel converter is at the first channel conduction position, the first connecting end of the channel converter is electrically communicated with the second connecting end, and when the channel converter is at the second channel conduction position, the first connecting end of the channel converter is electrically communicated with the third connecting end. The main flash memory chip module comprises a plurality of flash memory chips, the number of the plurality of flash memory chips is equal to that of the plurality of channel converters, and the flash memory chips correspond to the channel converters one by one, wherein when any flash memory chip in the main flash memory chip module is positioned at the first channel conduction position of the corresponding channel converter, the second connection end of the channel converter is electrically connected with the flash memory chips, so that the flash memory chips, the controller and the random access memory cache buffer are electrically connected. When any channel converter in the channel converter module is at the second channel conduction position, the third connecting end of the channel converter is electrically connected with the backup flash memory chip, so that the backup flash memory chip, the controller and the random access memory cache buffer are electrically connected.
Wherein, when a flash memory chip in the main flash memory chip module enters a write protection state due to a specific failure event, the controller calculates the used storage data amount in the flash memory chip entering the write protection state, calculates the remaining unused storage space of each of the remaining flash memory chips not entering the write protection state in the main flash memory chip module, sequentially and dispersedly writes the storage data in the flash memory chip entering the write protection state into the remaining unused storage space of each of the remaining flash memory chips not entering the write protection state via the random access memory cache buffer, and converts the channel converter corresponding to the flash memory chip entering the write protection state to the second channel conducting position. For the storage data in the flash memory chips entering the write protection state, the controller writes the storage data into the backup flash memory chips through the random access memory cache buffer, wherein the storage data cannot be written into the rest of the flash memory chips which do not enter the write protection state.
In the above embodiments, the number of times of writing and erasing of the backup flash memory chips in the solid state disk of the present invention is higher than that of the plurality of flash memory chips in the main flash memory module.
In the above embodiment, the specific failure event in the solid state disk of the present invention includes that the number of times of writing and erasing of the flash memory chips in the main flash memory chip module exceeds the first threshold value.
In the above embodiments, the specific failure event in the solid state disk further includes that the number of defective rails of the flash memory chips in the main flash memory chip module exceeds a second threshold.
Through the design, when the flash memory chip in the solid state disk enters a write-in protection state due to a specific failure event, the whole solid state disk can still continuously keep normal operation.
Drawings
Fig. 1 is a first embodiment of a solid state disk provided in the present invention.
Fig. 2 is a second embodiment of the solid state disk provided in the present invention. Wherein, in the figures, the various reference numbers: 1: a solid state disk; 10: a controller; 20: a random access memory cache buffer; 30: a primary flash memory chip module; 301: a flash memory chip; 31: the flash memory chips respectively have unused storage space; 40: backing up a flash memory chip; 50: a channel converter module; 501: a channel converter; 5011: a first connection end; 5012: a second connection end; 5013: a third connection end; 591: a first channel conduction position; 592: a second channel conducting position.
Detailed Description
First, referring to fig. 1, a solid state disk according to a first embodiment of the present invention is shown. The internal memory configuration of the solid state disk 1 includes a controller 10, a ram cache 20, a main flash chip module 30, a backup flash chip 40, and a channel converter module 50.
In one possible embodiment, the controller 10 is electrically connected to a random access memory cache buffer 20 for buffering solid state disk read and/or write data.
The channel converter module 50 comprises a plurality of channel converters, wherein any one of the channel converters 501 in the channel converter module 50 has a first connection end 5011, a second connection end 5012 and a third connection end 5013, the first connection end 5011 is electrically connected to the controller 10, and any one of the channel converters 501 in the channel converter module 50 is controlled to be in a first channel conducting position 591 or a second channel conducting position 592 by the controller 10, when any one of the channel converters 501 in the channel converter module 50 is in the first channel conducting position 591, the first connection end 5011 of the channel converter 501 is electrically connected to the second connection end 5012, and when any one of the channel converters 501 in the plurality of channel converters 50 is in the second channel conducting position 592, the first connection end 5011 of the channel converter 501 is electrically connected to the third connection end 5013. The main flash chip module 30 comprises a plurality of flash chips, the number of the flash chips is equal to the number of the channel switches and the flash chips correspond to the channel switches one by one, wherein when any flash chip 301 in the main flash chip module 30 is located at the first channel conducting position 591 of the corresponding channel switch 501, the second connecting terminal 5012 of the channel switch is electrically connected to the flash chip 301, so that the flash chip 301, the controller 10 and the ram cache buffer 20 are electrically connected. When any channel switch 501 in the channel switch module 50 is at the second channel conducting position 592, the third connecting terminal 5013 of the channel switch 501 is electrically connected to the backup flash chip 40, such that the backup flash chip 40, the controller 10, and the ram cache buffer 20 are electrically connected.
It should be noted that, in the present embodiment, the channel switch 501 utilizes the first connection end 5011, the second connection end 5012 and the third connection end 5013 to switch the first channel conducting position 591 and the second channel conducting position 592, which is only for illustration and not limited thereto.
Wherein, when the flash memory chip 301 in the main flash memory chip module 30 enters the write-protect state due to a specific failure event, the controller 10 calculates the amount of the used storage data in the flash memory chip 301, calculates the remaining unused storage space 31 of each of the remaining flash memory chips that do not enter the write-protect state in the main flash memory chip module 30, sequentially and dispersedly writes the storage data in the flash memory chip 301 into the remaining unused storage space 31 of each of the remaining flash memory chips that do not enter the write-protect state via the ram cache buffer 20, and switches the channel switch 501 corresponding to the flash memory chip 301 to the second channel conducting position 592 (shown in fig. 2), so as to electrically isolate the flash memory chip 301 in the write-protect state, thereby the whole solid state disk can still keep normal operation.
Next, referring to fig. 2, a second embodiment of the solid state disk according to the present invention is shown. The second embodiment is partially similar to the first embodiment, except that, in comparison with the first embodiment, if the amount of the used storage data in the flash memory chip 301 entering the write-protect state exceeds the total of the remaining unused storage spaces 31 of the remaining flash memory chips not entering the write-protect state, the controller further writes the storage data in the flash memory chip 301 into the remaining flash memory chips not entering the write-protect state, writes the storage data into the backup flash memory chip 40 through the ram cache buffer 20 after switching the channel switch 501 to the second channel conducting position 592, and then maintains the channel switch 501 to the second channel conducting position 592 to electrically isolate the flash memory chip 301 entering the write-protect state, so that the entire solid state hard disk can still keep operating normally.
In one possible implementation of the first or second embodiments, the backup flash chip 40 may be Single Level Cell (SLC) flash due to a higher write erase count (P/E cycles) of Single Level Cell (SLC) flash compared to other flash memories such as multi-level cell (MLC) and Triple Level Cell (TLC). Generally, the write-erase count of single-level memory (SLC) flash memory is about 100,000, the multi-level Memory (MLC) is about 10,000, and the triple-level memory (TLC) is about 1000, so single-level memory (SLC) flash memory is particularly suitable for some applications with high requirements on solid state disks.
In a possible implementation manner of the first or second embodiment, the specific failure event causing the flash memory chip 301 to enter the read-write state includes that the number of write-erase times of the flash memory chip 301 exceeds a first threshold (threshold), which may be determined according to the type of the selected flash memory chip, for example, when single-level Storage (SLC) flash memory is selected, the first threshold is about 100,000 times, and so on.
In a possible implementation manner of the first or second embodiment, the specific failure event causing the flash memory chip 301 to enter the read/write state further includes that the number of defective rails of the flash memory chip 301 exceeds a second threshold. Generally, before writing data into a memory location of the flash memory chip 301, the controller 10 checks the situation in advance, and if the controller 10 cannot perform a write operation on the memory location, the memory location is marked as unusable, which becomes a bad sector, and data is no longer written, wherein the value of the second threshold value is set by a manufacturer of each solid state disk in a firmware setup at the time of factory shipment, which will not be described in detail in this embodiment.
Compared with the prior art, the solid state disk provided by the invention has the advantages that when the internal flash memory chip enters the write-in protection state due to the specific failure event, the whole solid state disk can still continuously keep normal operation, so that the reliability of data storage of the solid state disk is effectively improved.
Claims (4)
1. A solid state disk, comprising:
a controller;
a random access memory cache buffer electrically connected to the controller;
a channel switch module, including a plurality of channel switches, electrically connected to the controller, wherein the controller controls each of the plurality of channel switches to be at a first channel conducting position or a second channel conducting position;
a main flash chip module including a plurality of flash chips, the number of the plurality of flash chips being equal to the number of the plurality of channel converters and corresponding to each of the plurality of channel converters one by one, wherein when any one of the flash chips in the main flash chip module is located at the first channel conducting position, the flash chip is electrically connected to the controller through the channel converter; and
a backup flash memory chip, wherein the backup flash memory chip is electrically connected to the controller via the channel switch when any one of the channel switches in the channel switch module is in the second channel conducting position,
wherein, when a flash memory chip in the main flash memory chip module enters a write-in protection state due to a specific failure event, the controller calculates the used storage data amount in the flash memory chip entering the write-in protection state, calculates the remaining unused storage space of each of the remaining flash memory chips not entering the write-in protection state in the main flash memory chip module, sequentially and dispersedly writes the storage data in the flash memory chip entering the write-in protection state into the remaining unused storage space of each of the remaining flash memory chips not entering the write-in protection state via the ram cache buffer, and converts the channel converter corresponding to the flash memory chip entering the write-in protection state to the second channel conducting position; and
wherein the controller further writes the storage data that cannot be written into the remaining flash memory chips that do not enter the write-protected state into the backup flash memory chip using the RAM cache buffer.
2. The solid state disk of claim 1, wherein the backup flash memory chip has a higher number of write erasures than the plurality of flash memory chips.
3. The solid state disk of claim 2, wherein the specific failure event comprises a number of write erasures of the flash memory chips exceeding a first threshold value.
4. The solid state disk of claim 2, wherein the specific failure event comprises a number of defective rails of the flash memory chip exceeding a second threshold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910116039.2A CN111581012B (en) | 2019-02-15 | 2019-02-15 | Solid state disk |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910116039.2A CN111581012B (en) | 2019-02-15 | 2019-02-15 | Solid state disk |
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| Publication Number | Publication Date |
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| CN111581012A CN111581012A (en) | 2020-08-25 |
| CN111581012B true CN111581012B (en) | 2023-02-28 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101399076A (en) * | 2007-09-28 | 2009-04-01 | 智多星电子科技有限公司 | Electronic data flash memory card, method for control and method for determining type of flash memory |
| TW201333682A (en) * | 2011-11-09 | 2013-08-16 | Apple Inc | Data protection from write failures in nonvolatile memory |
| CN107102819A (en) * | 2014-12-12 | 2017-08-29 | 西安三星电子研究有限公司 | The method and apparatus of data is write to solid state hard disc |
| CN109164975A (en) * | 2018-06-28 | 2019-01-08 | 华为技术有限公司 | A kind of method and solid state hard disk writing data into solid state hard disk |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014204331A1 (en) * | 2013-06-17 | 2014-12-24 | Llc "Topcon Positioning Systems" | Nand flash memory interface controller with gnss receiver firmware booting capability |
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2019
- 2019-02-15 CN CN201910116039.2A patent/CN111581012B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101399076A (en) * | 2007-09-28 | 2009-04-01 | 智多星电子科技有限公司 | Electronic data flash memory card, method for control and method for determining type of flash memory |
| TW201333682A (en) * | 2011-11-09 | 2013-08-16 | Apple Inc | Data protection from write failures in nonvolatile memory |
| CN107102819A (en) * | 2014-12-12 | 2017-08-29 | 西安三星电子研究有限公司 | The method and apparatus of data is write to solid state hard disc |
| CN109164975A (en) * | 2018-06-28 | 2019-01-08 | 华为技术有限公司 | A kind of method and solid state hard disk writing data into solid state hard disk |
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| CN111581012A (en) | 2020-08-25 |
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