CN112649681A - MCU chip electromagnetic compatibility test circuit - Google Patents
MCU chip electromagnetic compatibility test circuit Download PDFInfo
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- CN112649681A CN112649681A CN202010834136.8A CN202010834136A CN112649681A CN 112649681 A CN112649681 A CN 112649681A CN 202010834136 A CN202010834136 A CN 202010834136A CN 112649681 A CN112649681 A CN 112649681A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/001—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention discloses an MCU chip electromagnetic compatibility test circuit, which comprises a test unit, a test unit and a control unit, wherein the test unit is used for testing an MCU chip U1 to be tested; the testing unit comprises a testing main board, a fixed mounting position of the MCU chip to be tested is arranged on the testing main board, the MCU chip to be tested is mounted on the fixed mounting position of the MCU chip to be tested, a peripheral circuit connected with the MCU chip to be tested is arranged on the testing main board, and the testing main board is provided with an integrated electromagnetic compatibility testing unit for inspecting distance variables corresponding to the MCU chip to be tested; the invention provides an MCU chip electromagnetic compatibility test circuit, the structure is set up ingeniously and arrange rationally, the invention; in addition, the invention designs an integrated electromagnetic compatibility testing unit to carry out radiation testing and anti-interference testing on the MCU chip, thereby improving the testing efficiency.
Description
Technical Field
The invention relates to the technical field of MCU chip testing, in particular to an MCU chip electromagnetic compatibility testing circuit.
Background
Electromagnetic Compatibility (EMC) refers to the ability of a device or system to perform satisfactorily in its Electromagnetic environment without intolerable Electromagnetic disturbance to any device in its environment. Therefore, the EMC comprises two requirements, namely that Electromagnetic Disturbance (Electromagnetic Disturbance) generated by equipment to the environment in the normal operation process cannot exceed a certain limit value; on the other hand, the device has a certain degree of immunity to Electromagnetic disturbance existing in the environment, namely Electromagnetic Susceptibility (EMS); therefore, the inventor provides an MCU chip electromagnetic compatibility test circuit by integrating various factors. Past studies of electromagnetic compatibility have not been rigorous outside the military field, and most device manufacturers are not concerned with electromagnetic compatibility issues. But as the clock frequency of modern digital devices using lower signal voltages increases rapidly, the problem of electromagnetic compatibility becomes more and more important. Many countries recognize this emerging problem and issue political directives to the relevant equipment manufacturers that require that only equipment meeting the basic requirements be sold. Electromagnetic Interference (EMI) is called Electromagnetic Interference (EMI), and there are two types of Interference, namely conducted Interference and radiated Interference.
Most of the electromagnetic compatibility test circuits of the current MCU chip do not consider the influence of distance variables on electromagnetic compatibility, and in addition, radiation test and anti-interference test need to be independently carried out, so that the test is inconvenient and the test efficiency is low.
Disclosure of Invention
The invention aims to provide an MCU chip electromagnetic compatibility test circuit to solve the problems in the background technology.
In order to achieve the purpose, the invention provides the following technical scheme:
an MCU chip electromagnetic compatibility test circuit comprises a test unit, a test unit and a control unit, wherein the test unit is used for testing an MCU chip U1 to be tested; the test unit comprises a test mainboard, wherein a fixed mounting position of the MCU chip to be tested is arranged on the test mainboard, the MCU chip to be tested is mounted on the fixed mounting position of the MCU chip to be tested, a peripheral circuit connected with the MCU chip to be tested is arranged on the test mainboard, and the test mainboard is provided with an integrated electromagnetic compatibility test unit for inspecting distance variables corresponding to the MCU chip to be tested.
During operation, the electromagnetic compatibility test unit for inspecting the distance variable carries out electromagnetic compatibility tests with different distances on the MCU chip to be tested, the safe distance of the electromagnetic compatibility of the MCU chip to be tested is tested, in addition, the electromagnetic compatibility test unit of the integrated type carries out radiation test and anti-interference test on the MCU chip, and the test efficiency is improved.
As a further scheme of the invention: the integrated electromagnetic compatibility testing unit comprises an antenna unit and a measurement and control unit, wherein the antenna unit comprises at least two testing antennas, the distances between the testing antennas and the MCU chip to be tested are increased in an equidifferent mode, and interference receiving and transmitting circuits connected with the testing antennas are respectively arranged in the measurement and control unit corresponding to testing wires; when the interference receiving and transmitting circuit works, the interference signal generated by the interference receiving and transmitting circuit is used for interfering the MCU chip to be tested which normally works, the influence on the MCU chip to be tested is monitored, or the interference receiving and transmitting circuit is used for receiving the electromagnetic radiation generated by the MCU chip to be tested which normally works, and the electromagnetic radiation value is analyzed and calculated.
As a further scheme of the invention: and the antenna unit is internally provided with a first antenna, a second antenna and a third antenna, and the distances between the first antenna, the second antenna and the third antenna and the MCU chip to be detected are increased progressively by taking the tolerance as the distance value between the first antenna and the MCU chip to be detected.
As a further scheme of the invention: the first antenna, the second antenna, the third antenna and the MCU chip to be tested are arranged on the test mainboard along a straight line.
As a further scheme of the invention: the measurement and control unit comprises a measurement and control main board, wherein a measurement and control MCU is arranged on the measurement and control main board, a first interference transceiving circuit, a second interference transceiving circuit and a third interference transceiving circuit are arranged on the measurement and control main board correspondingly to the first antenna, the second antenna and the third antenna respectively, the measurement and control unit further comprises a voltage acquisition module, the measurement and control MCU is connected with an MCU chip to be tested through the voltage acquisition module, and the voltage acquisition module is arranged on the test main board and used for monitoring the influence of interference signals on the MCU chip to be tested.
As a further scheme of the invention: the measurement and control unit comprises a measurement and control chip U3, and the model of the chip U3 is STM32F103ZET 6; the chip U3 is connected with a first interference transceiver circuit, a second interference transceiver circuit and a third interference transceiver circuit;
the first interference transceiving circuit comprises an interference transceiving chip U4, sequentially numbered capacitors C6-C10, an inductor L3, an inductor L4 and an antenna E2; one end of the capacitor C6 is connected with one end of the inductor L3 and one end of the capacitor C8; the other end of the capacitor C6 is connected with the RF _ N pin of U4; one end of the capacitor C7 is connected with one end of the inductor L4 and one end of the capacitor C9; the other end of the capacitor C7 is connected with the RF _ P pin of U4; the other ends of the inductor L3 and the capacitor C9 are respectively grounded; the other end of the capacitor C8 is connected with the other end of the inductor L4 and one end of the capacitor C10; the other end of the capacitor C10 is connected with an antenna E2; the RXD pin of U4 is connected with the PA9 pin of U3; the TXD pin of U4 is connected with the PA10 pin of U3; the model number of U4 is CC2530F 256;
the second interference transceiving circuit comprises an interference transceiving chip U5, sequentially numbered capacitors C11-C15, an inductor L5, an inductor L6 and an antenna E3; one end of the capacitor C11 is connected with one end of the inductor L5 and one end of the capacitor C13; the other end of the capacitor C11 is connected with the RF _ N pin of U5; one end of the capacitor C12 is connected with one end of the inductor L6 and one end of the capacitor C14; the other end of the capacitor C12 is connected with the RF _ P pin of U5; the other ends of the inductor L5 and the capacitor C14 are respectively grounded; the other end of the capacitor C13 is connected with the other end of the inductor L6 and one end of the capacitor C15; the other end of the capacitor C15 is connected with an antenna E3; the RXD pin of U5 is connected with the PB10 pin of U3; the TXD pin of U5 is connected with the PB11 pin of U3; the model number of U5 is CC2530F 256;
the third interference transceiving circuit comprises an interference transceiving chip U6, sequentially numbered capacitors C16-C20, an inductor L7, an inductor L8 and an antenna E4; one end of the capacitor C16 is connected with one end of the inductor L7 and one end of the capacitor C18; the other end of the capacitor C16 is connected with the RF _ N pin of U6; one end of the capacitor C17 is connected with one end of the inductor L8 and one end of the capacitor C19; the other end of the capacitor C17 is connected with the RF _ P pin of U6; the other ends of the inductor L7 and the capacitor C19 are respectively grounded; the other end of the capacitor C18 is connected with the other end of the inductor L8 and one end of the capacitor C20; the other end of the capacitor C20 is connected with an antenna E4; the RXD pin of U6 is connected with the PC10 pin of U3; the TXD pin of U6 is connected with the PC11 pin of U3; the model number of U6 is CC2530F 256;
the voltage acquisition module comprises an operational amplifier P1 and resistors R1 to R3 which are numbered sequentially; one end of the resistor R1 is connected with a PA7 pin of the U1, and the other end of the resistor R1 is connected with one end of the resistor R2 and the same-direction end of the P1; the other end of the resistor R2 is grounded; one end of the resistor R3 is connected with the reverse end of the P1, and the other end is connected with the output end of the P1; v + of P1 is terminated by +12V voltage; the V-terminus of P1 is low; the output end of the P1 is connected with the PA6 pin of the U3; wherein the model of P1 is LM 358.
As a further scheme of the invention: the peripheral circuit is a signal transmitting circuit, the signal transmitting circuit is arranged on the other side of the test mainboard and is isolated from the integrated electromagnetic compatibility test unit, and a shielding cover is arranged outside the signal transmitting circuit to realize signal isolation and avoid interference with electromagnetic compatibility detection of the MCU chip to be tested.
As a further scheme of the invention: the signal transmitting circuit comprises a signal transmitting chip U2, sequentially numbered capacitors C1-C5, an inductor L1, an inductor L2 and an antenna E1; one end of the capacitor C1 is connected with one end of the inductor L1 and one end of the capacitor C3; the other end of the capacitor C1 is connected with the RF _ N pin of U2; one end of the capacitor C2 is connected with one end of the inductor L2 and one end of the capacitor C4; the other end of the capacitor C2 is connected with the RF _ P pin of U2; the other ends of the inductor L1 and the capacitor C4 are respectively grounded; the other end of the capacitor C3 is connected with the other end of the inductor L2 and one end of the capacitor C5; the other end of the capacitor C5 is connected with an antenna E1; the RXD pin of U2 is connected with the PA9 pin of U1; the TXD pin of U2 is connected with the PA10 pin of U1; the model number of U2 is CC2530F 256.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention provides an MCU chip electromagnetic compatibility test circuit, the structure is set up ingeniously and arrange rationally, the invention; during operation, the electromagnetic compatibility test unit for inspecting the distance variable carries out electromagnetic compatibility tests with different distances on the MCU chip to be tested, the safe distance of the electromagnetic compatibility of the MCU chip to be tested is tested, in addition, the electromagnetic compatibility test unit of the integrated type carries out radiation test and anti-interference test on the MCU chip, and the test efficiency is improved.
2. The invention further designs an integrated electromagnetic compatibility test unit which comprises an antenna unit and a measurement and control unit, wherein the antenna unit comprises at least two test antennas, the distances between the test antennas and the MCU chip to be tested are increased in an equidifferent mode, and interference transceiving circuits connected with the test antennas are respectively arranged in the measurement and control unit corresponding to test wires; when the device works, the interference transceiving circuit is used for generating interference signals to interfere the MCU chip to be tested which normally works, the influence on the MCU chip to be tested is monitored, or the interference transceiving circuit is used for receiving electromagnetic radiation generated by the MCU chip to be tested which normally works, and the electromagnetic radiation value is analyzed and calculated;
3. the test system is characterized in that a voltage acquisition module is further designed, the measurement and control MCU is connected with the MCU chip to be tested through the voltage acquisition module, the voltage acquisition module is arranged on the test mainboard, and the voltage acquisition module is used for monitoring the influence of interference signals on the MCU chip to be tested.
4. The peripheral circuit is further designed to be a signal transmitting circuit, the signal transmitting circuit is arranged on the other side of the test mainboard and is isolated from the integrated electromagnetic compatibility test unit through signals, and the shielding cover is arranged outside the signal transmitting circuit, so that signal isolation can be realized, and the electromagnetic compatibility detection of the MCU chip to be tested can be prevented from being interfered.
Drawings
FIG. 1 is a block diagram of a control system of an MCU chip electromagnetic compatibility test circuit.
Fig. 2 is a schematic diagram of an MCU chip electromagnetic compatibility test circuit.
In the figure: 100. testing the main board; 101. the MCU chip to be tested; 102. a peripheral circuit; 103. a first antenna; 104. a second antenna; 105. a third antenna; 106. a measurement and control main board; 107. a measurement and control MCU; 108. a first interference transceiver circuit; 109. a second interference transceiver circuit; 110. a third interference transceiver circuit; 111. and a voltage acquisition module.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention; the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, as they may be fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Referring to fig. 1-2, an MCU chip electromagnetic compatibility test circuit includes a test unit for testing an MCU chip 101U1 to be tested; the testing unit comprises a testing main board 100, a fixed mounting position of the MCU chip 101 to be tested is arranged on the testing main board 100, the MCU chip 101 to be tested is mounted on the fixed mounting position of the MCU chip 101 to be tested, a peripheral circuit 102 connected with the MCU chip 101 to be tested is arranged on the testing main board 100, and the testing main board 100 is provided with an integrated electromagnetic compatibility testing unit for inspecting distance variable corresponding to the MCU chip 101 to be tested; the integrated electromagnetic compatibility test unit comprises an antenna unit and a measurement and control unit, wherein the antenna unit comprises at least two test antennas, the distance equal difference between each test antenna and the MCU chip 101 to be tested is increased in an equal difference mode, and interference receiving and transmitting circuits connected with the test antennas are arranged in the measurement and control unit corresponding to test wires respectively.
In this embodiment, the antenna unit is provided with a first antenna 103, a second antenna 104 and a third antenna 105, and distances between the first antenna 103, the second antenna 104 and the third antenna 105 and the MCU chip 101 to be tested are increased by taking a tolerance as a distance value between the first antenna 103 and the MCU chip 101 to be tested; the first antenna 103, the second antenna 104, the third antenna 105 and the MCU chip 101 to be tested are arranged along a straight line on the test motherboard 100.
The measurement and control unit comprises a measurement and control main board 106, a measurement and control MCU107 is arranged on the measurement and control main board 106, a first interference transceiver circuit 108, a second interference transceiver circuit 109 and a third interference transceiver circuit 110 are respectively arranged on the measurement and control main board 106 corresponding to the first antenna 103, the second antenna 104 and the third antenna 105, the measurement and control unit further comprises a voltage acquisition module 111, the measurement and control MCU107 is connected with the MCU chip 101 to be tested through the voltage acquisition module 111, and the voltage acquisition module 111 is arranged on the test main board 100.
The measurement and control unit in the embodiment comprises a measurement and control chip U3, wherein the model of the chip U3 is STM32F103ZET 6; the chip U3 is connected with a first interference transceiver circuit 108, a second interference transceiver circuit 109 and a third interference transceiver circuit 110; the first interference transceiver circuit 108 comprises an interference transceiver chip U4, sequentially numbered capacitors C6-C10, an inductor L3, an inductor L4 and an antenna E2; one end of the capacitor C6 is connected with one end of the inductor L3 and one end of the capacitor C8; the other end of the capacitor C6 is connected with the RF _ N pin of U4; one end of the capacitor C7 is connected with one end of the inductor L4 and one end of the capacitor C9; the other end of the capacitor C7 is connected with the RF _ P pin of U4; the other ends of the inductor L3 and the capacitor C9 are respectively grounded; the other end of the capacitor C8 is connected with the other end of the inductor L4 and one end of the capacitor C10; the other end of the capacitor C10 is connected with an antenna E2; the RXD pin of U4 is connected with the PA9 pin of U3; the TXD pin of U4 is connected with the PA10 pin of U3; the model number of U4 is CC2530F 256;
the second interference transceiver circuit 109 comprises an interference transceiver chip U5, sequentially numbered capacitors C11 to C15, an inductor L5, an inductor L6 and an antenna E3; one end of the capacitor C11 is connected with one end of the inductor L5 and one end of the capacitor C13; the other end of the capacitor C11 is connected with the RF _ N pin of U5; one end of the capacitor C12 is connected with one end of the inductor L6 and one end of the capacitor C14; the other end of the capacitor C12 is connected with the RF _ P pin of U5; the other ends of the inductor L5 and the capacitor C14 are respectively grounded; the other end of the capacitor C13 is connected with the other end of the inductor L6 and one end of the capacitor C15; the other end of the capacitor C15 is connected with an antenna E3; the RXD pin of U5 is connected with the PB10 pin of U3; the TXD pin of U5 is connected with the PB11 pin of U3; the model number of U5 is CC2530F 256;
the third interference transceiver circuit 110 comprises an interference transceiver chip U6, sequentially numbered capacitors C16 to C20, an inductor L7, an inductor L8 and an antenna E4; one end of the capacitor C16 is connected with one end of the inductor L7 and one end of the capacitor C18; the other end of the capacitor C16 is connected with the RF _ N pin of U6; one end of the capacitor C17 is connected with one end of the inductor L8 and one end of the capacitor C19; the other end of the capacitor C17 is connected with the RF _ P pin of U6; the other ends of the inductor L7 and the capacitor C19 are respectively grounded; the other end of the capacitor C18 is connected with the other end of the inductor L8 and one end of the capacitor C20; the other end of the capacitor C20 is connected with an antenna E4; the RXD pin of U6 is connected with the PC10 pin of U3; the TXD pin of U6 is connected with the PC11 pin of U3; the model number of U6 is CC2530F 256;
the voltage acquisition module 111 comprises an operational amplifier P1 and resistors R1 to R3 which are numbered sequentially; one end of the resistor R1 is connected with a PA7 pin of the U1, and the other end of the resistor R1 is connected with one end of the resistor R2 and the same-direction end of the P1; the other end of the resistor R2 is grounded; one end of the resistor R3 is connected with the reverse end of the P1, and the other end is connected with the output end of the P1; v + of P1 is terminated by +12V voltage; the V-terminus of P1 is low; the output end of the P1 is connected with the PA6 pin of the U3; wherein the model of P1 is LM 358.
In this embodiment, the peripheral circuit 102 is a signal transmitting circuit, and the signal transmitting circuit is disposed at the other side of the test motherboard 100 and is isolated from the integrated electromagnetic compatibility test unit; the signal transmitting circuit comprises a signal transmitting chip U2, sequentially numbered capacitors C1-C5, an inductor L1, an inductor L2 and an antenna E1; one end of the capacitor C1 is connected with one end of the inductor L1 and one end of the capacitor C3; the other end of the capacitor C1 is connected with the RF _ N pin of U2; one end of the capacitor C2 is connected with one end of the inductor L2 and one end of the capacitor C4; the other end of the capacitor C2 is connected with the RF _ P pin of U2; the other ends of the inductor L1 and the capacitor C4 are respectively grounded; the other end of the capacitor C3 is connected with the other end of the inductor L2 and one end of the capacitor C5; the other end of the capacitor C5 is connected with an antenna E1; the RXD pin of U2 is connected with the PA9 pin of U1; the TXD pin of U2 is connected with the PA10 pin of U1; the model number of U2 is CC2530F 256.
The working principle of the invention is as follows: the invention provides an MCU chip electromagnetic compatibility test circuit, the structure is set up ingeniously and arrange rationally, the invention; during operation, the electromagnetic compatibility test unit for inspecting the distance variable carries out electromagnetic compatibility tests with different distances on the MCU chip to be tested, the safe distance of the electromagnetic compatibility of the MCU chip to be tested is tested, in addition, the electromagnetic compatibility test unit of the integrated type carries out radiation test and anti-interference test on the MCU chip, and the test efficiency is improved. The invention further designs an integrated electromagnetic compatibility test unit which comprises an antenna unit and a measurement and control unit, wherein the antenna unit comprises at least two test antennas, the distances between the test antennas and the MCU chip to be tested are increased in an equidifferent mode, and interference transceiving circuits connected with the test antennas are respectively arranged in the measurement and control unit corresponding to test wires; when the device works, the interference transceiving circuit is used for generating interference signals to interfere the MCU chip to be tested which normally works, the influence on the MCU chip to be tested is monitored, or the interference transceiving circuit is used for receiving electromagnetic radiation generated by the MCU chip to be tested which normally works, and the electromagnetic radiation value is analyzed and calculated; the test system is characterized in that a voltage acquisition module is further designed, the measurement and control MCU is connected with the MCU chip to be tested through the voltage acquisition module, the voltage acquisition module is arranged on the test mainboard, and the voltage acquisition module is used for monitoring the influence of interference signals on the MCU chip to be tested. The peripheral circuit is further designed to be a signal transmitting circuit, the signal transmitting circuit is arranged on the other side of the test mainboard and is isolated from the integrated electromagnetic compatibility test unit through signals, and the shielding cover is arranged outside the signal transmitting circuit, so that signal isolation can be realized, and the electromagnetic compatibility detection of the MCU chip to be tested can be prevented from being interfered.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (8)
1. The MCU chip electromagnetic compatibility test circuit is characterized by comprising a test unit, a test unit and a test unit, wherein the test unit is used for testing a U1 of an MCU chip (101) to be tested; the test unit comprises a test main board (100), wherein a fixed mounting position of the MCU chip (101) to be tested is arranged on the test main board (100), the MCU chip (101) to be tested is mounted on the fixed mounting position of the MCU chip (101) to be tested, a peripheral circuit (102) connected with the MCU chip (101) to be tested is arranged on the test main board (100), and the test main board (100) is provided with an integrated electromagnetic compatibility test unit for inspecting distance variables corresponding to the MCU chip (101) to be tested.
2. The MCU chip electromagnetic compatibility test circuit of claim 1, wherein the integrated electromagnetic compatibility test unit comprises an antenna unit and a measurement and control unit, the antenna unit comprises at least two test antennas, the distances between the test antennas and the MCU chip (101) to be tested are increased in an equidifferent manner, and interference transceiving circuits connected with the test antennas are respectively arranged in the measurement and control unit corresponding to test wires.
3. The MCU chip electromagnetic compatibility test circuit according to claim 2, wherein a first antenna (103), a second antenna (104) and a third antenna (105) are arranged in the antenna unit, and distances between the first antenna (103), the second antenna (104) and the third antenna (105) and the MCU chip (101) to be tested are increased by taking a tolerance as a distance value between the first antenna (103) and the MCU chip (101) to be tested.
4. An MCU chip electromagnetic compatibility test circuit according to claim 3, characterized in that the first antenna (103), the second antenna (104) and the third antenna (105) are arranged along a straight line with the MCU chip (101) to be tested on the test motherboard (100).
5. The MCU chip electromagnetic compatibility test circuit of claim 4, characterized in that, observe and control the unit and include observing and controlling mainboard (106), be equipped with observing and controlling MCU (107) on observing and controlling mainboard (106), it is equipped with first interference transceiver circuit (108), second interference transceiver circuit (109) and third interference transceiver circuit (110) respectively to correspond first antenna (103), second antenna (104) and third antenna (105) on observing and controlling mainboard (106), observe and control the unit and still include voltage acquisition module (111), observe and control MCU (107) and be connected with MCU chip (101) that awaits measuring through voltage acquisition module (111), voltage acquisition module (111) sets up on test mainboard (100).
6. The MCU chip electromagnetic compatibility test circuit according to claim 5, wherein the measurement and control unit comprises a measurement and control chip U3, the model of the chip U3 is STM32F103ZET 6; a first interference transceiver circuit (108), a second interference transceiver circuit (109) and a third interference transceiver circuit (110) are connected to the chip U3;
the first interference transceiving circuit (108) comprises an interference transceiving chip U4, sequentially numbered capacitors C6-C10, an inductor L3, an inductor L4 and an antenna E2; one end of the capacitor C6 is connected with one end of the inductor L3 and one end of the capacitor C8; the other end of the capacitor C6 is connected with the RF _ N pin of U4; one end of the capacitor C7 is connected with one end of the inductor L4 and one end of the capacitor C9; the other end of the capacitor C7 is connected with the RF _ P pin of U4; the other ends of the inductor L3 and the capacitor C9 are respectively grounded; the other end of the capacitor C8 is connected with the other end of the inductor L4 and one end of the capacitor C10; the other end of the capacitor C10 is connected with an antenna E2; the RXD pin of U4 is connected with the PA9 pin of U3; the TXD pin of U4 is connected with the PA10 pin of U3; the model number of U4 is CC2530F 256;
the second interference transceiving circuit (109) comprises an interference transceiving chip U5, sequentially numbered capacitors C11-C15, an inductor L5, an inductor L6 and an antenna E3; one end of the capacitor C11 is connected with one end of the inductor L5 and one end of the capacitor C13; the other end of the capacitor C11 is connected with the RF _ N pin of U5; one end of the capacitor C12 is connected with one end of the inductor L6 and one end of the capacitor C14; the other end of the capacitor C12 is connected with the RF _ P pin of U5; the other ends of the inductor L5 and the capacitor C14 are respectively grounded; the other end of the capacitor C13 is connected with the other end of the inductor L6 and one end of the capacitor C15; the other end of the capacitor C15 is connected with an antenna E3; the RXD pin of U5 is connected with the PB10 pin of U3; the TXD pin of U5 is connected with the PB11 pin of U3; the model number of U5 is CC2530F 256;
the third interference transceiving circuit (110) comprises an interference transceiving chip U6, sequentially numbered capacitors C16-C20, an inductor L7, an inductor L8 and an antenna E4; one end of the capacitor C16 is connected with one end of the inductor L7 and one end of the capacitor C18; the other end of the capacitor C16 is connected with the RF _ N pin of U6; one end of the capacitor C17 is connected with one end of the inductor L8 and one end of the capacitor C19; the other end of the capacitor C17 is connected with the RF _ P pin of U6; the other ends of the inductor L7 and the capacitor C19 are respectively grounded; the other end of the capacitor C18 is connected with the other end of the inductor L8 and one end of the capacitor C20; the other end of the capacitor C20 is connected with an antenna E4; the RXD pin of U6 is connected with the PC10 pin of U3; the TXD pin of U6 is connected with the PC11 pin of U3; the model number of U6 is CC2530F 256;
the voltage acquisition module (111) comprises an operational amplifier P1 and sequentially numbered resistors R1-R3; one end of the resistor R1 is connected with a PA7 pin of the U1, and the other end of the resistor R1 is connected with one end of the resistor R2 and the same-direction end of the P1; the other end of the resistor R2 is grounded; one end of the resistor R3 is connected with the reverse end of the P1, and the other end is connected with the output end of the P1; v + of P1 is terminated by +12V voltage; the V-terminus of P1 is low; the output end of the P1 is connected with the PA6 pin of the U3; wherein the model of P1 is LM 358.
7. An MCU chip electromagnetic compatibility test circuit according to any of claims 1-6 characterized in that the peripheral circuit (102) is a signal transmitting circuit which is arranged at the other side of the test motherboard (100) and is isolated from the integrated electromagnetic compatibility test unit signal.
8. The MCU chip electromagnetic compatibility test circuit of claim 7, wherein the signal transmitting circuit comprises a signal transmitting chip U2, sequentially numbered capacitors C1-C5, an inductor L1, an inductor L2 and an antenna E1; one end of the capacitor C1 is connected with one end of the inductor L1 and one end of the capacitor C3; the other end of the capacitor C1 is connected with the RF _ N pin of U2; one end of the capacitor C2 is connected with one end of the inductor L2 and one end of the capacitor C4; the other end of the capacitor C2 is connected with the RF _ P pin of U2; the other ends of the inductor L1 and the capacitor C4 are respectively grounded; the other end of the capacitor C3 is connected with the other end of the inductor L2 and one end of the capacitor C5; the other end of the capacitor C5 is connected with an antenna E1; the RXD pin of U2 is connected with the PA9 pin of U1; the TXD pin of U2 is connected with the PA10 pin of U1; the model number of U2 is CC2530F 256.
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| CN114397562A (en) * | 2022-03-24 | 2022-04-26 | 北京智芯微电子科技有限公司 | Automatic test method and system for EMC (electro magnetic compatibility) immunity of chip |
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