CN1126411A - Apparatus for parallel encoding/decoding of digital video signals - Google Patents
Apparatus for parallel encoding/decoding of digital video signals Download PDFInfo
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- CN1126411A CN1126411A CN 95101116 CN95101116A CN1126411A CN 1126411 A CN1126411 A CN 1126411A CN 95101116 CN95101116 CN 95101116 CN 95101116 A CN95101116 A CN 95101116A CN 1126411 A CN1126411 A CN 1126411A
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Abstract
The parallel encoder/decoder for digital video signals comprises encoder and decoder. Said encoder is composed of controller for counting lines of each frame, switch block for deviding video frame into more subframes, more FIFO buffers for storing more subframes, more encoding units for compressing subframes and frame formatter. Said decoder is composed of detector for detecting slice start code and generating slice start detection signal, controller for counting slice start code and generating control signal, switch block for dividing video frame into more subframes, more FIFO buffer for storing subframes, more decoding units for reproducing video image signals of subframes respectively, and frame formatter.
Description
The present invention relates to video imaging system; More specifically, relate to a kind of improved encoding and decoding of video device that to carry out parallel processing.
In such as various electronics/electrical applications such as high definition TV and video-telephone systems, picture intelligence may send with digitized forms.When picture intelligence was represented with digitized forms, considerable amount of digital data must appear.Yet,,, must use an image signal coding device to compress this considerable amount of digital data therefore for by wherein sending picture intelligence because the available frequency bandwidth of traditional transmitting channel is limited.
Thereby most of image signal coding devices adopt and are based upon utilization or reduce the space intrinsic in the input image signal and/or the notional various compress techniques (or coding method) of time redundancy.
In various video compression technologies, the so-called mixed coding technology of time and space compress technique being combined with the statistical coding technology is known to be the most effective.
The quantification and the VLC (variable length code) of the DPCM of most of mixed coding technologies employing motion compensation (sign indicating number modulation in the difference arteries and veins), two-dimensional dct (discrete cosine transform), DCT coefficient.Motion compensation DPCM is the processing of determining the motion of target in present frame and former frame thereof, and represents the differential signal of the difference between present frame and the prediction thereof with generation according to the motion stream prediction present frame of this target.This method is in " the fixing and adaptive predictor of hybrid predicting/transition coding " (ieee communication journal, COM-33, No. 12 (1985 December)) such as Staffan Ericsson; And describe to some extent in " the interframe encode scheme of the motion compensation of television image " (ieee communication journal, COM-30, No. 1 (January nineteen eighty-two)) of Ninomiya and Ohtsuka.
Reduce or eliminate two-dimensional dct, will convert one group of transform coefficient data to such as a digital image data of 8 * 8 pixels such as the spatial redundancy between the pattern datas such as DPCM data of motion compensation.This technology is described in " scene adaptive coding device " (ieee communication journal, COM-32, No. 3 (in March, 1984)) of Chen and Pratt to some extent.By handling these transform coefficient data, can compress effectively and want data quantity transmitted with a quantizer, zigzag scanning device and VLC.
Especially in the DPCM of motion compensation, current frame data is according to a kind of moltion estimation between the frame of current and front, the data prediction from the frame of front.The motion of this estimation can be described with the two-dimensional motion vector of representing the displacement of pixel between former frame and the present frame.
For with above-mentioned technique compresses picture intelligence, it is necessary using the processor that can carry out high speed processing, and this adopts parallel processing technique to finish usually.Usually, in having the encoding image signal/decoding device of parallel processing capability, a video image frame district is divided into a plurality of subframes, and handles the pictorial data in the video image frame district on basis of sub-frames one by one.
Yet, in order to determine a motion vector of a search block in the present frame, in the search block of present frame and be included in to carry out similarly between each piece in a plurality of equal-sized candidate blocks in the field of search bigger usually in the former frame and calculate, the size of search block wherein is usually in the scope of 8 * 8 and 32 * 32 pixels.Therefore, the field of search that comprises the boundary member of any subframe comprises the boundary member in abutting connection with subframe simultaneously.Thereby the performed moltion estimation of each encoder need exceed the storage access on the border of the former frame memory that is associated with this specific encoder, or has the accumulator system of sharing of multiple random access capability.
Therefore, a main purpose of the present invention can be carried out the improved encoding and decoding of video device that parallel processing need not to use the storage access on the border that exceeds the former frame memory that is associated with specific encoder/decoder or has the shared storage system of multiple random access capability for providing a kind of.
According to one aspect of the present invention, providing a kind of is used for from the device for the compressed format encodings input digital video signal that transmits usefulness, input digital video signal wherein comprises a plurality of video requency frame datas, it is capable that each video requency frame data has some pictures, this device comprises: control device, be used for counting each picture line number of a plurality of video requency frame datas, and the picture line number of response count generates a control signal; Be used to respond this control signal, video requency frame data be divided into the device of a plurality of subframes; A plurality of FIFO (first in first out) buffer is used to store video requency frame data separately; A plurality of encoders are used for the compressed video frame data, in a plurality of subframes of each encoder compresses one; And the device that is used to connect compressed video requency frame data.
Moreover, according to another aspect of the present invention, a kind of original video picture intelligence of regeneration that is is disclosed, decoding is with the device of the encoding digital video signal of the bit stream format of coding, encoding digital video signal wherein comprises a plurality of video requency frame datas, in these a plurality of video requency frame datas each has the some initial codes of starting point of wherein each of expression, and this device comprises: be used for from encoding digital video signal detection lug initial code and generate the device of an initial detection signal of sheet; Control device is used for responding the initial detection signal of this sheet and counts the number of the sheet initial code of the bit stream of encoding, and is used to respond control signal of counting generation of sheet initial code; Be used to respond the device that this control signal is divided into video requency frame data a plurality of subframes; A plurality of FIFO buffers are used to store video requency frame data separately; Regenerate in a plurality of subframes one of a plurality of decoders, the original video picture intelligence that is used to regenerate, each decoder; And the device that is used to connect the original video picture intelligence of regeneration.
From the description of the following preferred embodiment that provides in conjunction with the accompanying drawings, above-mentioned and other purpose of the present invention and feature will be conspicuous.
Figure 1A is schematically showing of a video image frame district;
Figure 1B illustrates the figure in a video image frame district that separates;
Fig. 2 represents to comprise the block diagram of the creative code device of a plurality of encoders;
The more detailed block diagram of one of same-code device shown in Fig. 3 presentation graphs 2;
Fig. 4 describes to comprise the block diagram of the creative decoding device of a plurality of decoders; And
Fig. 5 describes the more detailed block diagram of one of same decoder shown in Fig. 4.
The invention provides the communication of high definition TV (HDTV) signal from a transmitter site to many receivers.On the transmitter of " encoder " of communication link end, the digital video signal of the frame in succession of a television image is resolved into subframe for a plurality of processor processing.Each processor comprises an encoder that is exclusively used in coding from the video data of a specific subframe.
A video image frame district 10 has been shown among Figure 1A.It is capable that the entire frame district has the horizontal picture of M bar, and each picture is capable to comprise N pixel.For example, a single HDTV frame comprises that 960 pictures are capable, and each picture is capable to comprise 1408 pixels.In other words, a single HDTV frame comprises 60, and every to comprise 16 horizontal pictures capable.
According to the present invention, video image frame district is divided into a plurality of subframes, for example, frame 12,14,16,18 has been shown in Figure 1B.
In order to handle these subframes, distributing to processor of each subframe, to be used for compressed video frame be the numerical data on boundary with this subframe.Data redundancy between the frame of video of employing moltion estimation/compensation technique current video frame of reduction and one or more its fronts.Be distributed in a plurality of processors by processing, just can adopt the transmission that reaches the HDTV signal such as substantially the same encoder in the transmission of normal tv signals such as NTSC a video image frame district.
Referring to Fig. 2, wherein show a preferred embodiment that is used for according to the parallel encoding device of video image signal of the present invention.
As shown in Figure 2, via input 20 a pending input digital video signal is input to a control unit 30 and a switch block 40.On the basis of block-by-block, from an input store (not shown), read the digital video signal of input, in this memory, store as being each frame video signal of piece in succession of the pixel data of based process for block-by-block.The block size of input digital video signal is usually in the scope between 8 * 8 and 32 * 32 pixels.Input digital video signal comprises a plurality of video requency frame datas, and it is capable and occupy a video image frame district that each video requency frame data comprises some pictures.Picture line number in the control unit 30 counting video requency frame datas, and the counting of response screen row generate a control signal to switch block 40.When the capable counting of picture reaches a predetermined value (for example 24), control unit 30 just generates a control signal of alternately switching input digital video signal between I1, I2, I3, I4, each frame with the digital video signal that enters is divided into a plurality of subframes whereby, and they are stored in a plurality of first in first out (FIFO) buffer 52,54,56,58.The FIFO buffer outputs to sub-frame data in one corresponding in the encoder 62,64,66,68, and these encoders are identical basically.Respectively this encoder is exclusively used in the video image data that processing is the boundary with a specific subframe.More detailed description about encoder provides below with reference to Fig. 3.The treated sub-frame data of own coding device 62,64,66,68 offers a frame formatter 70 in the future, and they are combined into the frame data through coding.Frame data with coding offer a transmitter (not shown) for its transmission then.
Referring to Fig. 3, wherein described one of identical encoder, the more detailed block diagram of the encoder 62 shown in Fig. 2.To present to a subtracter 202 and a motion estimator 210 as current sub-frame data from the sub-frame data of FIFO buffer 52.From the search block of current sub-frame data, deduct predictor frame data 203 from motion compensator 222 at subtracter 202 places; With the data that obtain, promptly the difference pixel data divides and tasks a discrete cosine transform (DCT) circuit 205, therein a difference pixel data is encoded into one group of conversion coefficient.On a quantizer (Q) 206, these quantization of transform coefficients are become one group of quantization DCT coefficient then.After this, send these quantization DCT coefficients via two signal path; Article one, be directed to a scanner 207 then to a variable length code (VLD) circuit 208, use these quantization DCT coefficients of a kind of assembly coding therein, thereby the sub-frame data of VLC coding is offered a multiplex electronics (MUX) 230 such as haul distance and variable length code; Another then to an inverse discrete cosine transform (IDCT) circuit 214, converts quantization DCT coefficient to re-quantization and inverse transformation the difference pixel data of reconstruct then to an inverse quantizer (IQ) 213 respectively therein.The difference pixel data of portfolio restructuring reaches the prediction data from motion compensator 222 on an adder 215, with the current sub-frame data of the reconstruct that a frame memory 221 to be written is provided.
On motion estimator 210, handle to determine motion vector to current sub-frame data and from the last sub-frame data 218 of the reconstruct of frame memory 221.Motion vector 219 is acted on the motion compensator 222, therein on the basis of block-by-block from frame memory 221 the retrieval prediction data corresponding with motion vector 219, be the candidate blocks data, and provide it to subtracter 202 and further processing of adder 215 confessions.Also motion vector 219 is acted on the VLC circuit 208 and with VLC and encoded.Present to multiplex electronics 230 and be transferred to the frame formatter 70 shown in Fig. 2 with the sub-frame data of VLC coding and from the motion vector of VLC circuit 208.
Particularly, in motion estimator 210, in order to determine the motion vector of a search block in the current subframe, between each of a plurality of equal-sized candidate blocks in the search block of current subframe and a bigger usually field of search that is included in the last subframe, carry out similitude calculating.According to the present invention, only determine motion vector 219 with moltion estimation on the field of search in the subframe of respectively separating.
Referring to Fig. 4, wherein show a embodiment according to the device of the video image signal that is used for the parallel decoding variable length code of the present invention.
An encoding digital video signal that receives from the code device of Fig. 2 is input to a sheet initial code (SSC) detector 80 via an input 400.Encoding digital video signal comprises a plurality of video requency frame datas, each the described video requency frame data that wherein occupies a video image frame district has conversion coefficient, motion vector and some SSC of variable length code, and each SSC represents to be included in the starting point of a slice in the coding stream.SSC detector 80 detection lug initial code and control unit 90 generated the initial detection signal of sheet from encoding digital video signal, this signal is used for controlling a switch block 100 and a multiplex electronics 120.The initial detection signal of sheet that control unit 90 response SSC detectors 80 provide, the number of counting SSC.When the counting of SSC reaches a predetermined value (such as 15), control unit 90 just generates one first control signal that is used for alternately switching from the encoding digital video signal of SSC detector 80 between D1, D2, D3, D4, each frame with the coding image signal that enters is divided into a plurality of subframes whereby, and they are stored in a plurality of FIFO buffers 102,104,106,108.The FIFO buffer outputs to one corresponding in each identical mutually decoder 112,114,116,118 with sub-frame data.Each decoder processes is the video image data on boundary with the subframe of correspondence.In other words, decoder 112 will be handled the coded sub-frame data of the encoder 62 shown in Fig. 2.Similarly, will to handle the subframe of being handled by encoder 64,66,68 respectively be the video image data on boundary to decoder 114,116,118.The more detailed description of relevant decoder provides below with reference to Fig. 5.Respectively this decoder processing that to be exclusively used in a specific subframe be the video image data on boundary.Decoded sub-frame data from decoder acts on the frame formatter 120, and is combined into a single data flow of the original video picture intelligence that shows on such as a display unit (not shown) of indicating there.
Referring to Fig. 5, wherein show one of identical decoder, the more detailed block diagram of the decoder 112 shown in Fig. 4.The identical components and parts of decoder 112,114,116,118 usefulness shown in Fig. 4 are made, and each components and parts is served identical functions.
As shown in Figure 5, the video image data that is the boundary with a specific subframe offers length-changeable decoding (VLC) circuit 301 by FIFO buffer 102 (being illustrated among Fig. 4).The conversion coefficient and the motion vector of this group variable length code of VLD circuit 301 decodings are delivered to a contrary zigzag scanning device 303 with transform coefficient data, and motion vector data is delivered to a motion compensator 302.VLD circuit 301 is a look-up table basically: promptly, provide a plurality of code characters to define corresponding relation between variable-length codes and their run-length codes or the motion vector in VLD circuit 301.
In contrary zigzag scanning device 303, the reconstruct quantization DCT coefficient is to provide an original block of quantization DCT coefficient.In an inverse quantizer (IQ) 304, convert a quantization DCT coefficient to one group of DCT coefficient, and it is fed to an inverse discrete cosine transform (IDCT) circuit 305, this group DCT transformation of coefficient is become one group of differential data between its corresponding piece in a current subframe and the last subframe.To deliver to an adder 306 from the differential data of IDCT305 then.
Simultaneously, will be fed to motion compensator 302 from the motion vector through length-changeable decoding of VLD circuit 301.Motion compensator 302 extract corresponding pixel data in the last subframe from be stored in a frame memory 307, and the pixel data that these are corresponding acts on the adder 306 according to this motion vector.The corresponding pixel data of from motion compensator 302, deriving with sue for peace in adder 306 from the pixel differences divided data of IDCT305, with the representative diagram image data of a given piece constituting current subframe, and write in the frame memory 307 and be transferred to the frame formatter 120 shown in Fig. 4.
Though just described the present invention, also can make spirit of the present invention and scope that other remodeling does not still break away from the following claims with changing to be proposed with respect to some preferred embodiment.
Claims (2)
1, a kind of device with the input digital video signal of compressed format encodings that is used to send, wherein this input digital video signal comprises a plurality of video requency frame datas, and it is capable that each video requency frame data has some pictures, and this device comprises:
Control device is used for counting the respectively capable number of picture of these a plurality of video requency frame datas, and response generates a control signal to the capable counting of these pictures;
Be used to respond this control signal, video requency frame data be divided into the device of a plurality of subframes;
A plurality of FIFO buffers are used to store video requency frame data separately;
A plurality of encoders are used for the compressed video frame data, in a plurality of subframes of each encoder compresses one; And
Be used to connect the device of the video requency frame data after the compression.
2, a kind of in order to regenerate an original video picture intelligence device of an encoding digital video signal of the bit stream format of decoding and coding, wherein this encoding digital video signal comprises a plurality of video requency frame datas, respectively these a plurality of video requency frame datas have the wherein sheet initial code of the starting point of each sheet of some expressions, and this device comprises:
Be used for from encoding digital video signal detection lug initial code and generate the device of an initial detection signal of sheet;
Control device is used to respond the initial detection signal of this sheet, counts the number of the sheet initial code in the coding stream, and is used to respond the counting to the sheet initial code, generates a control signal;
Be used to respond this control signal, video requency frame data be divided into the device of a plurality of subframes;
A plurality of FIFO buffers are used to store video requency frame data separately;
Regenerate in a plurality of subframes one of a plurality of decoders, the original video picture intelligence that is used to regenerate, each decoder;
Be used to connect the device of the original video picture intelligence of regeneration.
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| CN 95101116 CN1126411A (en) | 1995-01-06 | 1995-01-06 | Apparatus for parallel encoding/decoding of digital video signals |
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| CN 95101116 CN1126411A (en) | 1995-01-06 | 1995-01-06 | Apparatus for parallel encoding/decoding of digital video signals |
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| CN101065760B (en) * | 2003-12-11 | 2010-06-16 | 富可视公司 | System and method for processing image data |
| CN101014122B (en) * | 2006-01-30 | 2010-09-01 | 索尼株式会社 | Encoding/decoding apparatuses and method |
| US7920295B2 (en) | 2007-03-16 | 2011-04-05 | Seiko Epson Corporation | Image processing circuit, displaying apparatus, and printing apparatus |
| CN101765010B (en) * | 2008-12-25 | 2013-06-19 | 索尼株式会社 | Encoder, decoder, encoding method and decoding method |
| WO2013159587A1 (en) * | 2012-04-28 | 2013-10-31 | 华为技术有限公司 | Video signal processing method and photographic device |
| CN103684597A (en) * | 2013-11-19 | 2014-03-26 | 北京邮电大学 | FPGA-based visible light video communication system and method |
| CN104768021A (en) * | 2015-04-22 | 2015-07-08 | 四川正冠科技有限公司 | Ultra-low time delay H.264 coding method and coder |
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| CN111384962A (en) * | 2018-12-28 | 2020-07-07 | 上海寒武纪信息科技有限公司 | Data compression/decompression device and data compression method |
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| CN115499667A (en) * | 2022-11-17 | 2022-12-20 | 山东云海国创云计算装备产业创新中心有限公司 | Video processing method, device and equipment and readable storage medium |
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| CN101065760B (en) * | 2003-12-11 | 2010-06-16 | 富可视公司 | System and method for processing image data |
| CN101014122B (en) * | 2006-01-30 | 2010-09-01 | 索尼株式会社 | Encoding/decoding apparatuses and method |
| US7920295B2 (en) | 2007-03-16 | 2011-04-05 | Seiko Epson Corporation | Image processing circuit, displaying apparatus, and printing apparatus |
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| WO2013159587A1 (en) * | 2012-04-28 | 2013-10-31 | 华为技术有限公司 | Video signal processing method and photographic device |
| CN103684597A (en) * | 2013-11-19 | 2014-03-26 | 北京邮电大学 | FPGA-based visible light video communication system and method |
| CN104768021A (en) * | 2015-04-22 | 2015-07-08 | 四川正冠科技有限公司 | Ultra-low time delay H.264 coding method and coder |
| CN106210729A (en) * | 2015-05-06 | 2016-12-07 | 扬智科技股份有限公司 | Decoding video stream system and method for decoding video stream |
| CN111384962A (en) * | 2018-12-28 | 2020-07-07 | 上海寒武纪信息科技有限公司 | Data compression/decompression device and data compression method |
| CN111384963A (en) * | 2018-12-28 | 2020-07-07 | 上海寒武纪信息科技有限公司 | Data compression/decompression device and data decompression method |
| CN111384963B (en) * | 2018-12-28 | 2022-07-12 | 上海寒武纪信息科技有限公司 | Data compression/decompression device and data decompression method |
| CN111384962B (en) * | 2018-12-28 | 2022-08-09 | 上海寒武纪信息科技有限公司 | Data compression/decompression device and data compression method |
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