CN1126410A - Apparatus for parallel decoding of digital video signals - Google Patents
Apparatus for parallel decoding of digital video signals Download PDFInfo
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- CN1126410A CN1126410A CN 95101115 CN95101115A CN1126410A CN 1126410 A CN1126410 A CN 1126410A CN 95101115 CN95101115 CN 95101115 CN 95101115 A CN95101115 A CN 95101115A CN 1126410 A CN1126410 A CN 1126410A
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Abstract
The parallel decoder for decoding the encoded digital video signal without shared memory system is composed of detector for detecting the slice start code in the encoded digital video signal and generating slice start detection signal, controller for counting slice start codes of encoded bit stream and generating control signal according to the counts of the slice start code, switch part for dividing video frame into two subframes, two FIFO buffers for storing subframes, image processor for decompression, and frame fomatter for linking reproduced original video image signals.
Description
The present invention relates to video image system, particularly relate to and have the improved video image decoding device that compressed vedio data that two decode component are used for will importing is concurrently removed compression.
In the purposes of various electrical/electronics, as high definition TV and video-phone system, picture signal may require to send in digitized mode.When picture signal is expressed with digital form, a large amount of numerical datas certainly will to be had.Yet, because the common spendable frequency bandwidth of transmission channel is limited, pass through its transmitted image signal, be necessary to use image signal coding device, to compress a large amount of numerical datas.
Therefore, most of image signal coding devices adopt various compress techniques (perhaps coding method), it be based on to utilize or reduce in the picture signal of input on the intrinsic space and/or temporal redundancy.
In various video compression technologies, so-called mixed coding technology is known to be the most effective, and it combines with the compress technique space and statistical coding technology the time.
Most mixed coding technologies adopt motion compensation DPCM (differential pulse-code modulation), two-dimensional dct (discrete cosine transform), the quantification of DCT coefficient, and VLC (variable length code).Motion compensation DPCM is a process, and its determines target motion between present frame and its former frame, and predicts present frame so that produce the difference signal of representing difference between present frame and its predicted value according to the motion stream of target.The method is described in, for example, " the Fixed and Adaptive Predictors for Hybrid Predictive/Transform Coding " of Staffan Ericsson, IEEE Transactions on Communications, COM-33, NO.12 (December1985); And Ninomiya and Ohtsuka " A Motion Compensated Interframe CodingScheme for Television Pictures ", IEEE Transactions on Communications, COM-30, No.1 (January 1982).
Two-dimensional dct, it reduces or eliminates the spatial redundancy that resembles between this view data of motion compensation DPCM data, and with a code block DID, for example, one 8 * 8 pixel is transformed into a cover transform coefficient data.This technology be described in Chen and Pratt's " SceneAdaptive Coder ", IEEE Transactions on Communications, COM-32, NO.3 (March 1984).Through using quantizer, zigzag scanning device and VLC circuit to handle this transform coefficient data, the data volume that transmit can be effectively incompressible.
Particularly, in motion compensation DPCM, current frame data is on the basis of frame and the motion between the frame formerly before estimation, predicts from frame data formerly.The motion of this estimation can be described by having represented formerly between the frame and present frame the two-dimensional motion vector of the displacement of pixel.
For the technology with above narration is come compressing image signal, the processor that use can be carried out high speed processing becomes and is necessary that this adopts parallel processing technique to reach usually.Generally, in having the image signal decoding apparatus of parallel processing capability, a width of cloth video frame image zone is divided into several subframes, and the view data in the video frame image zone is that handle on the basis with frame one by one.
On the other hand, determine the motion vector of retrieval code block in the present frame, will do the retrieval code block of present frame and in general what formerly comprised in the frame be that similitude between each code block of several equidimensions candidate code block in the bigger retrieval district is calculated, wherein, the size of retrieval code block is typically between 8 * 8 and 32 * 32 pixels.Therefore, the retrieval district that has comprised the marginal portion of any one subframe also comprises the marginal portion of adjacent sub-frame.So the estimation of being carried out by each processor needs the shared file system of multichannel random access capability.
Primary and foremost purpose of the present invention provides a kind of improved video image decoding device, and it can carry out parallel processing, needn't use the shared file system of multichannel random access capability.
According to the present invention, a kind of device that the encoding digital video signal that coding stream is arranged is decoded is provided, be used to reappear the raw video image signal, wherein encoding digital video signal comprises a plurality of video requency frame datas, each video requency frame data has several representatives sheet initial code of the beginning of each sheet wherein, and described device comprises: detection lug initial code and produce the device of an initial detection signal of sheet from encoding digital video signal; Control device is used for according to the number counting of the initial detection signal of sheet to the sheet initial code of coding stream, and is used for producing control signal according to the number of the sheet initial code of counting; A device is used for responsive control signal, and video requency frame data is divided into two subframes; Two first in first out (FIFO) buffer is used to store the video requency frame data that is divided into; Image processing apparatus is used for the input data of coding are removed compression and reappeared original video signal; And the device that is used to connect the raw video image signal of reproduction.Image processing apparatus comprises two decoder component and a frame storage area, be used to reappear the raw video image signal, wherein each decoder component is reappeared each in two subframes, and storage area comprises two memory assemblies that are used to store the video requency frame data that is divided into; A memory assembly selection control is used for producing first and second and selects the signal and first and second address dates; And select control, be used for selecting signal to produce the pixel data that is stored in the corresponding memory assembly according to first and second.
Above and other purpose of the present invention and characteristics will be by describing preferred embodiment and become clearer below in conjunction with accompanying drawing, wherein:
Fig. 1 is the video frame image area schematic that is divided into two subframes;
Fig. 2 is the block diagram that comprises the decoding device of the present invention of view data division circuit and image processing apparatus;
Fig. 3 represents to receive the more detailed block diagram that is shown in the image processing apparatus of view data division circuit among Fig. 2; And
Fig. 4 A and 4B draw the sequential chart of each subframe processing order of expression.
The invention provides communication from county of emission to high definition TV (HDTV) signal that receives a group of planes.At the transmitter place that " encoder " of communication chain held, each successive frame data video signal of television image is divided into subframe so that handle with the multistep treatment device.The decoding device of being invented comprises two decoder component, wherein each video data from independent subframe that is used to decode.
Referring to Fig. 1, show the video frame image 10 that is divided into two subframes.All the frame district has M horizontal picture line, and each bar picture line contains N pixel.For example, a width of cloth HDTV frame comprises 960 picture lines, and each picture line has comprised 1408 pixels.In other words, a width of cloth HDTV frame comprises 60 sheets, and every comprises 16 horizontal picture lines.
According to the present invention, the video frame image district is divided into two subframes, for example, and subframe 13,16 as shown in Figure 1.
In order to handle this two subframes, processor is selected to each subframe makes the compressed numerical data that subframe limited in frame of video remove compression.In code device, use the motion estimation/compensation technology to reduce current video frame and one or several its superfluous She of the data between the frame of video formerly.
Referring to Fig. 2, represented the block diagram of the parallel image decoding device invented, it has comprised that view data divides circuit 30 and image processing apparatus 40.
View data is divided circuit 30 and is comprised that sheet initial code (SSC) detector 31, control unit 32, switch member 33 and two first in first out (FIFO) buffer 34,35 received image processing apparatus 40, and the numerical data that this circuit has been used for having compiled sign indicating number is divided into two subframes so that handle under the principle that subframe is handled one by one.Image processing apparatus 40 comprises two decoder component 50,60, each decoder component has length-changeable decoding (VLD) circuit 51,61, motion compensator 52,62, contrary zigzag scanning device 53,63, inverse quantizer (IQ) 54,64, inverse discrete cosine transform (IDCT) circuit 55,65, and adder 56,66, decoder component is connected with frame storage area 70 respectively, and compressed input digital data is removed compression.
As shown in Figure 2, the variable length code digital video signal that receives from the code device (not shown) is imported into SSC detector 31 by terminal 20.The digital video signal of having compiled sign indicating number comprises a plurality of video requency frame datas, each described video requency frame data that occupies the video frame image district has variable length code conversion coefficient, motion vector and some SSC, and wherein each SSC representative is included in the beginning of the sheet in the coding stream.SSC detector 31 detects the sheet initial code from the digital video signal of having compiled sign indicating number and raw cook initial detection signal is given control unit 32, and it is used for control switch spare 33.Control unit 32 is counted SSC according to the initial detection signal of sheet that is provided by SSC detector 31.When the SSC number of being counted reaches predetermined number, for example 30, just produce control signal by control unit 32, the volume that alternation switch is provided by SSC detector 31 between S1 and S2 the sign indicating number digital video signal, thus the volume that will import each frame of picture signal of sign indicating number be divided into two subframes, and they are stored in two FIFO buffers 34,35.The FIFO buffer outputs to the corresponding decoder component 50,60 that is combined in the image processing apparatus 40 with sub-frame data, and each described decoder component is used to handle the vedio data that is limited by independent subframe, and they are actually identical mutually.Image processing apparatus 40 is rebuild discrete cosine transform (DCT) coefficient, finishes motion compensation on the motion vector basis, and constitutes the view data of physical block representative in the present frame.From separating of image processing apparatus 40 sub-frame data of sign indicating number be sent to frame formatter 80 and be combined to form an independent representative former here by the data flow of video signal, for example be presented at (not shown) on the display unit.
Referring now to Fig. 3,, the there illustrates receives the more detailed block diagram that the view data that is shown in Fig. 2 is divided the image processing apparatus 40 of circuit 30.The decoder component 50 and 60 that is included in the image processing apparatus 40 is made into by components identical, and each element all plays a part same.
As shown in Figure 3, the vedio data that is limited by an independent subframe is divided circuit 30 from view data and is provided to length-changeable decoding (VLD) circuit 51,61 by line 501,601 respectively.The vedio data that each VLD processing of circuit is limited by corresponding subframe.Here it is, and each VLD circuit is the conversion coefficient and the motion vector decoder of variable length code, and transform coefficient data is delivered to separately contrary zigzag scanning device 53,63, motion vector data delivered to each motion compensator 52,62 that is combined in the decoder component.The VLD circuit is a check table basically: promptly, provide many cover sign indicating numbers and define between variable-length code (VLC) and run length code or the motion vector separately relation in the VLD circuit.Be distributed to corresponding processor then from the output of each VLD circuit.The vedio data that each processor processing is limited by corresponding subframe.
The vedio data that is limited by first subframe 13 shown in Figure 1 offers contrary zigzag scanning device 53 by VLD circuit 51 by line 503.In contrary zigzag scanning device 53, the rebuilt original code block that quantization DCT coefficient is provided of quantization DCT coefficient.The code block of quantization DCT coefficient is transformed to the DCT coefficient in inverse quantizer (IQ) 54, and is fed to inverse discrete cosine transform (IDCT) circuit 55, and it becomes current subframe code block and its variance data between the corresponding code block of subframe formerly with the DCT transformation of coefficient.Variance data from idct circuit 55 is fed to adder 56 then.
Simultaneously, the length-changeable decoding motion vector from VLD circuit 51 is fed to motion compensator 52 and the memory assembly selection control 75 in frame storage area 70 by line 502 and 701.Motion compensator 52 is according to extracting corresponding pixel data in the subframe formerly of motion vector from be stored in frame storage area 70, and corresponding pixel data is delivered to adder 56.The corresponding pixel data of obtaining from motion compensator 52 and from pixel variance data addition adder 56 of idct circuit 55, constituting current subframe specifies the presentation graphics data of code block and writes on the first memory assembly 71, be transferred to frame formatter 80, as shown in Figure 2.
Also have, decoder component 60 structurally goes up similar in appearance to decoder component 50 with operation.In other words, the vedio data that is limited by second subframe 16 shown in Figure 1 offers contrary zigzag scanning device 63 by VLD circuit 61 by line 603, and quantization DCT coefficient is rebuilt here.Quantization DCT coefficient is transformed into the DCT coefficient and presents to idct circuit 65 in IQ64, then the DCT transformation of coefficient is become the code block of current subframe and its variance data between the corresponding code block of frame formerly.Be sent to adder 66 again from the variance data of idct circuit 65.
Simultaneously, from the motion vector of VLD circuit 61 by line 602 and 702 fed motion compensator 62 and memory assembly selection control 75.Motion compensator 62 extracts corresponding pixel data and this corresponding pixel data is offered adder 66 according to motion vector from the subframe formerly that is stored in 70 li of frame storage areas.The corresponding pixel data of obtaining from motion compensator 62 and from pixel variance data addition adder 66 of idct circuit 65, be formed in the current subframe presentation graphics data of specifying code block and write on the second memory assembly 72, be transferred to frame formatter 80, as shown in Figure 2.
According to the present invention, a video frame image district is divided into two subframes, and each sub-frame data is processed by using corresponding decoder component.In the case, in the time will handling between two subframes the marginal portion, for example, sheet 30 or sheet 31, as shown in Figure 1, motion compensator 52 or 62 in can reference to storage assembly 71,72.That is, if be found in the subframe 16 during the sheet 30 of first motion vector that provides from VLD circuit 51 during handling subframe 13, motion compensator 52 should reference to storage assembly 72.Similarly, if second motion vector that provides from VLD circuit 61 is subframe 13 when handling sheet 31, motion compensator 62 should reference to storage assembly 71.At this moment, must stop two motion compensators to attempt to visit same memory assembly simultaneously by each the movement compensation process Be Controlled finished in two decoder component.In other words, two memory assemblies make and have suitable locking and make two motion compensators can not visit same memory assembly simultaneously.Being described in detail of aforesaid operations will be consulted Fig. 4 to be provided.
As shown in Figure 3, for the visit of the memory assembly of this mutual exclusiveness, frame storage area 70 comprises 71,72, two multiplexer circuits 73,74 of two memory assemblies, and memory assembly selection control 75.Check in memory assembly selection control 75 whether motion vector is at the adjacent sub-frame place.
Memory assembly selection control 75 receives first and second motion vectors by line 701 and 702 from VLD circuit 51,61, and the first and second selection signals that produce, and gives many multiplexer circuits 73,74 by line 703,704.Memory assembly selection control 75 also produces first and second address dates simultaneously, gives memory assembly 71,72 by line 705,706.
When each motion vector that is offered memory assembly selection control 75 by the VLD circuit is in corresponding each subframe, memory assembly selection control 75 produces first and second and selects signals, and for example, logic " low " is given multiplexer circuit 73,74.Each multiplexer circuit is according to motion vector, in response to selecting signal with first and second of described logic " low ", the corresponding pixel data of the formerly subframe of output from be stored in the corresponding memory assembly.That is, when first selects signal to be logic " low ", multiplexer circuit 73 will offer motion compensator 52 from the pixel data that memory assembly 71 adds to.Similar, when second selects signal to be logic " low ", multiplexer circuit 74 will offer motion compensator 62 from the pixel data that memory assembly 72 adds to.
When each motion vector is in other adjacent sub-frame the time, by memory assembly selection control 75 produce first and second to select signals are logic " height ".In this occasion, multiplexer circuit 73 and 74 is exported respectively from the pixel data of memory assembly 72 and 71.As previously discussed, 71,72 of two memory assemblies mutually between the memory access operation of exclusiveness be under the control of memory assembly selection control 75, to finish.
Consult Fig. 4 A and 4B now, the sequential chart of each subframe processing order has been represented to represent in the there.
Point out that as Fig. 4 decoder component 50 begins to occupy the processing of the vedio data of subframe 13.Behind pending whole each sheet that are included in the subframe 13, by the processing of decoder component 60 beginning subframes 16.At this moment, decoder 50 lockings have been finished up to decoder component 60 till the processing of sheet 31 in subframe 16, and this is in order to prevent to be shown in the same memory assembly of two motion compensators, 52,62 visits among Fig. 3.When sheet 31 was handled by decoder 60, decoder 50 began to handle next sub-frame data, for example, and the sheet 1 ' in next video frame image district.The processing of the sheet 30 ' in next video frame image district is finished in decoder component 60 lockings up to decoder component 50.In this way, the operation of each decoder component 50,60 repeat decoding, up to all vedio datas that enter processed till.
The present invention has only described some preferred embodiments, does not depart from the spirit and scope of the present invention that are published in claims, can make other correction and change.
Claims (2)
1, is used for the encoding digital video signal of coding stream is decoded so that reproduce the device of original video signal, wherein encoding digital video signal comprises a plurality of video requency frame datas, each video requency frame data has some sheet initial codes of having represented the beginning of each sheet therein, and this device comprises:
Be used for from encoding digital video signal detection lug initial code and produce the device of the initial detection signal of sheet;
Control device is used in response to the number counting of the initial detection signal of sheet to the sheet initial code in coding stream, and is used for producing a control signal in response to the number of the sheet initial code of counting;
Be used for video requency frame data being divided into the device of two subframes according to control signal;
Be used to store two first in first out (FIFO) buffer of the video requency frame data that is divided into;
Be used for the digital video signal of coding is removed the image processing apparatus that compresses and reproduce original video signal; And
Be used to connect the device of the original video signal that is reproduced.
2,, it is characterized in that wherein image processing apparatus comprises two decoder component and a frame storage area that is used to reproduce original video signal according to the device of claim 1; Wherein each decoder component produces the digital video signal that compresses through removing, and the frame storage area comprises two memory assemblies, is used to store the digital video signal of removing compression; The memory assembly selection control is used for producing first and second and selects the signal and first and second address dates; And choice device, be used for selecting signal to produce the pixel data of storing in the corresponding memory assembly according to first and second.
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| CN 95101115 CN1126410A (en) | 1995-01-06 | 1995-01-06 | Apparatus for parallel decoding of digital video signals |
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| CN 95101115 CN1126410A (en) | 1995-01-06 | 1995-01-06 | Apparatus for parallel decoding of digital video signals |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100459692C (en) * | 2005-07-14 | 2009-02-04 | 乐金电子（惠州）有限公司 | Controller of double-video decording buffer |
| US8768076B2 (en) | 2004-09-27 | 2014-07-01 | Intel Corporation | Low-latency remote display rendering using tile-based rendering systems |
| WO2018107338A1 (en) * | 2016-12-12 | 2018-06-21 | 深圳市大疆创新科技有限公司 | Image signal processing method and device |
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1995
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8768076B2 (en) | 2004-09-27 | 2014-07-01 | Intel Corporation | Low-latency remote display rendering using tile-based rendering systems |
| CN102625149B (en) * | 2004-09-27 | 2015-08-19 | 英特尔公司 | Use the long-range display reproduction of low latency based on the playback system of sheet |
| CN100459692C (en) * | 2005-07-14 | 2009-02-04 | 乐金电子（惠州）有限公司 | Controller of double-video decording buffer |
| WO2018107338A1 (en) * | 2016-12-12 | 2018-06-21 | 深圳市大疆创新科技有限公司 | Image signal processing method and device |
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