CN112637197A - Multi-channel multiplexing based on HDLC controller - Google Patents
Multi-channel multiplexing based on HDLC controller Download PDFInfo
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- CN112637197A CN112637197A CN202011521976.5A CN202011521976A CN112637197A CN 112637197 A CN112637197 A CN 112637197A CN 202011521976 A CN202011521976 A CN 202011521976A CN 112637197 A CN112637197 A CN 112637197A
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- data
- hdlc
- processing
- bit
- hdlc controller
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- 238000012545 processing Methods 0.000 claims abstract description 26
- 238000013507 mapping Methods 0.000 claims abstract description 5
- 238000009432 framing Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000007726 management method Methods 0.000 description 2
- 230000001502 supplementing effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
- H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
- H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/06—Notations for structuring of protocol data, e.g. abstract syntax notation one [ASN.1]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
Abstract
The invention discloses a multi-channel multiplexing based on an HDLC controller, which comprises the HDLC controller, wherein the internal data processing of the HDLC comprises the following working steps: (1) the DMA controller receives data information; (2) then, the data information is transmitted to HDLC and button management; (3) then the data is transmitted to bit for processing; (4) mapping the time slot after bit processing; (5) e1 frame structure; (6) and transmitting the data. The invention has the advantages that the invention realizes the input of a plurality of groups of signals and the output of a group of signals by changing the bit processing circuit, reduces the resource consumption and is convenient for people to use.
Description
Technical Field
The invention relates to the technical field of data communication, in particular to a multi-channel multiplexing based on an HDLC controller.
Background
Because the internal data of the HDLC controller can be processed only in a single direction at present, namely DMA input data is single, and data input and output are data with the same bit number, certain defects exist during use, if the data bits of the input and output are not consistent during use, multiple times of processing is needed, the efficiency is low, and the resource consumption is increased; and data input and output can only be single-path, and data processing is relatively complicated.
In view of the above, there is a need for an improved data processing method that can accommodate the current needs for data processing.
Disclosure of Invention
Because the data input of the HDLC controller can only be used for transmitting data in a single path and can not meet the use requirements of people when the HDLC controller is used at present, the HDLC controller-based multi-path multiplexing is designed on the basis of the defects of the prior art, the data can be processed in multiple paths, and the input and output data bits can be adjusted as required, so that the HDLC controller is convenient for people to use.
The technical scheme of the invention is that the multi-channel multiplexing based on the HDLC controller comprises the HDLC controller, and the internal data processing of the HDLC comprises the following working steps:
(1) the DMA controller receives data information;
(2) then, the data information is transmitted to HDLC and button management;
(3) then the data is transmitted to bit for processing;
(4) mapping the time slot after bit processing;
(5) e1 frame structure;
(6) and transmitting the data.
Further supplementing the technical scheme, the bit processing in the step (3) can convert the data in the fifo memory from high byte to low byte.
Further supplementing the technical scheme, the bit processing in the step (3) can convert the data in the fifo memory from low bytes to high bytes.
Further complementing the technical solution, the E1 frame structure is framing.
The multi-group signal input and output circuit has the advantages that through changing the bit processing circuit, multi-group signal input and one-group signal output are realized, resource consumption is reduced, and the multi-group signal input and output circuit is convenient for people to use.
Drawings
FIG. 1 is a schematic workflow diagram of the present invention;
FIG. 2 is a schematic flow chart of bit processing according to the present invention.
Detailed Description
In order to make the technical solution more clear to those skilled in the art, the technical solution of the present invention will be explained in detail below: the utility model provides a multichannel multiplexing based on HDLC controller, includes the HDLC controller, and the inside data processing of HDLC includes the following work step:
(1) the DMA controller receives data information;
(2) then, the data information is transmitted to HDLC and button management;
(3) then the data is transmitted to bit for processing;
(4) mapping the time slot after bit processing;
(5) e1 frame structure;
(6) and transmitting the data.
An E1 frame is 256 bits long and divided into 32 slots, one slot is 8 bits, and 8K E1 frames per second pass through the interface, i.e., 8K × 256 ═ 2048kbps, each slot occupies 8 bits in the E1 frame, 8 × 8K ═ 64K, i.e., one E1 contains 32 64K.
The frame structure of the E1 has three modes of framing, multi-frame and non-framing, wherein the 0 th time slot in the framed E1 is used for transmitting frame synchronization data, and the other 31 time slots can be used for transmitting valid data; in E1 of multiframe, except the 0 th time slot, the 16 th time slot is used for transmitting signaling, and only 30 time slots from 1 st to 15 th and from 17 th to 31 th are used for transmitting valid data; while in unframed, all 32 slots are available for transmitting valid data; the E1 frame structure is framed in the present invention.
In the frame structure of E1, 8 bits constitute one slot, and 32 slots constitute one frame;
in use, the bit processing in step (3) can convert the data in the fifo memory from high byte to low byte, for example it can convert 32 bits to 8 bits.
The bit processing in step (3) can convert the data in the fifo memory from low bytes to high bytes, e.g., it can convert 8 bits to 32 bits.
The working process of the invention is as follows: the chip can realize DMA access, actively write the received data into the shared memory or actively take the data out of the shared memory, and the data is sent from the serial port through bit processing and time slot mapping.
The HDLC protocol is used for ensuring that data transmitted to the next layer can be accurately received in the transmission process, namely, no loss exists in error release, and the sequence is correct.
The FIFO memory is a buffer link of the system, if the FIFO memory is not available, the whole system cannot work normally, and the FIFO memory mainly has the functions of several aspects:
(1) caching continuous data streams to prevent data loss during machine entering and storage operations;
(2) the data are collected to enter the machine and be stored, so that frequent bus operation can be avoided, and the burden of a CPU is reduced;
(3) if the DMA operation is not adopted, the data transmission cannot meet the transmission requirement, the load of a CPU is greatly increased, and the data storage work cannot be simultaneously finished; therefore, the data processing of the fifo memory is more important, which is the design objective of the invention.
The technical solutions described above only represent the preferred technical solutions of the present invention, and some possible modifications to some parts of the technical solutions by those skilled in the art all represent the principles of the present invention, and fall within the protection scope of the present invention.
Claims (4)
1. The utility model provides a multichannel multiplexing based on HDLC controller, includes the HDLC controller, its characterized in that, HDLC internal data processing includes the following working procedure:
(1) the DMA controller receives data information;
(2) then, the data information is transmitted to HDLC and button management;
(3) then the data is transmitted to bit for processing;
(4) mapping the time slot after bit processing;
(5) e1 frame structure;
(6) and transmitting the data.
2. The HDLC controller-based multi-pass multiplexing of claim 1, wherein the bit processing in step (3) is capable of converting the data in the fifo memory from high byte to low byte.
3. The HDLC controller-based multi-pass multiplexing of claim 2, wherein the bit processing in step (3) is capable of converting the data in the fifo memory from low bytes to high bytes.
4. The HDLC controller-based multi-pass multiplexing of claim 1, wherein the E1 frame structure is framing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011521976.5A CN112637197A (en) | 2020-12-21 | 2020-12-21 | Multi-channel multiplexing based on HDLC controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011521976.5A CN112637197A (en) | 2020-12-21 | 2020-12-21 | Multi-channel multiplexing based on HDLC controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112637197A true CN112637197A (en) | 2021-04-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011521976.5A Pending CN112637197A (en) | 2020-12-21 | 2020-12-21 | Multi-channel multiplexing based on HDLC controller |
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| Country | Link |
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| CN (1) | CN112637197A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115480708A (en) * | 2022-10-11 | 2022-12-16 | 成都市芯璨科技有限公司 | Method for time division multiplexing local memory access |
-
2020
- 2020-12-21 CN CN202011521976.5A patent/CN112637197A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115480708A (en) * | 2022-10-11 | 2022-12-16 | 成都市芯璨科技有限公司 | Method for time division multiplexing local memory access |
| CN115480708B (en) * | 2022-10-11 | 2023-02-28 | 成都市芯璨科技有限公司 | Method for time division multiplexing local memory access |
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| RJ01 | Rejection of invention patent application after publication | ||
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Application publication date: 20210409 |