CN112635547A - Diode and manufacturing method thereof - Google Patents
Diode and manufacturing method thereof Download PDFInfo
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- CN112635547A CN112635547A CN202011554045.5A CN202011554045A CN112635547A CN 112635547 A CN112635547 A CN 112635547A CN 202011554045 A CN202011554045 A CN 202011554045A CN 112635547 A CN112635547 A CN 112635547A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 95
- 230000002441 reversible effect Effects 0.000 claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 148
- 229920005591 polysilicon Polymers 0.000 claims description 66
- 238000001259 photo etching Methods 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 37
- 238000005530 etching Methods 0.000 claims description 25
- 238000000137 annealing Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 238000005137 deposition process Methods 0.000 claims description 11
- -1 boron ions Chemical class 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 2
- 239000011241 protective layer Substances 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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Abstract
The invention relates to the technical field of semiconductors, in particular to a diode and a manufacturing method thereof, wherein the diode comprises an N substrate, an active region P + layer and a plurality of mos structures, the active region P + layer is formed on the N substrate, the plurality of mos structures are arranged in the active region P + layer, anode metal is arranged on the active region P + layer, each mos structure comprises a groove, a gate oxide layer and polycrystalline silicon are formed in each groove, the N + layer electrically connected with the anode metal is arranged outside each groove, an insulating medium layer is arranged on each groove to separate the polycrystalline silicon from the anode metal, when reverse voltage is applied to the diode to increase, starting voltage is applied to the polycrystalline silicon, a conductive channel is formed outside each groove, the conductive channel is connected with a space charge region in the diode, and reverse current is formed in the diode. The diode provided by the invention can have specific reverse current capability within a certain reverse voltage range, and the avalanche capability of the diode is far superior to that of a common diode.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a diode and a manufacturing method thereof.
Background
In an electronic circuit, the application of the diode is very wide, and the selection of a proper diode is very important for the whole electronic circuit system. The diode is often subjected to the condition that the peak voltage exceeds the breakdown voltage of the diode, so that the diode is subjected to avalanche breakdown, the current is suddenly increased, the magnitude of the avalanche current can be increased to infinity, and the ordinary diode avalanche generally occurs in a local area of a terminal, and the local area is heated due to the flowing of larger avalanche current, so that the thermal damage of the diode can be caused sometimes.
Therefore, selecting an appropriate diode requires that the diode can withstand the current in the circuit and satisfy a certain avalanche capability, that is, avalanche attenuation caused by the flow of electric field attenuation current when a large reverse attenuation bias is applied to the junction of the semiconductor, and the energy that the diode element can absorb at this time is called avalanche capability and indicates the breakdown resistance when a voltage is applied. However, the current diode directly generates avalanche breakdown when the reverse voltage is large, and the avalanche tolerance capability of the diode is weak, so that the use requirement cannot be met in many circuits.
Disclosure of Invention
The invention provides a diode and a manufacturing method thereof, aiming at solving the technical problem that the avalanche capability of the diode in the prior art is weaker, the diode can have specific reverse current capability within a certain reverse voltage range, and the avalanche capability of the diode is far superior to that of a common diode.
The technical scheme of the invention is as follows:
a diode, comprising:
the semiconductor device comprises an N substrate, wherein an active region P + layer is formed on the N substrate;
the active region P + layer is internally provided with a plurality of mos structures and is provided with anode metal;
the diode comprises a plurality of mos structures, each mos structure comprises a groove, a gate oxide layer and polycrystalline silicon are formed in the groove, an N + layer electrically connected with anode metal is arranged outside the side wall of the groove, an insulating medium layer is arranged on the groove to separate the polycrystalline silicon from the anode metal, when reverse voltage is applied to the diode and the voltage is increased, starting voltage is applied to the polycrystalline silicon, a conductive channel is formed outside the groove and is connected with a space charge area in the diode, and reverse current is formed in the diode.
Optionally, the diode further includes a P + field ring, the polysilicon extends outward from the trench and is electrically connected to the P + field ring, and field oxide is disposed between the extension portion of the polysilicon and the N base and between the extension portion of the polysilicon and the P + layer of the active region.
Furthermore, the number of the P + field rings is multiple, and the polysilicon is electrically connected with one or more of the P + field rings.
Optionally, the polysilicon extends out of the trench, a metal layer is disposed on the extended portion of the polysilicon and electrically connected to an external circuit, and field oxide is disposed between the extended portion of the polysilicon and the N-substrate and the active region P + layer.
Furthermore, the insulating medium layer is arranged at the first end of the extension part of the polycrystalline silicon and is separated from the anode metal, and the protection layer is arranged at the second end of the extension part of the polycrystalline silicon and wraps the extension part of the polycrystalline silicon.
Optionally, the diode further includes an inner P + ring junction, the polysilicon extension is electrically connected to the inner P + ring junction, and field oxide is disposed between the polysilicon extension and the N base and between the polysilicon extension and the active region P + layer.
Furthermore, the number of the active region P + layers is multiple, and the polysilicon in the mos structures in the active region P + layers extends to be electrically connected with the inner P + ring junction.
In another aspect of the present invention, a method for manufacturing a diode is provided, in which a layer of field oxide is grown on an N substrate, and an active region is etched, the method further including the following steps:
photoetching and etching processes are adopted, a groove area is defined through photoetching, and etching is carried out to form the groove;
growing an oxide layer on the surface of the groove by thermal oxidation to form a gate oxide layer by adopting a thermal oxidation process;
and depositing a layer of polysilicon on the gate oxide layer by adopting a deposition process, filling the groove, depositing an extension part of the polysilicon on the field oxide, and connecting the extension part of the polysilicon to a P + field ring or a metal layer electrically connected with an external circuit or an internal P + ring junction.
Further, the manufacturing method of the diode further comprises the following steps:
photoetching and etching processes are adopted, different polycrystalline silicon areas are defined by photoetching, and unnecessary polycrystalline silicon is etched;
photoetching, ion implantation and annealing processes are adopted, an active region P + layer region needing to be implanted is defined through photoetching, boron ions are implanted and annealing is carried out, and an active region P + layer is formed;
photoetching, ion implantation and annealing processes are adopted, an N + region needing to be implanted is defined through photoetching, arsenic ions or phosphorus ions are implanted and annealing is carried out, and an N + layer is formed;
depositing an insulating medium layer on the surface of the polycrystalline silicon by adopting a deposition process to serve as electrical isolation of the polycrystalline silicon and anode metal;
photoetching and etching processes are adopted, a contact hole layer is defined by photoetching, and an unnecessary insulating dielectric layer is etched;
depositing a layer of metal on the insulating medium layer and the active region P + layer by adopting a deposition process;
and photoetching and etching processes are adopted, the anode metal layer area is defined by photoetching, and etching is carried out to form an anode metal electrode of the device.
Preferably, the manufacturing method of the diode further comprises the following steps:
an N-epitaxial layer with the required thickness is epitaxially formed on the surface of the N substrate by adopting an epitaxial process to form an N substrate;
growing an oxide layer on the surface of the N-epitaxial layer by thermal oxidation to form field oxygen by adopting a thermal oxidation process;
and photoetching and etching processes are adopted, an active region is defined by photoetching, and field oxygen etching is carried out to form the active region.
After the technical scheme is adopted, compared with the prior art, the invention has the following beneficial effects: the invention adds a plurality of mos structures in an active region P + layer of a diode, a gate oxide layer and polycrystalline silicon grow in a groove of the mos structure, the polycrystalline silicon is connected with a terminal or a high-voltage region through the surface, an inversion layer electron conduction channel is formed between the gate oxide layer and the active region P + layer in the groove, when reverse voltage increases, a space charge layer of the active region P + layer gradually expands towards the groove, when the space charge layer expands to the vicinity of the groove, electrons in the inversion layer at the groove can flow to a cathode of the diode under the action of an electric field to form reverse current, the diode can have specific reverse current capability within a certain reverse voltage range, the reverse current capability of the diode far exceeds the avalanche current capability of a common diode, and the tolerance capability of the diode far exceeds the avalanche current capability of the common diode.
Drawings
FIG. 1 is a schematic diagram of a prior art diode structure;
fig. 2 is a schematic structural diagram of a diode in the first embodiment and the third embodiment;
fig. 3 is a schematic structural view of a diode in the first embodiment taken along the Y-Y direction in fig. 2;
FIG. 4 is a schematic diagram of the reverse voltage and current relationship of a diode of the present invention;
fig. 5 is a schematic structural view of a diode in the third embodiment taken along the Y-Y direction in fig. 2;
FIG. 6 is a schematic partial structure diagram of a diode according to a fourth embodiment;
FIG. 7 is a schematic view showing the connection of polysilicon in the fourth embodiment;
fig. 8 is a schematic structural view of a diode in the fourth embodiment taken along the Y-Y direction in fig. 6.
Wherein,
the field oxide layer structure comprises an N substrate 1, an N substrate 11, an N-epitaxial layer 12, an active region P + layer 2, a mos structure 21, a groove 211, a gate oxide layer 212, polycrystalline silicon 213, an extension portion 2131, an N + layer 214, an insulating medium layer 3, a protective layer 31, anode metal 4, a P + field ring 5, a metal layer 6, an internal P + ring junction 7 and field oxide 8.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
In the description of the present invention, it is to be understood that the orientation or positional relationship indicated by the orientation words such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc. are usually based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplicity of description, and in the case of not making a reverse description, these orientation words do not indicate and imply that the device or element being referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore, should not be considered as limiting the scope of the present invention; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.
Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of the present invention should not be construed as being limited.
The invention aims to provide a diode with high reverse current tolerance, wherein a groove and an N + layer are added in an active region P + layer, a gate oxide layer and polycrystalline silicon are grown in the groove, the polycrystalline silicon is connected with a terminal or a high-voltage region through the surface, an inversion layer electron conduction channel is formed between the gate oxide layer and the active region P + layer in the groove, when reverse voltage is increased, a space charge layer of the active region P + layer can be gradually expanded towards the groove, when the space charge layer is expanded to the vicinity of the groove, electrons in the inversion layer at the groove can flow to a diode cathode under the action of an electric field to form reverse current, and the diode can have specific reverse current capability within a certain reverse voltage range, and the reverse current capability of the diode can far exceed the avalanche current capability of a common diode. The structure of the diode and the method for manufacturing the diode are specifically described below with reference to specific embodiments.
The first embodiment is as follows:
as shown in fig. 1, the diode of the related art includes an N substrate 1 and an active region P + layer 2 formed on the N substrate 1, an anode metal 4 is formed on the active region P + layer 2, a reverse current thereof is small and almost 0 when a reverse voltage is applied, and when the reverse voltage is increased to a reverse breakdown voltage, a current is sharply increased and an avalanche breakdown occurs.
As shown in fig. 2, the diode of the present embodiment includes an N base 1 and an active region P + layer 2 formed on the N base 1, the active region P + layer 2 is provided with an anode metal 4, and here, the N base 1 includes an N substrate 11 and an N-epitaxial layer 12 epitaxially formed on the N substrate 11, and is integrally formed as a PiN diode structure. Further, a plurality of mos structures 21 are arranged in the active region P + layer 2, each mos structure 21 includes a trench 211, a gate oxide layer 212, polysilicon 213 and an N + layer 214, specifically, the bottom of the trench 211 is higher than the bottom of the active region P + layer 2, the gate oxide layer 212 is formed in the trench 211, the polysilicon 213 is filled in the gate oxide layer 212, the N + layer 214 electrically connected with the anode metal 4 is arranged on the outer two sides of the sidewall of the trench 211, and an insulating medium layer 3 is arranged on the trench 211 to separate the polysilicon 213 from the anode metal 4.
Further, the diode of this embodiment further includes a P + field ring 5, as shown in fig. 3, the polysilicon 213 extends upward along the sidewall of the trench 211, and then extends outward of the trench 211 to be electrically connected to the P + field ring 5 at the terminal, and the extension portion 2131 of the polysilicon 213 is separated from the N-body 1 and the active region P + layer 2 by the field oxide 8.
Thus, when the reverse voltage applied by the diode is gradually increased, the space charge region is gradually enlarged, when the space charge region is enlarged to the position of the P + field ring 5, the P + field ring 5 is formed to be at a high potential, because the P + field ring 5 is connected with the polysilicon 213 in the groove 211, the starting voltage is equivalently applied to the polysilicon 213, a circle of inversion layer, namely a conductive channel, is formed outside the groove 211, when the reverse voltage applied by the diode is continuously increased, the space charge region is continuously expanded to the position of the groove 211, and when the space charge region is connected with the inversion layer, electrons in the inversion layer flow to the cathode of the diode under the action of an electric field to form a reverse current.
Fig. 4 is a schematic diagram showing a relationship between a reverse voltage and a current of the diode of the present embodiment, wherein an abscissa is a magnitude of the reverse voltage, an ordinate is a magnitude of the reverse current, and curves A, B, C, D are graphs respectively for different depths of the trench 211, taking curve a as an example, when the reverse voltage is small, such as less than 190V, since the space charge region is also small and is not in contact with the inversion layer outside the trench 211, the reverse current is small at this time and is almost 0, so that the one-way conductivity of the diode can be ensured; when the reverse voltage is increased to 190V, the space charge region starts to contact with the inversion layer outside the trench 211, and then a reverse current gradually starts to form, and when the reverse voltage is within the range of 190V-760V, the diode has a stable reverse current, and the current of the diode in the prior art is still almost 0 in the voltage range, so that avalanche breakdown easily occurs under high electric field intensity.
As shown in fig. 4, the depth of the trench 211 corresponding to the curve A, B, C, D is gradually decreased, that is, the deeper the trench 211 is, the smaller the reverse voltage that needs to be applied to form a specific reverse current of the diode, so that the voltage range for forming the specific reverse current can be adjusted by adjusting the depth of the trench 211 to meet different circuit requirements.
Further, the magnitude of the specific reverse current is related to the density of the mos structure 21 in the diode and the potential magnitude of the polysilicon 213, and the density of the mos structure 21 in the active region P + layer 2 and the potential magnitude of the polysilicon 213 can be designed according to the requirement of the reverse current. The mos structures 21 can be uniformly distributed in the active region P + layer 2 of the diode, and the polysilicon 213 can be connected to different P + field rings 5 in the diode due to the potential, specifically, the diode generally has a plurality of P + field rings 5, and the P + field rings 5 at different positions have different potentials when the diode reverse voltage is increased, so that the polysilicon 213 can be electrically connected to one or more P + field rings 5 at different positions, thereby changing the potential of the polysilicon 213.
In addition, it should be noted that, this embodiment may be implemented in a silicon-based PiN diode device, and may also be implemented in a schottky diode device on a P + layer of a silicon-based active region, and similarly, this embodiment may be implemented in a silicon carbide-based PiN diode device, and may also be implemented in a schottky diode device on a P + layer of a silicon carbide-based active region, in other words, the structure of the diode of this embodiment is suitable for any diode device having an active region P + layer.
As can be seen from the above, the diode provided by the present embodiment can have a specific reverse current capability within a certain reverse voltage range, and the avalanche capability of the diode is far better than that of a common diode.
Example two:
the present embodiment provides a method for manufacturing a diode according to the first embodiment, which specifically includes the following steps:
s1: an N-epitaxial layer 12 with the required thickness is epitaxially formed on the surface of an N substrate 11 by adopting an epitaxial process to form an N matrix 1;
s2: growing an oxide layer on the surface of the N-epitaxial layer 12 by thermal oxidation to form a field oxide 8 by adopting a thermal oxidation process;
s3: photoetching and etching processes are adopted, an active region is defined by photoetching, and field oxide 8 etching is carried out to form the active region;
s4: photoetching and etching processes are adopted, a groove 211 area is defined through photoetching, and etching is carried out to form a groove 211;
s5: adopting a thermal oxidation process to grow an oxide layer on the surface of the groove 211 by using thermal oxidation to form a gate oxide layer 212;
s6: depositing a layer of polysilicon 213 on the gate oxide layer 212 by a deposition process, filling the trench 211, and depositing an extension 2131 of the polysilicon 213 on the field oxide 8, connecting the extension 2131 of the polysilicon 213 to the P + field ring 5;
s7: photoetching and etching processes are adopted, different polycrystalline silicon 213 areas are defined by photoetching, and unnecessary polycrystalline silicon 213 is etched;
s8: photoetching, ion implantation and annealing processes are adopted, the region of the active region P + layer 2 to be implanted is defined by photoetching, boron ions are implanted and annealing is carried out, and the active region P + layer 2 is formed;
s9: photoetching, ion implantation and annealing processes are adopted, an N + region needing to be implanted is defined through photoetching, arsenic ions or phosphorus ions are implanted and annealing is carried out, and an N + layer 214 is formed;
s10: depositing a layer of insulating medium layer 3 on the surface of the polycrystalline silicon 213 by adopting a deposition process to electrically isolate the polycrystalline silicon 213 from the anode metal 4;
s11: photoetching and etching processes are adopted, a contact hole layer is defined by photoetching, and the unnecessary insulating dielectric layer 3 is etched;
s12: depositing a layer of metal on the insulating medium layer 3 and the active region P + layer 2 by adopting a deposition process;
s13: and photoetching and etching processes are adopted, the anode metal 4 layer area is defined by photoetching, and etching is carried out to form an anode metal 4 electrode of the device.
Example three:
the diode of this embodiment is different from the first embodiment in that the polysilicon 213 of this embodiment is connected to an external circuit, and the turn-on voltage is obtained by the external circuit, specifically, as shown in fig. 5, the polysilicon 213 extends out of the trench 211, the metal layer 6 is disposed on the extension portion 2131 of the polysilicon 213 and electrically connected to the external circuit, and the extension portion 2131 of the polysilicon 213 is separated from the N-body 1 and the active region P + layer 2 by the field oxide 8.
Further, a first end of the extension portion 2131 of the polysilicon 213 is provided with an insulating dielectric layer 3 to be separated from the anode metal 4, and a second end of the extension portion 2131 of the polysilicon 213 is provided with an insulating protection layer 31 to wrap the polysilicon 213, so that the polysilicon 213 is protected by the protection layer 31.
Further, the manufacturing method of the diode of this embodiment is different from that of the second embodiment in that in the manufacturing step S6, a deposition process is used to deposit a layer of polysilicon 213 on the gate oxide layer 212, fill the trench 211, and deposit the extension 2131 of the polysilicon 213 on the field oxide 8, so as to connect the extension 2131 of the polysilicon 213 to the metal layer 6 electrically connected to the external circuit.
Example four:
the diode of this embodiment is different from the first embodiment in that the polysilicon 213 of this embodiment is connected to the inner P + ring junction 7 of the diode, specifically, as shown in fig. 6 to 8, the diode of this embodiment further includes the inner P + ring junction 7, the polysilicon 213 is extended to be electrically connected to the inner P + ring junction 7, the field oxide 8 is disposed between the extended portion 2131 of the polysilicon 213 and the N body 1 and the active region P + layer 2, and when the reverse voltage applied to the diode is increased, the inner P + ring junction 7 reaches a high level, so that an inversion layer is formed outside the trench 211.
Further, as shown in fig. 6-7, in the diode of this embodiment, there are a plurality of active regions P + layers 2, and each active region P + layer 2 is provided with a plurality of mos structures 21, the polysilicon 213 in these mos structures 21 extends in the cross-sectional structure shown in fig. 7 to be electrically connected to the inner P + ring junction 7, and the cross-section shown in fig. 7 is parallel to the cross-section shown in fig. 6, so that after the reverse voltage of the polysilicon 213 in each mos structure 21 is increased, the inner P + ring junction 7 is at a high level, and the polysilicon 213 in each mos structure 21 is also at a high level, so that an inversion layer is formed outside the trench 211 of each mos structure 21. Also, as shown in fig. 8, an N + layer 214 may be disposed on the outer sidewall of the trench 211 where the polysilicon 213 is located, thereby increasing the width of the conductive channel.
Further, the manufacturing method of the diode of this embodiment is different from the second embodiment in that in step S6, a layer of polysilicon 213 is deposited on the gate oxide layer 212 by a deposition process, the trench 211 is filled, and the extension 2131 of the polysilicon 213 is deposited on the field oxide 8, so as to connect the extension 2131 of each polysilicon 213 to the inner P + ring junction 7.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.
Claims (10)
1. A diode, comprising:
the semiconductor device comprises an N substrate (1), wherein an active region P + layer (2) is formed on the N substrate (1);
the structure comprises an active region P + layer (2), wherein a plurality of mos structures (21) are arranged in the active region P + layer (2), and anode metal (4) is arranged on the active region P + layer (2);
a plurality of mos structures (21), mos structure (21) includes slot (211), be formed with gate oxide (212) and polycrystalline silicon (213) in slot (211), be equipped with outside slot (211) lateral wall with the N + layer (214) of positive pole metal (4) electricity connection, be equipped with insulating medium layer (3) in order to separate on slot (211) polycrystalline silicon (213) with positive pole metal (4), when the diode applys reverse voltage increase, starting voltage is applyed in polycrystalline silicon (213), slot (211) outward form the conducting channel, the conducting channel with space charge district in the diode connects, form reverse current in the diode.
2. The diode of claim 1, further comprising a P + field ring (5), wherein the polysilicon (213) extends outside the trench (211) and is electrically connected to the P + field ring (5), and wherein a field oxide (8) is disposed between the extension (2131) of the polysilicon (213) and the N body (1) and the active region P + layer (2).
3. The diode of claim 2, wherein said P + field rings (5) are plural, said polysilicon (213) being electrically connected to one or more of said P + field rings (5).
4. The diode of claim 1, wherein the polysilicon (213) extends out of the trench (211), the extension (2131) of the polysilicon (213) has a metal layer (6) disposed thereon for electrical connection to an external circuit, and the extension (2131) of the polysilicon (213) has a field oxide (8) disposed between the N-body (1) and the active region P + layer (2).
5. The diode according to claim 4, wherein a first end of the extended portion (2131) of the polysilicon (213) is provided with the insulating dielectric layer (3) spaced apart from the anode metal (4), and a second end of the extended portion (2131) of the polysilicon (213) is provided with a protective layer (31) surrounding the extended portion (2131) of the polysilicon (213).
6. The diode of claim 1, further comprising an inner P + ring junction (7), wherein the polysilicon (213) extension is electrically connected to the inner P + ring junction (7), and wherein a field oxide (8) is provided between the extension (2131) of the polysilicon (213) and the N body (1) and the active region P + layer (2).
7. The diode of claim 6, wherein said active region P + layers (2) are plural, and wherein said polysilicon (213) in said plurality of mos structures (21) within said plurality of active region P + layers (2) each extend to electrically connect with said inner P + ring junction (7).
8. A method for manufacturing a diode by growing a layer of field oxide (8) on an N-substrate (1) and etching an active region, comprising the steps of:
photoetching and etching processes are adopted, a groove (211) area is defined through photoetching, and etching is carried out to form the groove (211);
growing an oxide layer on the surface of the groove (211) by thermal oxidation by adopting a thermal oxidation process to form a gate oxide layer (212);
depositing a layer of polysilicon (213) on the gate oxide layer (212) by a deposition process, filling the trench (211), and depositing an extension (2131) of the polysilicon (213) on the field oxide (8), connecting the extension (2131) of the polysilicon (213) to a P + field ring (5) or to a metal layer (6) electrically connected to an external circuit or to an internal P + ring junction (7).
9. The method of claim 8, further comprising the steps of:
photoetching and etching processes are adopted, different polycrystalline silicon (213) areas are defined by photoetching, and unnecessary polycrystalline silicon (213) is etched;
photoetching, ion implantation and annealing processes are adopted, the region of the active region P + layer (2) needing to be implanted is defined through photoetching, boron ions are implanted and annealing is carried out, and the active region P + layer (2) is formed;
photoetching, ion implantation and annealing processes are adopted, an N + region needing to be implanted is defined through photoetching, arsenic ions or phosphorus ions are implanted and annealing is carried out, and an N + layer (214) is formed;
depositing an insulating dielectric layer (3) on the surface of the polycrystalline silicon (213) by adopting a deposition process to serve as the electrical isolation of the polycrystalline silicon (213) and the anode metal (4);
photoetching and etching processes are adopted, a contact hole layer is defined by photoetching, and the unnecessary insulating dielectric layer (3) is etched;
depositing a layer of metal on the insulating medium layer (3) and the active region P + layer (2) by adopting a deposition process;
and photoetching and etching processes are adopted, the anode metal (4) layer area is defined by photoetching, and etching is carried out to form an anode metal (4) electrode of the device.
10. The method of claim 8, further comprising the steps of:
an N-epitaxial layer (12) with a required thickness is epitaxially formed on the surface of an N substrate (11) by adopting an epitaxial process to form an N substrate (1);
growing an oxide layer on the surface of the N-epitaxial layer (12) by thermal oxidation by adopting a thermal oxidation process to form field oxide (8);
and photoetching and etching processes are adopted, an active region is defined by photoetching, and field oxide (8) etching is carried out to form the active region.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113809181A (en) * | 2021-11-19 | 2021-12-17 | 陕西亚成微电子股份有限公司 | MOSFET structure with temperature detection function and manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113809181A (en) * | 2021-11-19 | 2021-12-17 | 陕西亚成微电子股份有限公司 | MOSFET structure with temperature detection function and manufacturing method |
| CN113809181B (en) * | 2021-11-19 | 2022-02-22 | 陕西亚成微电子股份有限公司 | MOSFET structure with temperature detection function and manufacturing method |
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