CN113809181B - MOSFET structure with temperature detection function and manufacturing method - Google Patents
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- 238000001514 detection method Methods 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 238000002955 isolation Methods 0.000 claims abstract description 54
- 238000005468 ion implantation Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 238000007740 vapor deposition Methods 0.000 claims abstract description 7
- 210000000746 body region Anatomy 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 48
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 31
- 238000002513 implantation Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 238000001312 dry etching Methods 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 239000011521 glass Substances 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 238000000407 epitaxy Methods 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000005368 silicate glass Substances 0.000 claims description 6
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 238000005019 vapor deposition process Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/66409—Unipolar field-effect transistors
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- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
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Abstract
The invention discloses a MOSFET structure with temperature detection function, wherein an N + substrate comprises an MOSFET drain electrode and a diode cathode electrode, an N-epitaxial layer is laminated on the upper surface of the N + substrate, a grid groove of the MOSFET, a plurality of MOSFET isolation grooves and at least one diode isolation groove are arranged on the upper surface of the N-epitaxial layer, a grid oxide layer is generated on the surfaces of the N-epitaxial layer, the grid groove, the isolation grooves and the diode isolation grooves, an MOSFET source electrode is formed by vapor deposition metal after ion implantation in a contact hole of a MOSFET P-type body area, at least one diode anode is formed by vapor deposition metal after ion implantation in a contact hole of a diode P-type body area, the distance between at least one diode anode and the MOSFET source electrode is smaller than a first threshold value and larger than zero, the first threshold value is determined by a withstand voltage class of the MOSFET structure and a withstand voltage class of the diode.
Description
Technical Field
The invention relates to the technical field of power electronic components, in particular to a MOSFET structure with a temperature detection function and a manufacturing method thereof.
Background
The power MOSFET is a very important core device in a power electronic system, heat loss is mainly generated in the power MOSFET, and particularly in the case of high-current operation, the heat loss easily causes the failure of the power MOSFET, so that the whole circuit system cannot operate, and therefore, the temperature of the whole circuit system needs to be detected. The temperature of the whole system is indirectly detected by controlling the circuit in the IC to detect the temperature of the IC. However, this method cannot detect the temperature of the circuit system most directly and accurately, and the temperature of the IC cannot be real and accurately reflect the temperature of the power MOSFET, which is likely to cause thermal damage to the MOSFET.
The above information disclosed in this background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is well known to those of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a MOSFET structure with a temperature detection function and a manufacturing method thereof, which overcome the defects of the prior art and can directly, truly and accurately reflect the temperature of a power MOSFET.
In order to achieve the above object, the present invention provides a MOSFET structure having a temperature detection function including,
an N + substrate comprising a MOSFET drain and a diode cathode;
the N-epitaxial layer is stacked on the upper surface of the N + substrate, and a grid groove of the MOSFET, a plurality of MOSFET isolation grooves and at least one diode isolation groove are formed in the upper surface of the N-epitaxial layer;
the gate oxide layer is generated on the surfaces of the N-epitaxial layer, the gate trench, the MOSFET isolation trench and the diode isolation trench;
a polysilicon gate deposited in the gate trench;
the MOSFET P-type body region is implanted with ions in the N-epitaxial layer;
the P-type body region of the diode is implanted with ions in the N-epitaxial layer;
a source electrode N + formed by ion implantation in the N-epitaxial layer;
the middle dielectric layer is stacked on the gate oxide layer and the polysilicon gate, contact holes of MOSFET P-type body regions are formed from the middle dielectric layer to the MOSFET P-type body regions through etching, and contact holes of diode P-type body regions are formed from the middle dielectric layer to the diode P-type body regions through etching, wherein the number of the contact holes of the MOSFET P-type body regions is multiple, and the number of the contact holes of the diode P-type body regions is multiple;
a MOSFET source formed by vapor deposition of metal after ion implantation in the contact hole of the MOSFET P-type body region;
and the distance between the anode of the diode and the source electrode of the MOSFET is smaller than a first threshold value and larger than zero, and the first threshold value is determined by the voltage-resistant grade of the MOSFET structure and the voltage-resistant grade of the diode.
Preferably, the first and second liquid crystal materials are,
the at least one diode anode is distributed around the MOSFET source.
Preferably, the first and second liquid crystal materials are,
for the MOSFET structure, measuring a leakage current of a diode in the MOSFET structure via a control IC to detect a temperature of the MOSFET structure and turning off the MOSFET structure by the control IC when the temperature exceeds a threshold.
Preferably, the first and second liquid crystal materials are,
the distance between every two adjacent MOSFET isolation trenches is the same, the width of all the MOSFET isolation trenches is the same, and the width of at least one diode isolation trench is the same as the width of any one MOSFET isolation trench.
Preferably, the first and second liquid crystal materials are,
the distance between every two adjacent diode isolation trenches is the same, and the distance is also the same as the distance between any two adjacent MOSFET isolation trenches.
Preferably, the first and second liquid crystal materials are,
the intermediate dielectric layer comprises undoped silicon glass and silicon glass containing boron and phosphorus, and the undoped silicon glass and the silicon glass containing boron and phosphorus are both formed by adopting a chemical vapor deposition process.
In addition, the present invention also provides a method for manufacturing a MOSFET structure having a temperature detection function according to the present invention, characterized by comprising the steps of,
s100, providing an N + substrate, and laminating an N-epitaxial layer on the N + substrate;
s200, photoetching and limiting a groove area on the N-epitaxial layer, and etching the groove area by a dry etching process to form a gate groove of the MOSFET, a plurality of MOSFET isolation grooves and at least one diode isolation groove;
s300, growing an oxide layer on the surface of the N-epitaxial layer by adopting a thermal oxidation process, removing the oxide layer by wet etching, and performing a second thermal oxidation process on the whole surface of the N-epitaxial layer with the oxide layer removed to form a gate oxide layer of the MOSFET;
s400, depositing polycrystalline silicon in the grid groove and on the gate oxide layer of the N-epitaxy to enable the grid groove to be filled with the polycrystalline silicon, then etching back the deposited polycrystalline silicon by using a dry etching process to etch and remove the polycrystalline silicon on the grid oxide layer on the upper surface of the N-epitaxy, and reserving the polycrystalline silicon in the grid groove to form a polycrystalline silicon grid and an isolation structure of the MOSFET;
s500, forming a P-type body region of the MOSFET and a P-type body region of the diode on the N-epitaxial layer by sequentially adopting an ion implantation process and a thermal annealing process, photoetching on the N-epitaxial layer to define a source N + implantation region, forming a source N + in the source N + implantation region by adopting the ion implantation process, and then activating implanted ions by carrying out thermal annealing;
s600, depositing undoped silicon glass and silicon glass containing boron and phosphorus on the upper surface of the gate oxide layer by using a chemical vapor deposition process, etching contact holes by using a dry etching process, then performing ion implantation, and finally depositing metal tungsten and aluminum copper in sequence by using a vapor deposition process to form a source electrode and a diode anode of the MOSFET, wherein the distance between the contact hole of the diode P-type body region for forming the diode anode and the contact hole of the MOSFET P-type body region for forming the source electrode of the MOSFET is less than a second threshold value and greater than zero, the second threshold value is also determined by the voltage-resistant grade of the MOSFET structure and the voltage-resistant grade of the diode, and the second threshold value is greater than the first threshold value.
Preferably, the first and second liquid crystal materials are,
the width of the grid groove is 0.2-0.5 μm, and the depth is 1-2 μm.
Preferably, the first and second liquid crystal materials are,
the thickness of the gate oxide layer is 500-1200A.
Preferably, the first and second liquid crystal materials are,
the source N + implantation region adopts arsenic as an ion implantation impurity type, the energy is 60-100KeV, and the implantation dosage is 4E15-8E15/cm2。
In the above technical solution, the MOSFET structure with temperature detection function and the manufacturing method provided by the present invention have the following beneficial effects: the invention detects the temperature rise of the MOS field effect transistor by detecting the reverse leakage current of the diode along with the temperature change and enables the control IC to turn off the MOS field effect transistor in time so as to improve the reliability of the MOS field effect transistor. Under the condition of not increasing the process steps of the MOS field effect transistor, the diode which can be used for temperature detection is integrated, the temperature of the MOS field effect transistor can be detected more accurately and directly, the reliability of the system is improved, and particularly the MOS field effect transistor is in a large-current working state in a normally open state.
Drawings
In order to more clearly illustrate the embodiments of the present application or technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings can be obtained by those skilled in the art according to the drawings.
Fig. 1 is a schematic structural diagram of a MOSFET structure having a temperature detection function according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a gate trench and isolation trench generation method for a MOSFET structure with temperature detection according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a gate oxide layer generation method for a MOSFET structure with temperature detection according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a method of fabricating a MOSFET structure with temperature sensing capability that produces P-type body regions in accordance with one embodiment of the present invention;
fig. 5 is a schematic diagram of a MOSFET source electrode and a diode anode electrode of a method of manufacturing a MOSFET structure with temperature detection function according to an embodiment of the present invention;
fig. 6 is a schematic diagram of the positions of the resulting MOSFET and diode of the method of fabricating a MOSFET structure with temperature sensing capability according to one embodiment of the invention.
Description of the figure numbers: the semiconductor device comprises a 1-N + substrate, a 2-N-epitaxial layer, a 3-grid groove, a 4-MOSFET isolation groove, a 5-diode isolation groove, a 6-grid oxide layer, a 7-polysilicon grid, an 8-MOSFET P body region, a 9-diode P body region, a 10-source electrode N +, an 11-contact hole, a 12-MOSFET source electrode, a 13-diode anode, a 14-MOSFET drain electrode and a 15-diode cathode.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be described in detail and completely with reference to fig. 1 to 6 of the drawings of the embodiments of the present invention, and it is apparent that the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the equipment or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In order to make the technical solutions of the present invention better understood, those skilled in the art will now describe the present invention in further detail with reference to the accompanying drawings.
In one embodiment, as shown in fig. 1, a MOSFET structure with temperature sensing comprises,
an N + substrate 1 comprising a MOSFET drain 14 and a diode cathode 15;
the N-epitaxial layer 2 is laminated on the upper surface of the N + substrate 1, and a gate trench 3 of an MOSFET, a plurality of MOSFET isolation trenches 4 and at least one diode isolation trench 5 are arranged on the upper surface of the N-epitaxial layer 2;
a gate oxide layer 6 which is generated on the surfaces of the N-epitaxial layer 2, the gate trench 3, the MOSFET isolation trench 4 and the diode isolation trench 5;
a polysilicon gate 7 deposited in the gate trench 3;
a MOSFET P-type body region 8 ion-implanted in the N-epitaxial layer 2;
a diode P-type body region 9 ion-implanted in the N-epitaxial layer 2;
a source N +10 formed by ion implantation in the N-epitaxial layer 2;
an intermediate dielectric layer which is laminated on the gate oxide layer 6 and the polysilicon gate 7, and a plurality of contact holes 11 are formed by etching from the intermediate dielectric layer to a MOSFET P type body region 8 and a diode P type body region 9; the contact holes 11 comprise a plurality of contact holes of MOSFET P-type body regions and a plurality of contact holes of diode P-type body regions;
a MOSFET source 12 formed by ion implantation followed by vapor deposition of metal in the contact holes of said MOSFET P-type body region 8,
at least one diode anode formed by vapor deposition of metal after ion implantation in the contact hole of the diode P-type body region 9, the distance between the at least one diode anode and the MOSFET source is smaller than a first threshold value and larger than zero, and the first threshold value is determined by the voltage-resistant grade of the MOSFET structure and the voltage-resistant grade of the diode.
It can be appreciated that the first threshold ensures that the respective MOSFET source, diode anode is not broken down. Whichever is lower of the withstand voltage class of the MOSFET structure and the withstand voltage class of the diode is the final constraint.
In the preferred embodiment of the MOSFET structure with temperature detection function, the at least one diode anode is distributed around the MOSFET source 12.
In the preferred embodiment of the MOSFET structure with temperature detection function, for the MOSFET structure, a leakage current of a diode in the MOSFET structure is measured via a control IC to detect a temperature of the MOSFET structure and the MOSFET structure is turned off by the control IC when the temperature exceeds a threshold.
The threshold corresponding to the temperature is determined by the heat dissipation environment and the heat dissipation capability of the MOSFET structure in practical applications. For example, the threshold may be 90 degrees celsius or even higher if the heat dissipation environment is capable of dissipating heat quickly and without causing significant heat buildup; the threshold may be 50 degrees celsius or even lower if heat build-up is significant due to an inability of the heat dissipation environment to dissipate heat quickly. It is understood that 90 degrees celsius or 50 degrees celsius are merely examples herein.
In the preferred embodiment of the MOSFET structure with temperature detection function, the distance between every two adjacent MOSFET isolation trenches is the same, the width of all MOSFET isolation trenches is the same, and the width of at least one diode isolation trench is the same as the width of any MOSFET isolation trench.
In the preferred embodiment of the MOSFET structure with temperature detection function, the distance between every two adjacent diode isolation trenches is the same, and the distance is also the same as the distance between any two adjacent MOSFET isolation trenches.
It should be emphasized that the distances and widths of the MOSFET structures proposed by the present invention may be the same or different, and are not limited thereto, but the same shall belong to the preferred embodiments. The distance and width may affect the performance parameters of the related devices, and the performance parameters may cause the related distance and width to be the same or different as the constraint condition. Thus, in another embodiment, the distance between every two adjacent MOSFET isolation trenches is different, the width of all MOSFET isolation trenches is different, and the width of at least one diode isolation trench is different from the width of any one MOSFET isolation trench.
In the preferred embodiment of the MOSFET structure with temperature detection function, the intermediate dielectric layer includes undoped silicate glass and silicate glass containing boron and phosphorus, both of which are formed by using a chemical vapor deposition process.
In the preferred embodiment of the MOSFET structure with temperature detection function, the MOSFET P-type body region 8 is larger in size than the P-type body region 9 of the diode.
As shown in fig. 2 to 6, the present invention also discloses a method for manufacturing the MOSFET structure with temperature detection function, comprising the following steps,
s100, providing an N + substrate 1, and laminating an N-epitaxial layer 2 on the N + substrate 1; it can be understood that the N + substrate 1 is not only the drain electrode of the MOSFET, but also the cathode electrode of the diode;
s200, photoetching and limiting a groove area on the N-epitaxial layer 2, and etching the groove area by a dry etching process to form a gate groove 3 of the MOSFET, a plurality of MOSFET isolation grooves 4 and at least one diode isolation groove 5;
s300, growing an oxide layer on the surface of the N-epitaxial layer 2 by adopting a thermal oxidation process, removing the oxide layer by wet etching, and performing a second thermal oxidation process on the whole surface of the N-epitaxial layer 2 with the oxide layer removed to form a gate oxide layer 6 of the MOSFET;
s400, depositing polycrystalline silicon in the grid groove 3 and on the gate oxide layer 6 of the N-epitaxy to enable the grid groove 3 to be filled with the polycrystalline silicon, then etching back the deposited polycrystalline silicon by using a dry etching process to etch and remove the polycrystalline silicon on the gate oxide layer 6 on the upper surface of the N-epitaxy, and reserving the polycrystalline silicon in the grid groove 3 to form a polycrystalline silicon grid and an isolation structure of the MOSFET;
s500, sequentially adopting an ion implantation process and a thermal annealing process on the N-epitaxial layer 2 to form a MOSFET P type body region 8 and a diode P type body region 9, photoetching on the N-epitaxial layer 2 to define a source N + implantation region, adopting the ion implantation process on the source N + implantation region to form a source N +10, and then carrying out thermal annealing to activate implanted ions;
s600, depositing undoped silicon glass and silicon glass containing boron and phosphorus on the upper surface of the gate oxide layer 6 by using a chemical vapor deposition process, etching a contact hole 11 by using a dry etching process, then performing ion implantation, and finally depositing metal tungsten and aluminum copper in sequence by using a vapor deposition process to form a source electrode of the MOSFET and a diode anode 13, wherein the distance between the contact hole of the diode P-type body region for forming the diode anode 13 and the contact hole of the MOSFET P-type body region for forming the source electrode of the MOSFET is less than a second threshold value and greater than zero, the second threshold value is also determined by the voltage-resistant grade of the MOSFET structure and the voltage-resistant grade of the diode, and the second threshold value is greater than the first threshold value.
The second threshold is greater than the first threshold because: for both types of contact holes, the electrode covers a larger area than the aperture of the hole itself.
In a preferred embodiment of the manufacturing method, the gate trench 3 has a width of 0.2 to 0.5 μm and a depth of 1 to 2 μm. It is to be understood that these parameters are determined by the etch process and device performance parameters, and that similar dimensional parameters of the present invention are likewise determined by the process and performance parameters.
In a preferred embodiment of the method, the gate oxide layer 6 has a thickness of 500 to 1200A.
In a preferred embodiment of the manufacturing method, the source N +10 implantation region adopts arsenic as an ion implantation impurity type, the energy is 60 to 100KeV, and the implantation dose is 4E15 to 8E15/cm2。
In the preferred embodiment of the manufacturing method, the MOSFET and the diode comprise an N + substrate 1 and an N-epitaxial layer 2, a trench region is defined by performing a photolithography process on the N-epitaxial layer 2, the trench region is etched by a dry etching process to define a trench, the trench comprises a gate trench 3 and an isolation trench of the MOSFET and an isolation trench of the diode, and the number of the isolation trenches of the MOSFET is 3 or more than 3.
In the preferred embodiment of the manufacturing method, an oxide layer of 500-;
in the preferred embodiment of the manufacturing method, polysilicon is deposited in the trench and on the gate oxide layer 6 of the N-epitaxy to ensure that the gate trench 3 is filled with polysilicon, then the deposited polysilicon is etched back by a dry etching process to etch and remove the polysilicon of the gate oxide layer 6 on the upper surface of the N-epitaxy, the polysilicon in the gate trench 3 is retained, and the polysilicon gate 7 and the isolation structure of the MOSFET are formed.
In the preferred embodiment of the manufacturing method, the N-epitaxial layer 2 is subjected to an ion implantation process, and then a thermal annealing process is performed to form the MOSFET P-type body region 8 and the diode P-type body region 9. Performing a photolithography process on the N-epitaxial layer 2 to define a source N +10 implantation region, performing an ion implantation process on the N-epitaxial layer 2 of the source N +10 implantation region to form a source N +10, and performing thermal annealing to activate implanted ions, wherein the ion implantation impurity type is arsenic, the energy is 60-100KeV, and the implantation dose is generally 4E15-8E15/cm2Left and right; in addition, after USG (undoped silicate glass) and BPSG (silicate glass containing boron and phosphorus) are deposited on the upper surface of the oxide layer by a chemical vapor deposition process, four contact holes 11 are etched by a dry etching process, ion implantation is carried out, and finally, metal tungsten and aluminum copper are sequentially deposited by a vapor deposition process to form a source electrode of the MOSFET and an anode 13 electrode of the diode.
In the preferred embodiment of the manufacturing method, the integrated temperature diodes are distributed around or in the middle of the MOSFET and are close to the routing of the MOSFET source electrode 12, so that the temperature rise of the MOSFET can be really and rapidly reflected on the leakage current of the diodes, and when the temperature exceeds the corresponding threshold value, the control IC is enabled to rapidly turn off the MOSFET. It will be appreciated that the number of diodes is one or more, preferably more than one, selected in particular according to the area of the MOSFETs and the redundancy of the diodes, in accordance with the inventive concept. When a plurality of diodes are provided, the diodes may be of uniform size or may be of non-uniform size.
Finally, it should be noted that: the embodiments described are only a part of the embodiments of the present application, and not all embodiments, and all other embodiments obtained by those skilled in the art without making creative efforts based on the embodiments in the present application belong to the protection scope of the present application.
While certain exemplary embodiments of the present invention have been described above by way of illustration only, it will be apparent to those of ordinary skill in the art that the described embodiments may be modified in various different ways without departing from the spirit and scope of the invention. Accordingly, the drawings and description are illustrative in nature and should not be construed as limiting the scope of the invention.
Claims (9)
1. A MOSFET structure with temperature detection function, which is characterized by comprising,
an N + substrate comprising a MOSFET drain and a diode cathode;
the N-epitaxial layer is stacked on the upper surface of the N + substrate, and a grid groove of the MOSFET, a plurality of MOSFET isolation grooves and at least one diode isolation groove are formed in the upper surface of the N-epitaxial layer;
the gate oxide layer is generated on the surfaces of the N-epitaxial layer, the gate trench, the MOSFET isolation trench and the diode isolation trench;
a polysilicon gate deposited in the gate trench;
the MOSFET P-type body region is implanted with ions in the N-epitaxial layer;
the P-type body region of the diode is implanted with ions in the N-epitaxial layer;
a source electrode N + formed by ion implantation in the N-epitaxial layer;
the middle dielectric layer is stacked on the gate oxide layer and the polysilicon gate, contact holes of MOSFET P-type body regions are formed from the middle dielectric layer to the MOSFET P-type body regions through etching, and contact holes of diode P-type body regions are formed from the middle dielectric layer to the diode P-type body regions through etching, wherein the number of the contact holes of the MOSFET P-type body regions is multiple, and the number of the contact holes of the diode P-type body regions is multiple;
a MOSFET source formed by vapor deposition of metal after ion implantation in the contact hole of the MOSFET P-type body region;
at least one diode anode formed by vapor deposition metal after ion implantation in the contact hole of the diode P-type body region, wherein the distance between the diode anode and the MOSFET source electrode is smaller than a first threshold and larger than zero, the first threshold is determined by the voltage-resistant grade of the MOSFET structure and the voltage-resistant grade of the diode, the size of the MOSFET P-type body region is larger than that of the diode P-type body region, the distance between every two adjacent MOSFET isolation trenches is the same, the width of all the MOSFET isolation trenches is the same, and the width of at least one diode isolation trench is the same as that of any MOSFET isolation trench.
2. The MOSFET structure of claim 1, wherein the at least one diode anode is distributed around the MOSFET source.
3. The MOSFET structure of claim 1, wherein for the MOSFET structure, a leakage current of a diode in the MOSFET structure is measured via a control IC to detect a temperature of the MOSFET structure and the MOSFET structure is turned off by the control IC when the temperature exceeds a threshold.
4. The MOSFET structure with temperature detection function of claim 3, wherein the distance between every two adjacent diode isolation trenches is the same, and the distance is the same as the distance between any two adjacent MOSFET isolation trenches.
5. The MOSFET structure of claim 1, wherein the intermediate dielectric layer comprises undoped silicate glass and silicate glass containing boron and phosphorus, both formed by chemical vapor deposition.
6. A method for manufacturing a MOSFET structure with temperature detection function according to any one of claims 1-5, characterized by comprising the steps of,
s100, providing an N + substrate, and laminating an N-epitaxial layer on the N + substrate;
s200, photoetching and limiting a groove area on the N-epitaxial layer, and etching the groove area by a dry etching process to form a gate groove of the MOSFET, a plurality of MOSFET isolation grooves and at least one diode isolation groove;
s300, growing an oxide layer on the surface of the N-epitaxial layer by adopting a thermal oxidation process, removing the oxide layer by wet etching, and performing a second thermal oxidation process on the whole surface of the N-epitaxial layer with the oxide layer removed to form a gate oxide layer of the MOSFET;
s400, depositing polycrystalline silicon in the grid groove and on the gate oxide layer of the N-epitaxy to enable the grid groove to be filled with the polycrystalline silicon, then etching back the deposited polycrystalline silicon by using a dry etching process to etch and remove the polycrystalline silicon on the grid oxide layer on the upper surface of the N-epitaxy, and reserving the polycrystalline silicon in the grid groove to form a polycrystalline silicon grid and an isolation structure of the MOSFET;
s500, forming a P-type body region of the MOSFET and a P-type body region of the diode on the N-epitaxial layer by sequentially adopting an ion implantation process and a thermal annealing process, photoetching on the N-epitaxial layer to define a source N + implantation region, forming a source N + in the source N + implantation region by adopting the ion implantation process, and then activating implanted ions by carrying out thermal annealing;
s600, depositing undoped silicon glass and silicon glass containing boron and phosphorus on the upper surface of the gate oxide layer by using a chemical vapor deposition process, etching contact holes by using a dry etching process, then performing ion implantation, and finally depositing metal tungsten and aluminum copper in sequence by using a vapor deposition process to form a source electrode and a diode anode of the MOSFET, wherein the distance between the contact hole of the diode P-type body region for forming the diode anode and the contact hole of the MOSFET P-type body region for forming the source electrode of the MOSFET is less than a second threshold value and greater than zero, the second threshold value is also determined by the voltage-resistant grade of the MOSFET structure and the voltage-resistant grade of the diode, and the second threshold value is greater than the first threshold value.
7. The manufacturing method according to claim 6,
the width of the grid groove is 0.2-0.5 μm, and the depth is 1-2 μm.
8. The manufacturing method according to claim 6,
the thickness of the gate oxide layer is 500-1200 angstroms.
9. The manufacturing method according to claim 6,
the source N + implantation region adopts arsenic as an ion implantation impurity type, the energy is 60-100KeV, and the implantation dosage is 4E15-8E15/cm2。
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