CN112630632A

CN112630632A - Implementation method of on-line logic analyzer based on automatic signal pulling

Info

Publication number: CN112630632A
Application number: CN202011609667.3A
Authority: CN
Inventors: 杨海钢
Original assignee: Aerospace Information Research Institute of CAS
Current assignee: Aerospace Information Research Institute of CAS
Priority date: 2020-12-28
Filing date: 2020-12-28
Publication date: 2021-04-09
Anticipated expiration: 2040-12-28
Also published as: CN112630632B

Abstract

An implementation method of an online logic analyzer based on signal automatic pulling comprises the following steps: opening a logic analyzer, and reading in the synthesized netlist file; the logic analyzer automatically counts all internal signals in the netlist file; selecting internal signals of one or more netlists by a user; the logic analyzer automatically adds a netlist port for each internal signal and connects the port to the corresponding internal signal; the user sets port constraint for some or all selected signals, and the logic analyzer automatically generates port constraint statements; the logic analyzer automatically generates a new netlist file and a new port constraint file, and informs a user of a magnetic disk path where the new netlist file and the new port constraint file are located; after finding a new netlist file and a new port constraint file, a user operates layout wiring to generate a code stream, and the code stream is downloaded to a development board; and the user captures and grabs the real-time signal of the chip through the oscilloscope.

Description

Implementation method of on-line logic analyzer based on automatic signal pulling

Technical Field

The invention relates to the technical field of digital logic analyzers, in particular to an implementation method of an online logic analyzer based on signal automatic pulling.

Background

In the real-time debugging process of the signal of the operation of the RTL netlist, two online logic analyzers are currently used in a popular way:

1) signals are captured and grabbed by using an oscilloscope, and the signals can only be port signals of an RTL netlist, and the main implementation scheme is as follows:

firstly, synthesizing and laying out wiring on an RTL netlist to obtain a binary code stream file, then connecting a probe hook of an oscilloscope with a contact pin of a development board, setting a signal trigger condition, a sampling depth, a signal cache size and the like on the oscilloscope, then downloading the code stream file to the development board through a JTAG (joint test action group), immediately executing various instructions in the code stream by a chip after the code stream is successfully downloaded, and sending data to the contact pin of the development board through a port outwards, so that the oscilloscope can receive signal data, and when the trigger condition is met, observing whether a signal level value on the oscilloscope meets an expectation or not, and exporting the signal data and then analyzing by using MATLAB software;

2) the software-implemented online logic analyzer captures and captures signals, which may be port signals of the RTL netlist or any internal signal, such as ChipScope Pro developed by Xilinx corporation, usa and SignalTap II developed by Altera corporation.

The following generally describes an embodiment of an online logic analyzer implemented by software, taking ChipScope Pro as an example, and the following is a simplified implementation flow of ChipScope Pro:

firstly, an RTL synthesis tool is used for synthesizing an RTL file to obtain a synthesized netlist file, then a trigger condition, a sampling depth and the like are configured on software, then an online logic analyzer can automatically compile and generate a result file (an IP core), then layout and wiring are carried out on the IP core to obtain a code stream file, the code stream file is downloaded to a development board through a JTAG, after the code stream file is successfully downloaded, a chip can immediately execute various instructions in the code stream and send data through a JTAG port, after the IDE software receives the JTAG data, waveform data are finally displayed on a display of a PC in real time through a series of processing such as format conversion, GUI display and the like.

In the process of implementing the present invention, the inventor finds that the prior art has the following defects:

1. the defect of capturing and grabbing real-time signals of the chip by using the oscilloscope is that only port signals of the RTL netlist can be grabbed. Because only the port of the RTL netlist can be constrained to the packaging port of the chip through logic synthesis and layout wiring, signals in the RTL netlist cannot be directly constrained to the packaging port of the chip and cannot be captured by an oscilloscope, and therefore the signal capturing range is greatly limited. If a user wants to capture an internal signal, the user needs to manually modify the RTL netlist or the synthesized netlist, the internal signal is led out through a newly-built port, then the new port is synthesized, the wiring is laid out again, and a code stream is generated.

2. The defects of capturing and grabbing chip real-time signals by an online logic analyzer realized by software mainly comprise the following two aspects:

1) the waveform data length is kept short, generally, dozens of megabytes or hundreds of megabytes of data are kept at most, and an oscilloscope can keep more than 1GB byte of data;

2) the storage of the sampling signal can occupy the logic resource, the memory resource and the wiring resource of the chip, when the width and the depth of signal capture and sampling are large, the resources are seriously occupied, great pressure is brought to layout and wiring, and the layout and wiring failure is caused in serious conditions, so that the sampling requirement of a user cannot be met.

Disclosure of Invention

In view of the above, the main objective of the present invention is to provide an implementation method of an online logic analyzer based on signal automatic pulling, so as to partially solve at least one of the above technical problems.

In order to achieve the above object, as an aspect of the present invention, there is provided an implementation method of an online logic analyzer based on signal automatic pulling, including the steps of:

opening a logic analyzer, and reading in the synthesized netlist file;

the logic analyzer automatically counts all internal signals in the netlist file;

selecting internal signals of one or more netlists by a user;

the logic analyzer automatically adds a netlist port for each internal signal and connects the port to the corresponding internal signal;

the user sets port constraint for some or all selected signals, and the logic analyzer automatically generates port constraint statements;

the logic analyzer automatically generates a new netlist file and a new port constraint file, and informs a user of a magnetic disk path where the new netlist file and the new port constraint file are located;

after finding a new netlist file and a new port constraint file, a user operates layout wiring to generate a code stream, and the code stream is downloaded to a development board;

and the user captures and grabs the real-time signal of the chip through the oscilloscope.

When the user selects the internal signals of one or more netlists, if the user selects the repeated internal signals, the logic analyzer prompts error information of 'signal repetition' and guides the user to cancel the operation.

Before setting the port constraint, the logic analyzer lists all candidate items including chip port addresses corresponding to all pins in the development board, and the logic analyzer automatically generates a port constraint statement supported by a layout and wiring tool when the user selects one of the port addresses.

If the user sets a repeated chip port address for a certain signal or a certain chip port address is occupied, the logic analyzer prompts error information and guides the user to cancel the operation.

Based on the technical scheme, compared with the prior art, the implementation method of the online logic analyzer based on signal automatic pulling has at least one of the following beneficial effects:

1. the invention greatly simplifies the flows of manually modifying the netlist and manually creating the port constraint by the user;

2. the invention can avoid the grammar problem caused by manually writing the file by the user;

3. the logic analyzer of the invention greatly improves the efficiency of users in searching internal signals, constructing a new netlist, compiling a port constraint file and the like by automatically counting all internal signals, automatically constructing a netlist port, automatically connecting a port and internal signals, automatically generating a new netlist file, automatically generating a port constraint statement, automatically generating a new port constraint file and the like;

4. the operation object of the logic analyzer is not limited to the netlist after logic synthesis, and is also suitable for the RTL original netlist;

5. the logic analyzer of the invention, through combining with the oscilloscope, not only inherits the advantage of powerful sampling function of the oscilloscope, but also avoids the defects that the layout and the wiring are influenced when the online logic analyzer compiled by software has shorter data retention and larger resource occupation.

Drawings

FIG. 1 is a schematic flow chart diagram of a method for implementing an on-line logic analyzer based on signal automatic pull according to an embodiment of the present invention;

FIG. 2 is a main interface for the actual operation of the logic analyzer according to the embodiment of the present invention;

fig. 3 is an operation interface for adding port constraints to the logic analyzer according to the embodiment of the present invention.

Detailed Description

In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.

The invention provides a novel on-line logic analyzer (hereinafter referred to as an analyzer) based on signal automatic pulling, which can guide a user to select any one or more RTL internal signals, then automatically generate a new RTL port and connect the RTL internal signals selected by the user, and simultaneously can guide the user to carry out packaging constraint on the RTL port and automatically generate a new synthesized netlist and port constraint files, thereby greatly simplifying the process of manually leading out the RTL internal signals by the user, avoiding the grammatical problem caused by manually compiling the netlist or the port constraint files, and finally greatly shortening the debugging period of the RTL netlist.

As shown in fig. 1, a schematic flow chart of an implementation method of an online logic analyzer based on signal automatic pulling specifically includes the following steps:

the first step is as follows: opening an analyzer, and reading in the synthesized netlist file;

the second step is that: the analyzer automatically counts all internal signals (wire, reg and other statements) in the netlist file, and displays the internal signals to a user after sequencing in a pull-down list form;

the third step: the user selects one or more internal signals of the netlist, and if the user selects repeated internal signals, the analyzer prompts error information of 'signal repetition' and guides the user to cancel the operation;

the fourth step: the analyzer automatically adds a netlist port for each internal signal and connects the port to the internal signal, so that the internal signal is pulled to the port of the netlist, for example, the following RTL codes exist in the netlist:

module test(a，b，c)；

input a；

input b；

output c；

wire w；

assign w＝a&b；

assign c＝w&！b；

endmodule

the user wants to capture the waveform of the signal of wire w with the analyzer, and then just select the w signal in the analyzer interface, the analyzer will automatically add a port (e.g., named w _ pull) to the w signal and assign the w signal through the assign statement given in verilog syntax, and the modified RTL code is as follows:

module test(a，b，c，w_pull)；

input a；

input b；

output c；

output w_pull；

wire w；

wire w_pull；

assign w＝a&b；

assign c＝w&！b；

assign w_pull＝w；

endmodule

the fifth step: the user can set port constraints for some or all selected signals, before setting, the analyzer can list all candidate items, including chip port addresses corresponding to all contact pins in the development board, the user selects one of the port addresses, the analyzer can automatically generate port constraint statements supported by the layout and wiring tool, and if the user sets repeated chip port addresses for some signal or some chip port address is occupied, the analyzer can prompt error information and guide the user to cancel the operation;

and a sixth step: after the user confirms, the analyzer automatically generates new netlist files and port constraint files according to the operations of the fourth step and the fifth step, and informs the user of the disk paths of the files;

the seventh step: after finding a new netlist file and a new port constraint file, a user operates layout wiring to generate a code stream, and the code stream is downloaded to a development board;

eighth step: and the user captures and grabs the real-time signal of the chip through the oscilloscope.

Through the steps, the analyzer helps a user to count all internal signals and available port constraint addresses, automatically modify the netlist and automatically generate the port constraint file, and the user only needs to click and select the signals and the ports suitable for the user in the data provided by the analyzer, so that the method is very simple and convenient, and can more quickly verify the design of the user.

As shown in FIG. 2, which is a main interface for actual operation of the analyzer, "vqm" in the figure is actually a netlist file after logic synthesis, and "physical constraint file" is actually a port constraint file. Fig. 3 shows an operation interface for adding port constraints to the analyzer.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An implementation method of an online logic analyzer based on signal automatic pulling is characterized by comprising the following steps:

opening a logic analyzer, and reading in the synthesized netlist file;

selecting internal signals of one or more netlists by a user;

2. The method of claim 1, wherein when the user selects the internal signals of one or more netlists, if the user selects the repeated internal signals, the logic analyzer will prompt a "signal repeat" error message and guide the user to cancel the operation.

3. The method of claim 1, wherein the step of setting port constraints for some or all selected signals is performed by the user, and before setting the port constraints, the logic analyzer lists all candidates, including chip port addresses corresponding to all pins in the development board, and selects one of the port addresses, and the logic analyzer automatically generates a port constraint statement supported by the place and route tool.

4. The method of claim 3, wherein if the user sets a duplicate chip port address for a signal or a chip port address is occupied, the logic analyzer will prompt an error message and direct the user to cancel the operation.