CN112615609A - Reset circuit with automatic watchdog switching period - Google Patents
Reset circuit with automatic watchdog switching period Download PDFInfo
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- CN112615609A CN112615609A CN202011278236.3A CN202011278236A CN112615609A CN 112615609 A CN112615609 A CN 112615609A CN 202011278236 A CN202011278236 A CN 202011278236A CN 112615609 A CN112615609 A CN 112615609A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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Abstract
The invention discloses a reset circuit capable of automatically switching watchdog periods, which belongs to the field of power management and comprises a reference module, a voltage sampling module, a comparator, a watchdog counting module, a logic control module and an output module. The reference module provides a reference voltage irrelevant to the working temperature and the voltage for the reset circuit; the voltage sampling module provides sampling voltage to the reset circuit; the comparator judges the logic relation between the power supply voltage and a preset value; the watchdog counting module is mainly used for counting input clock signals and generating related logic control signals; the clock signal is generated by a clock module in the reset circuit or is provided externally; the logic control module logically combines the logic signals generated by other modules to obtain corresponding control signals and simultaneously obtains output control signals; the output module sets the output mode of the reset end to open-drain or push-pull; the reset level is set to a high or low level while enhancing the output driving capability.
Description
Technical Field
The invention relates to the technical field of power supply management, in particular to a reset circuit capable of automatically switching watchdog periods.
Background
With the continuous improvement of the integration level of the chip, the capability of integrating the complex module by a single chip is enhanced. The power-on reset circuit is an indispensable component in the system, and provides a chip internal reset signal at the initial stage of the system to ensure that the whole system can be normally started. The main function of power supply monitoring is to check whether the power supply voltage meets the set requirements to ensure that the system operates under a reliable premise. The main function of the watchdog reset is to prevent the program from running away and causing system damage. Such watchdog resets with voltage monitoring are widely used. However, in the actual use process, the time length from power-on to stability of the system or the time length from the power-on to the normal recovery after the power supply voltage has severe disturbance is often much longer than the counting time of the normal working watchdog, and the two times are generally more than one order of magnitude, so that the two times cannot be mutually compromised. The invention aims to solve the contradiction between the long time from the serious disturbance of the system on power-on or power supply voltage to the system stabilization and the short counting time of the traditional watchdog.
Disclosure of Invention
The invention aims to provide a reset circuit with an automatic watchdog switching period, which is used for solving the problem that the counting time of a system is longer than that of a traditional watchdog in the power-on process or the time from the serious disturbance of a power supply voltage to the system stabilization.
In order to solve the above technical problem, the present invention provides a reset circuit with an automatic watchdog switching period, comprising:
the reference module is used for providing a reference voltage irrelevant to the working temperature and the power supply voltage VCC for the whole circuit;
the voltage sampling module is used for providing sampling voltage for the reset circuit;
the comparator is used for judging the logic relation between the power supply voltage and a preset value;
the watchdog counting module counts the input clock signals and generates related logic control signals;
the logic control module is used for logically combining the logic signals generated by other modules to obtain corresponding control signals and simultaneously obtaining output control signals;
the output module sets the output mode of the reset end to be open-drain or push-pull; the reset level is set to a high or low level while enhancing the output driving capability.
Alternatively, the clock signal is generated by a clock module inside the reset circuit, or is externally provided.
Optionally, the voltage sampling module provides a sampling voltage to a non-inverting input terminal of the comparator, and the reference module provides a reference voltage to an inverting input terminal of the comparator;
the first input end of the logic control module is connected with the output end of the comparator; the second input end is connected with an external input signal in; the third input end is connected with the output end of the watchdog counting module;
the first output end of the logic control module is connected with the input end of the output module; the second output end is connected with the input end of the clock module; the third output end is connected with the second input end of the watchdog counting module;
the first input end of the watchdog counting module is connected with the clock signal generated by the clock module.
Optionally, the watchdog counting module comprises two counters, gates s 1-s 3 and a D trigger; the two counters are respectively a first counter and a second counter, and the corresponding counting periods are respectively T1 and T2;
clk of the first counter is connected with the output end of the gate s1, reset is connected with a reset signal reset1, the output end of the first counter is connected with the first input end of an OR gate, and the second input end of the OR gate is connected with a signal in 3;
clk of the second counter is connected with the output end of the gate s2, reset is connected with a reset signal reset2, and the output end is the output end of the watchdog counting module;
the sel terminal signal q of the gate s2 is gated to the sel terminal of the gate s 1; the output end of the gate s3 is connected with the first input end of a NOR gate, and the second input end of the NOR gate is connected with the signal in 2;
clk of the D trigger is connected with the output end of the OR gate, D is connected with a power supply voltage VCC, reset is connected with the output end of the NOR gate, and an output end signal q is grounded through a megaohm-level resistor.
Optionally, the counting period of the first counter is in the order of minutes, and the counting period of the second counter is set according to the running time.
Optionally, the sampling voltage provided by the voltage sampling module is obtained by dividing voltage through a resistor, and is directly proportional to the power supply voltage VCC.
Optionally, the input and output signals in the reset circuit are both a set of semaphores, not a single signal.
The reset circuit with the watchdog period capable of being automatically switched comprises a reference module, a voltage sampling module, a comparator, a watchdog counting module, a logic control module and an output module. The reference module provides a reference voltage irrelevant to the working temperature and the power supply voltage VCC for the reset circuit; the voltage sampling module provides sampling voltage to the reset circuit; the comparator judges the logic relation between the power supply voltage and a preset value; the watchdog counting module is mainly used for counting input clock signals and generating related logic control signals; the clock signal is generated by a clock module in the reset circuit or is provided externally; the logic control module obtains a corresponding control signal through logic combination of logic signals and obtains an output control signal at the same time; the output module sets the output mode of the reset end to open-drain or push-pull; the reset level is set to a high or low level while enhancing the output driving capability.
The invention has the following beneficial effects:
(1) a counter with longer counting time is added on the basis of the traditional watchdog counter, so that the system has enough time to reach a stable state during power-on and large-disturbance processes;
(2) only through the 1-from-2 selector and the D trigger, the automatic switching of two watchdog counters is realized, and only one counter is in a working state at any time;
(3) when the circuit is powered on or the system voltage VCC is greatly disturbed to recover the stable process of the system voltage VCC, the system firstly switches on the counting mode of the watchdog counter with longer counting time, and switches to the counting mode of the traditional watchdog counter after the system is ensured to be stable.
Drawings
FIG. 1 is a block diagram of a reset circuit with an automatic watchdog switching cycle according to the present invention;
FIG. 2 is a schematic view of a watchdog counting module;
fig. 3 is a flow chart of the operation of the reset circuit.
Detailed Description
The reset circuit with an automatic watchdog switching period according to the present invention will be described in detail with reference to the accompanying drawings and embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
In the invention, VCC is power voltage relative to the internal module of the reset circuit; with respect to the outside of the reset circuit, VCC is the system voltage. The invention provides a reset circuit with an automatic watchdog switching period, which is structurally shown in figure 1 and comprises a reference module, a voltage sampling module, a comparator, a watchdog counting module, a logic control module and an output module. The reference module provides a reference voltage irrelevant to the working temperature and the power supply voltage VCC for the reset circuit; the voltage sampling module provides sampling voltage to the reset circuit; the comparator judges the logic relation between the power supply voltage and a preset value; the watchdog counting module is mainly used for counting input clock signals and generating related logic control signals; the clock signal is generated by a clock module in the reset circuit or is provided externally; the logic control module obtains corresponding control signals by logically combining logic signals generated by other modules and obtains output control signals at the same time, wherein the other modules refer to a comparator module, a watchdog counting module and an external input module; the output module sets the output mode of the reset end to open-drain or push-pull; the reset level is set to a high or low level while enhancing the output driving capability.
With reference to fig. 1, the voltage sampling module provides a sampling voltage to the non-inverting input of the comparator, and the reference module provides a reference voltage to the inverting input of the comparator; the first input end of the logic control module is connected with the output end of the comparator; the second input end is connected with an external input signal in; the third input end is connected with the output end of the watchdog counting module; the first output end of the logic control module is connected with the input end of the output module; the second output end is connected with the input end of the clock module; the third output end is connected with the second input end of the watchdog counting module; the first input end of the watchdog counting module is connected with the clock signal generated by the clock module. The input and output signals in the reset circuit are a group of semaphores, not single signals. The sampling voltage provided by the voltage sampling module is obtained by dividing voltage through resistors and is in direct proportion to the power voltage.
FIG. 2 is a schematic structural diagram of the watchdog counting module, which includes two counters, gates s 1-s 3 and a D flip-flop; the two counters are respectively a first counter and a second counter, and the corresponding counting periods are respectively T1 and T2; clk of the first counter is connected with the output end of the gate s1, reset is connected with a reset signal reset1, the output end of the first counter is connected with the first input end of an OR gate, and the second input end of the OR gate is connected with a signal in 3; clk of the second counter is connected with the output end of the gate s2, reset is connected with a reset signal reset2, and the output end is the output end of the watchdog counting module; the sel terminal signal q of the gate s2 is gated to the sel terminal of the gate s 1; the output end of the gate s3 is connected with the first input end of a NOR gate, and the second input end of the NOR gate is connected with the signal in 2; clk of the D trigger is connected with the output end of the OR gate, D is connected with a power supply voltage VCC, reset is connected with the output end of the NOR gate, and an output end signal q is grounded through a megaohm-level resistor. The counting period T1 of the first counter is long and can reach the minute level, and the counting period T2 of the second counter is set according to the running time. When the voltage VCC is larger than the set voltage value at the time of power-on, the watchdog counting module starts to work, the first counter starts to count, because the time T1 is long enough to ensure that the system voltage transits from the power-on state to the stable state, and the counting period of the watchdog counting module is switched from T1 to T2 after the system voltage is stable.
When the system voltage is stabilized, it must be ensured that the second counter is working normally, and the first counter does not affect the performance of the reset circuit. This condition can be achieved by controlling the input clock signal of the watchdog counting module. Due to the 1-out-of-2 controller, only one counter can work at any time. The other counter stops operating because there is no input clock signal. And meanwhile, the D trigger is self-locked, and the clock of the watchdog counting module is ensured to be T2 after the D trigger is stabilized. If the system voltage suddenly has serious voltage disturbance under the stable condition, the D trigger resets and turns off the second counter. After the system voltage recovers to be stable, the power-on process described in the previous paragraph is repeated, and the specific flow is shown in fig. 3.
The voltage monitoring function: and respectively connecting a reference voltage signal generated by the reference module and a sampling voltage signal obtained by the voltage sampling module to two input ends of the comparator, and judging the state of the output level of the comparator to know whether the power supply voltage meets the setting requirement of the voltage of the integral reset circuit. The resulting output signal is then connected to the input of the logic control module. Only if VCC meets the set voltage requirement, the circuit can work normally.
Watchdog count switching function: in FIG. 2, the clk signal is provided by the clock module, and the logic control module controls the reset1, reset2, in1, in2, in3 signals. After power-on, since the pull-down resistance signal D toggles the output signal q to a low level, the output signal of the gate s3 is the signal in1, which is a power-on reset signal. The pulse signal resets the D flip-flop, again ensuring that the output signal q is low. When the signal q is low, the first counter starts counting, and the second counter is in an off state. When the first counter finishes counting, the output of the first counter generates a rising edge, and the output signal q of the D trigger changes to high level. At this time, the first counter is turned off, the second counter starts counting, and the conventional watchdog working mode is entered. Meanwhile, the reset signal of the D trigger is also switched to a fixed low level, and the D trigger completes self-locking. After the circuit is working normally, the first counter is turned off, and if and only if VCC has a serious disturbance, the comparator is operated, the signal in2 triggers the D flip-flop to reset, and the first counter can start counting again.
To meet the design requirements, the input signal in3 is taken as the highest priority signal in the present invention. When the input signal in3 shows a valid signal, the first counter is directly turned off, and the second counter is turned on to count; if the highest priority is not required, the signal in3 may be tied high. A manual reset signal is typically used as the control signal for in 3.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (7)
1. A reset circuit having an automatically switching watchdog period, comprising:
the reference module is used for providing a reference voltage irrelevant to the working temperature and the power supply voltage VCC for the whole circuit;
the voltage sampling module is used for providing sampling voltage for the reset circuit;
the comparator is used for judging the logic relation between the power supply voltage and a preset value;
the watchdog counting module counts the input clock signals and generates related logic control signals;
the logic control module is used for logically combining the logic signals generated by other modules to obtain corresponding control signals and simultaneously obtaining output control signals;
the output module sets the output mode of the reset end to be open-drain or push-pull; the reset level is set to a high or low level while enhancing the output driving capability.
2. The reset circuit with an automatically switching watchdog period of claim 1, wherein the clock signal is generated by a clock module internal to the reset circuit or provided externally.
3. The reset circuit with an automatically switching watchdog period according to claim 2, wherein said voltage sampling module provides a sampled voltage to a non-inverting input of said comparator, said reference module provides a reference voltage to an inverting input of said comparator;
the first input end of the logic control module is connected with the output end of the comparator; the second input end is connected with an external input signal in; the third input end is connected with the output end of the watchdog counting module;
the first output end of the logic control module is connected with the input end of the output module; the second output end is connected with the input end of the clock module; the third output end is connected with the second input end of the watchdog counting module;
the first input end of the watchdog counting module is connected with the clock signal generated by the clock module.
4. The reset circuit with an automatically switching watchdog period according to claim 3, wherein said watchdog counting module comprises two counters, gates s 1-s 3, and a D flip-flop; the two counters are respectively a first counter and a second counter, and the corresponding counting periods are respectively T1 and T2;
clk of the first counter is connected with the output end of the gate s1, reset is connected with a reset signal reset1, the output end of the first counter is connected with the first input end of an OR gate, and the second input end of the OR gate is connected with a signal in 3;
clk of the second counter is connected with the output end of the gate s2, reset is connected with a reset signal reset2, and the output end is the output end of the watchdog counting module;
the sel terminal signal q of the gate s2 is gated to the sel terminal of the gate s 1; the output end of the gate s3 is connected with the first input end of a NOR gate, and the second input end of the NOR gate is connected with the signal in 2;
clk of the D trigger is connected with the output end of the OR gate, D is connected with a power supply voltage VCC, reset is connected with the output end of the NOR gate, and an output end signal q is grounded through a megaohm-level resistor.
5. The reset circuit with an automatically switching watchdog period according to claim 1, wherein a count period of the first counter is in the order of minutes and a count period of the second counter is set according to a run time.
6. The reset circuit with an automatically switching watchdog period according to claim 1, wherein the sampling voltage provided by the voltage sampling module is obtained by dividing a voltage through a resistor and is proportional to the power voltage VCC.
7. The reset circuit with an automatically switching watchdog period of claim 1, wherein each module in the reset circuit and external input and output signals are a set of semaphores, not a single signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011278236.3A CN112615609B (en) | 2020-11-16 | 2020-11-16 | Reset circuit with automatic watchdog switching period |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011278236.3A CN112615609B (en) | 2020-11-16 | 2020-11-16 | Reset circuit with automatic watchdog switching period |
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| CN112615609B CN112615609B (en) | 2022-08-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115459565A (en) * | 2022-11-10 | 2022-12-09 | 成都智融微电子有限公司 | State switching control device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7173493B1 (en) * | 2003-12-19 | 2007-02-06 | Cypress Semiconductor Corp. | Range controller circuit and method |
| CN101710296A (en) * | 2009-11-27 | 2010-05-19 | 广州从兴电子开发有限公司 | Watchdog circuit |
| CN106648951A (en) * | 2016-12-29 | 2017-05-10 | 广州周立功单片机科技有限公司 | Watchdog control circuit and watchdog application circuit |
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2020
- 2020-11-16 CN CN202011278236.3A patent/CN112615609B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7173493B1 (en) * | 2003-12-19 | 2007-02-06 | Cypress Semiconductor Corp. | Range controller circuit and method |
| CN101710296A (en) * | 2009-11-27 | 2010-05-19 | 广州从兴电子开发有限公司 | Watchdog circuit |
| CN106648951A (en) * | 2016-12-29 | 2017-05-10 | 广州周立功单片机科技有限公司 | Watchdog control circuit and watchdog application circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115459565A (en) * | 2022-11-10 | 2022-12-09 | 成都智融微电子有限公司 | State switching control device |
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| CN112615609B (en) | 2022-08-02 |
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