CN101141126A

CN101141126A - Soft reset device of integrated circuit chip

Info

Publication number: CN101141126A
Application number: CNA2007101631839A
Authority: CN
Inventors: 王洋
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2007-10-16
Filing date: 2007-10-16
Publication date: 2008-03-12

Abstract

The invention relates to a soft reset device for integrated circuit chip and is inserted into the integrated circuit chip. The utility model consists of a ring shape oscillator(11), a reset pulse signal that has certain cycle and meets the reset request under the action of trigger signal according to the software control; a first edge detecting unit(12) that receives the reset pulse signal and outputs reset ending signal, a reset module(13) that receives the reset ending signal and outputs reset signal to start-up reset while outputs reset closing signal to the ring shape oscillator to stop the output of the reset pulse signal. The static power consumption of the module is around zero; the area is small and can prevent the filtering of high frequency input signal caused by the low pass property of the RC; compatible to meet more than one trigger method; clear design concept and can be realized by standard CMOS technique approved by tape-out inspection needless of adding mask.

Description

Soft reset device of integrated circuit chip

Technical Field

The invention relates to an integrated circuit, in particular to a soft reset device of an integrated circuit chip.

Background

With the widespread development of CMOS integrated circuits, integrated circuit chips operate at faster and faster speeds, which puts higher and higher demands on clock signals that drive the entire circuit to operate. For a high-speed digital circuit working under the frequency of hundreds of megahertz, the stability of a clock signal directly influences whether the circuit can work normally. When high-frequency signals are transmitted, the high-frequency signals are influenced by stray distributed capacitance, inductance and the like, and the accurate work of the circuit along with a clock is seriously influenced by the distortion and the drift of the clock signals. There is often a need for a reset circuit in an integrated circuit that automatically resets the chip when the system enters a faulty mode of operation but does not require the power to be turned off or reset to empty all data. The soft reset circuit is very critical in the design of a plurality of CMOS mixed signal circuits, the trouble of manual operation is avoided, the whole equipment can not be initialized again due to the reset of hardware, and a large amount of time is delayed, so that the soft reset circuit has very extensive and important functions in an integrated circuit.

The soft reset structure generally adopts a fully-customized structure, because the digital processing circuit needs different reset time lengths under different conditions, which is a disadvantageous factor for the popularization of the digital processing circuit; in addition, the partially mixed signal design may require several reset signals of different pulse lengths for the same port, thereby achieving different reset results. The general reset signal is realized by a 'number buffer' method in the internal design of a chip, but the method is limited by an external clock and the area of the chip, and the control part of the frequency division circuit also needs to be reset because the system is in an error state; the invention adopts the oscillator structure to get rid of the trouble of an external clock and reduce the area of the module.

The traditional chip reset circuit is generally used in an off-chip environment and comprises a soft or hard reset circuit, wherein the reset circuit has only one reset function and cannot determine whether to clear data content in a register; meanwhile, the process of resetting the chip comprises the following steps: chip identification is abnormal; sending out an instruction to the outside and preparing the chip for resetting by itself; the external soft reset circuit receives the instruction and delays the time according to the specific reset preparation of the chip and then sends out a reset signal; thus, it is slow to reset, intended to preserve the necessary register states or data, and consumes a lot of power, cannot be integrated into the chip, and is not suitable for the high-speed integrated circuit applications of the present stage.

In addition, the chinese patent application "clock generation circuit", application number 03178666.9, mainly describes a programmable clock generation circuit; the invention relates to a ring oscillator with stable frequency, which is applied to China's invention patent application No. 03816891.X, and mainly describes a ring oscillator designed by adopting a current mode, and a feedback structure is adopted to stabilize the ring oscillator.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a soft reset device of an integrated circuit chip, which can get rid of the trouble of an external clock, reduce the area of a module, reduce power consumption and properly accelerate the reset speed.

The above-mentioned technical problem of the present invention is solved by providing a soft reset device for an integrated circuit chip, which is built in the integrated circuit chip, comprising:

the ring oscillator outputs a reset pulse signal with a certain period meeting the reset requirement under the action of the trigger signal according to software control;

the edge detection unit receives and outputs a reset ending signal according to the reset pulse signal;

and the reset module receives the reset ending signal, outputs a reset signal to start resetting, and simultaneously outputs a reset closing signal to the ring oscillator to stop outputting the reset pulse signal.

According to the soft reset device provided by the invention, the ring oscillator is mainly formed by end-to-end ring connection of one or more delay units.

According to the soft reset device provided by the invention, the number of the delay units is controlled by an electronic switch group and software which are connected with the tail part of each delay unit and the head part of the first delay unit, namely: the frequency of the oscillator is changed through an inverter structure and a programmable mode, and the requirements of the same port on different complex bit lengths are met.

According to the soft reset device provided by the invention, the electronic switch is an amplifier, so that the insufficient gain of the delay unit is made up, and the whole loop meets the oscillation condition.

According to the soft reset device provided by the invention, the ring oscillator is a current mode ring oscillator, the delay unit comprises a bias of a mirror current source, and a smaller current can be obtained through current mirror replication, so that the same time constant can be achieved by using a smaller capacitor, and the soft reset device has a smaller area than a traditional RC structure.

According to the soft reset device provided by the invention, the oscillator structure can be configured by programming, so that the frequency of the oscillator can be changed, and the requirements of the same port for different reset lengths are met.

According to the soft reset device provided by the invention, the loop gains of the one or more delay units which are connected end to end in a loop mode are larger than 1 at the oscillation frequency of the ring oscillator, and the oscillation condition is met.

According to the soft reset device provided by the invention, the device further comprises a second edge detection unit (optional) connected with the ring oscillator trigger signal input end, so that the level trigger mode of the ring oscillator can be converted into edge trigger.

According to the soft reset device provided by the invention, the edge detection unit can be either a rising edge detection unit or a falling edge detection unit.

According to the soft reset device provided by the invention, the edge detection unit or the ring oscillator is a field effect transistor circuit, so that the power consumption can be reduced.

The soft reset device provided by the invention is arranged in a chip, and compared with the prior art, the soft reset device comprises: the static power consumption of the module is close to zero (the bias part is not counted); the area is small, the RC circuit saves the area compared with the traditional RC circuit with the same function, and the high-frequency input signal can be prevented from being filtered due to the low-pass characteristic of the RC; the compatibility is strong, and various triggering modes are met; the design idea is clear, the realizability is good, the design can be realized by adopting a standard CMOS process through the wafer casting verification at present, and no additional mask design is needed.

Drawings

The invention is further described in detail below with reference to the figures and the specific embodiments.

FIG. 1 is a first block diagram of the overall circuit of a soft reset device;

FIG. 2 is a second block diagram of the overall circuit of the soft reset device;

FIG. 3-1 is a circuit block diagram of a ring oscillator in an embodiment of the present invention;

fig. 3-2 is a circuit diagram of an oscillating unit in the ring oscillator shown in fig. 3-1.

FIGS. 4-1, 4-2 and 4-3 are schematic structural views of a Falling edge detector in the embodiment of the present invention;

fig. 5 is a diagram illustrating simulation results of current source start-up in an embodiment of the invention.

Figure 6 is a schematic diagram of the structure of a programmable ring oscillator extension in an embodiment of the present invention.

Detailed Description

First, the apparatus of the present invention is explained:

fig. 1 shows a circuit structure of a soft reset device according to the present invention, which mainly includes three components: the first edge detection unit 12 includes (a) an oscillator 11 and a bias circuit thereof, (b) a first edge detection unit 12 and a bias circuit thereof, and (c) a reset module 13. The oscillator can be designed to have large phase shift, weak noise can generate oscillation, an input enabling port EN is arranged, an output signal port of the oscillator is SWRESET, and reset pulse signals are output. The next receiving is an edge detection unit, the input is an SWRESET signal, the module output signal is an SWRST _ CLR _ B signal, and the edge detection unit monitors the change of the SWRESET signal and gives a reset ending signal at an SWRST _ CLR _ B signal end; the next receiving is a RESET module, the input signal is SWRST _ CLR _ B, and the output is a RESET closing Disable and RESET signal, so that the system is informed of the completion of the RESET. The bias section provides a bias operating current for the oscillator and the falling edge detection structure. The structure can change the biased current or change the oscillation period of the oscillator according to the actual reset requirement to realize different reset periods. Generally, the pulse width of the reset pulse signal is not required to be very accurate, and the accuracy of the reset pulse width of the present invention is mainly determined by the accuracy of the oscillator. In addition, the input signal of the present invention can be adapted to various needs, including two ways of edge triggering and level triggering, and the second edge detecting unit 21 in fig. 2 needs to be added on the input side by using edge triggering.

The second step, the present invention will be described in detail with reference to specific examples:

in order to complete the reset signal with the pulse width of lus, a ring oscillator structure composed of 5 delay units is assumed, the delay period of each delay unit is 200ns, each unit is composed of 9 mos tube circuits, and the starting of the current source is realized through an enable signal input from the outside.

According to the "barkhausen criterion", the negative feedback oscillator array must satisfy two conditions:

|H(jω ₀ )|≥1

∠H(jω ₀ )＝180°

let the final transfer function be expressed as

Considering that the final phase shift is 180 degrees to oscillate, i.e. 36 degrees per stage, given by

Then there is ω _OSC ＝0.727ω ₀

Minimum voltage gain per stage is required to make the loop gain at ω _OSC Is equal to 1.

A0=1.24 can be obtained

Therefore, the low-frequency gain of each stage of circuit required by the five-stage oscillator is 1.24, the oscillation frequency is 500KHz, and the 3db bandwidth of each stage of circuit is 688KHz.

As shown in fig. 2, the structure of the soft reset apparatus is simplified, wherein the OSC has a ring oscillator structure, and each oscillating unit is shown in fig. 3; the first inverter structure in the unit can not only shape but also increase phase shift and improve circuit reliability. As shown in fig. 4-1, 4-2 and 4-3, the Falling edge detector employs a conventional logic detection mode, and its internal elements are similar to the internal delay elements of the ring oscillator OSC, and the MOS transistors used only as capacitors have different sizes; the logic implementation refers to the following expression:

(assume that the input signal is A)

All logic circuits are at a certain level when the whole reset module is not started, and the static power consumption is zero (the bias is not counted). The bias circuit in the figure is designed in a MOS voltage division mode connected in a diode mode, and the requirement can be met under the condition of not high precision requirement

The apparatus of the present invention will be described in further detail with reference to specific embodiments.

As shown in fig. 1, the front four backward oscillating unit structures and the rear expanded backward oscillating unit structure form a ring oscillator 11; considering that the ring oscillator structures shown in fig. 3-1 and 3-2 have a low gain in the middle delay structure, an inverting amplifier is added in each of the front and rear stages to increase the gain of each of the inverted oscillation units, so that the satisfaction of the "barkhausen criterion" ensures that the system can start oscillation. The bias circuit mainly provides reference current designed by a delay unit adopting a switch current source structure, and can obtain smaller current through current mirror replication, so that the same time constant can be achieved by adopting smaller capacitance, and the bias circuit has a smaller area than a traditional RC structure; in addition, the edge triggering mode is also supported, and the traditional RC structure may filter out smaller triggering edges due to the low-pass characteristic of the traditional RC structure. The transistor which is used for current mirror copy in the oscillating unit works in a saturation region, and the switching tube works in a linear region and a cut-off region.

The programmable approach of fig. 6 can be adopted to meet the requirement of different reset lengths of the same port. By increasing or decreasing the number of delay cells, larger or smaller time constants may be obtained, resulting in higher or lower delay sizes. Due to the existence of the inverter of each oscillation unit, the programming mode is basically not limited by the number and can be increased almost without limit.

In the design of the edge triggering mode, a rising edge triggering mode and a falling edge triggering mode can be adopted, a double-edge triggering mode can also be adopted, a rising/falling edge detection circuit needs to be added at an input stage, the realization mode of the circuit is similar to the structure of a falling edge circuit, and only the last logic gate is changed.

The soft reset block formed by the circuit of fig. 1 has two stable states:

in state 1, the output node swreset is at a low level (this value may be changed according to actual requirements, and it is assumed that the low level reset is invalid), and the ring oscillator is in an open-loop state, and each unit is in a dc state, and a transistor releasing the redundant payload is arranged at the output node swreset to increase the turn-off time of the ring oscillator.

In the state 2, the output node swreset is a high level pulse, the node EN is a transistor which is mentioned in the low level stop state 1 and is accelerated to be closed, at this time, the ring oscillator starts to work, a high level pulse of the first oscillation is generated at the output node, even after the falling edge detector detects the falling edge pulse, the ring oscillator is closed by resetting a specific register to input EN to the high level, and meanwhile, redundant residual charges are quickly released.

Claims

1. A soft reset device of an integrated circuit chip, which is built in the integrated circuit chip, comprises:

the ring oscillator (11) outputs a reset pulse signal with a certain period meeting the reset requirement under the action of a trigger signal according to software control;

a first edge detection unit (12) which receives the reset pulse signal and outputs a reset end signal;

and the reset module (13) receives the reset ending signal, outputs a reset signal to start resetting, and simultaneously outputs a reset closing signal to the ring oscillator to stop outputting the reset pulse signal.

2. The soft reset apparatus according to claim 1, wherein the ring oscillator (11) is mainly composed of one or more delay units connected end to end in a ring.

3. The soft reset apparatus of claim 2, wherein the number of the delay units is controlled by the electronic switch group and the software connected to the tail of each delay unit and the head of the first delay unit.

4. A soft-reset apparatus according to claim 3, wherein the electronic switch is an amplifier.

5. A soft reset device according to claim 2 wherein the ring oscillator (11) is a current mode ring oscillator and the delay element comprises a bias of a mirror current source.

6. The soft-reset apparatus of claim 5, wherein the frequency of the ring oscillator is programmable.

7. The soft-reset apparatus of claim 2, wherein the loop gain of the one or more delay cells looped end-to-end is greater than 1 at a ring oscillator oscillation frequency.

8. A soft reset device according to claim 1 further comprising a second edge detector unit (21) connected to the ring oscillator trigger signal input.

9. A soft reset device according to claim 1 or 8, wherein the edge detection unit (12 or 21) is a rising edge detection unit or a falling edge detection unit.

10. A soft reset device according to claim 1 or 8 wherein the edge detector cell (12 or 21) or ring oscillator (11) is a field effect transistor circuit.