CN112615556A - Multi-level inverter and control method thereof - Google Patents

Multi-level inverter and control method thereof Download PDF

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Publication number
CN112615556A
CN112615556A CN202011375682.6A CN202011375682A CN112615556A CN 112615556 A CN112615556 A CN 112615556A CN 202011375682 A CN202011375682 A CN 202011375682A CN 112615556 A CN112615556 A CN 112615556A
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China
Prior art keywords
inverter
bridge arm
circuit
controlling
inverter circuit
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CN202011375682.6A
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Chinese (zh)
Inventor
蒋正东
卢茂勇
黄朱勇
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Huawei Digital Power Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN202011375682.6A priority Critical patent/CN112615556A/en
Publication of CN112615556A publication Critical patent/CN112615556A/en
Priority to PCT/CN2021/112418 priority patent/WO2022110904A1/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
    • H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
    • H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
    • H02J9/062—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems for AC powered loads
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Business, Economics & Management (AREA)
  • Emergency Management (AREA)
  • Inverter Devices (AREA)

Abstract

The application provides a multi-level inverter, a control method of the multi-level inverter and an uninterruptible power supply, and relates to the technical field of power electronics. The multi-level inverter comprises a converter bridge arm, an inverter circuit and a controller. The positive input port of the inverter circuit is connected with the positive input port of the multilevel inverter, the negative input port of the inverter circuit is connected with the negative input port of the multilevel inverter, and the output end of the inverter circuit is connected with the positive output port of the multilevel inverter. The converter bridge arm comprises an upper half bridge arm and a lower half bridge arm, and the midpoint of the bridge arm is connected with a negative output port of the multi-level inverter. The controller controls the upper half-bridge arm to be switched off and the lower half-bridge arm to be switched on in a positive output period of the inverter circuit; and controlling the upper half-bridge arm to be switched on and the lower half-bridge arm to be switched off in a negative output period. By the adoption of the scheme, the number of the switching tubes used in the inverter circuit can be reduced by half, and the cost of the multi-level inverter is reduced.

Description

Multi-level inverter and control method thereof
Technical Field
The present disclosure relates to the field of power electronics technologies, and in particular, to a multi-level inverter, a control method of the multi-level inverter, and an uninterruptible power supply.
Background
An Inverter (Inverter) is a transformer that converts Direct Current (DC) into Alternating Current (AC), and is widely used in uninterruptible power supplies, photovoltaic power generation systems, electric vehicles, and other scenes. The inverter generally comprises an inverter circuit and a resonant circuit, wherein the inverter circuit is used for converting direct current into alternating current, and the resonant circuit is used for converting the alternating current into alternating current with a waveform approximate to a sine curve for alternating current output.
With the continuous development of inverter technology, the application of multilevel inverters is becoming more and more extensive. The multi-level inverter can reduce the voltage drop born by each power device, so that high-voltage and high-power output can be realized by using devices with low voltage withstanding specification, the increase of the level number means that the output voltage waveform of the inverter is improved and the distortion of the output waveform is reduced, the function of the two-level inverter which works at high switching frequency can be realized only by using lower switching frequency, the loss of the power devices is reduced, and the efficiency of the inverter is improved.
Referring to fig. 1 and fig. 2 together, fig. 1 is a schematic diagram of a three-level inverter in which an inverter circuit adopts T-type connection, and fig. 2 is a schematic diagram of an inverter circuit adopting I-type connection.
When the three-level inverter converts a direct current input into a single-phase alternating current output, the inverter circuit 10 of the above two topologies uses four controllable switching tubes. However, as the number of inverter levels increases, the number of controllable switching tubes used by the inverter circuit also increases accordingly.
Referring to fig. 3 and 4 together, fig. 3 is a schematic diagram of a diode-clamped five-level inverter of the prior art, and fig. 4 is a schematic diagram of a flying capacitor five-level inverter circuit of the prior art.
After the number of the levels is increased, the inverter circuit 10 of the two topologies needs to use eight controllable switching tubes, which is doubled compared with a three-level inverter circuit, and so on, as the number of the levels is gradually increased from three, the number of the controllable switching tubes in the inverter circuit is increased in a doubling manner, so that the driving signal is complex, the control difficulty is increased, and the cost of the multi-level inverter is increased due to the fact that a large number of diodes (in a mode of fig. 3) or capacitors (in a mode of fig. 4) are increased.
Disclosure of Invention
In order to solve the technical problems, the application provides a multi-level inverter, a control method of the multi-level inverter and an uninterruptible power supply, so that the number of controllable switching tubes used by the multi-level inverter is reduced, and the cost of the multi-level inverter is reduced.
In a first aspect, the present application provides a multi-level inverter applicable to a single bus system, the multi-level inverter including a converter leg, an inverter circuit, and a controller. The positive input port of the inverter circuit is connected with the positive input port of the multilevel inverter, the negative input port of the inverter circuit is connected with the negative input port of the multilevel inverter, and the output end of the inverter circuit is connected with the positive output port of the multilevel inverter. The converter bridge arm comprises an upper half bridge arm and a lower half bridge arm, wherein the first end of the upper half bridge arm is connected with a positive input port of the multi-level inverter, the second end of the upper half bridge arm is connected with the first end of the lower half bridge arm through a bridge arm midpoint, the second end of the lower half bridge arm is connected with a negative input port of the multi-level inverter, and the bridge arm midpoint is connected with a negative output port of the multi-level inverter. The controller controls the upper half-bridge arm to be switched off and the lower half-bridge arm to be switched on in a positive output period of the inverter circuit; and controlling the upper half-bridge arm to be switched on and the lower half-bridge arm to be switched off in the negative output period of the inverter circuit.
The converter bridge arm of the multi-level inverter switches working states in the positive and negative output periods of the inverter circuit so as to change the potential reference point of the negative output end, and the method specifically comprises the following steps: when the upper half bridge arm of the converter bridge arm is disconnected and the lower half bridge arm of the converter bridge arm is connected, the potential reference point of the negative output end of the multi-level inverter is the negative input port of the inverter circuit; when the upper half bridge arm of the converter bridge arm is switched on and the lower half bridge arm is switched off, the potential reference point of the negative output end of the multi-level inverter is the positive input port of the inverter circuit. And then through changing the reference point of the electric potential, increase the quantity of the level that the multi-level inverter outputs, for example when the multi-level inverter needs to output five levels, the inverter circuit only needs to use three-level topology, when the multi-level inverter needs to output seven levels, the inverter circuit only needs to use five-level topology, therefore, can reduce the quantity of the switch tube that the inverter circuit needs by half with this scheme, has reduced the cost of the multi-level inverter.
The switching tubes used in the inverter circuit and the converter bridge arm of the multilevel inverter can be as follows: one or a combination of plural kinds of Insulated Gate Bipolar Transistors (IGBTs), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), hereinafter referred to as MOS transistors, Silicon Carbide field Effect transistors (SiC MOSFETs), and the like.
With reference to the first aspect, in a first possible implementation manner, the upper half bridge arm of the commutation bridge arm includes a switching tube M1, the lower half bridge arm of the commutation bridge arm includes a switching tube M2, and M1 and M2 are respectively connected in anti-parallel with one diode. The controller controls the M1 to be disconnected and controls the M2 to be closed in a positive output period of the inverter circuit, and at the moment, a potential reference point of a negative output port of the inverter circuit is a negative input port of the multi-level inverter; and in the negative output period of the inverter circuit, the controller controls the M1 to be closed and controls the M2 to be opened, and at the moment, the potential reference point of the negative output port of the inverter circuit is the positive input port of the multi-level inverter.
With reference to the first aspect, in a second possible implementation manner, the multi-level inverter is a five-level inverter, and the inverter circuit includes a first capacitor, a second capacitor, and switching transistors Q1-Q4, where each switching transistor is connected in anti-parallel to a diode. The first end of the first capacitor and the first end of the Q1 are connected with a positive input port of the multilevel inverter, the second end of the first capacitor is connected with the first end of the second capacitor through a first node, the second end of the second capacitor and the second end of the Q2 are connected with a negative input port of the multilevel inverter, the first node is connected with the first end of the Q4, the second end of the Q4 is connected with the second end of the Q3, and the first end of the Q3 is connected with the output end of the inverter circuit. A second terminal of Q1 is connected to the output of the inverter circuit and to a first terminal of Q2.
With reference to the first aspect, in a third possible implementation manner, the controller is configured to, in each positive output period:
firstly, controlling Q1 to be turned off, controlling Q3 to be turned on, and controlling Q2 and Q4 to be alternately turned on within a first preset time; controlling the Q1 and the Q3 to be alternately switched on within a second preset time, controlling the Q2 to be switched off and controlling the Q4 to be switched on; then controlling the Q1 to be turned off, the Q3 to be turned on, and the Q2 and the Q4 to be alternately turned on during the remaining time of each positive output period;
the controller is further configured to, during each of the negative output cycles:
firstly, controlling the Q2 to be turned off within a first preset time, controlling the Q4 to be turned on, and controlling the Q1 and the Q3 to be alternately turned on; controlling the Q2 and the Q4 to be alternately switched on within a second preset time, controlling the Q1 to be switched off and controlling the Q3 to be switched on; the Q2 is then controlled to turn off, the Q4 is controlled to turn on, and the Q1 and Q3 are controlled to turn on alternately for the remainder of each positive output period.
Wherein the first preset time is equal to the remaining time.
With reference to the first aspect, in a fourth possible implementation manner, the inverter circuit of the multilevel inverter includes a first branch, a second branch, and N third branches, where N is a positive integer greater than or equal to 2. The first branch circuit comprises a switching tube Q5, a first end of a Q5 is connected with a positive input port of the inverter circuit, and a second end of a Q5 is connected with an output end of the inverter circuit. The second branch comprises a switching tube Q6, a first end of a Q6 is connected with the output end of the inverter circuit, and a second end of a Q6 is connected with the negative input port of the inverter circuit. Each third branch comprises switching tubes Q7 and Q8, a first end of Q7 is connected to a first end of the third branch, a second end of Q7 is connected to a second end of Q8, and a first end of Q8 is connected to a second end of the third branch.
The first end of the first third branch is connected with the first end of the first branch through a first capacitor, the first end of the Mth third branch is connected with the first end of the (M-1) th third branch through an Mth capacitor, the first end of the Nth third branch is connected with the second end of the second branch through a (N +1) th capacitor, and M is 2, 3, … and N. And second ends of the N third branches are connected with a negative output port of the inverter circuit. Each switching tube included in the inverter circuit is connected with a diode in an anti-parallel mode.
With reference to the first aspect, in a fifth possible implementation manner, the multi-level inverter is a five-level inverter, and the inverter circuit includes a first capacitor, a second capacitor, and switching tubes Q1-Q4, where each switching tube is connected in anti-parallel to a diode. The first end of the first capacitor and the first end of the Q1 are connected with a positive input port of the multilevel inverter, the second end of the first capacitor is connected with the first end of the second capacitor through a first node, the second end of the second capacitor and the second end of the Q4 are connected with a negative input port of the multilevel inverter, the first node is connected with the second end of the Q2, the first end of the Q2 is connected with the second end of the Q1 and the first end of the Q3, and the second end of the Q3 is connected with the first end of the Q4 and an output end of the inverter circuit.
With reference to the first aspect, in a sixth possible implementation manner, the controller is configured to, in each positive output period:
firstly, controlling Q1 to be turned off and Q2 to be turned on within a first preset time, and controlling Q3 and Q4 to be alternately turned on;
controlling Q3 to be switched on and Q4 to be switched off within second preset time, and controlling Q1 and Q2 to be alternately switched on;
then controlling Q1 to be switched off, Q2 to be switched on, and controlling Q3 and Q4 to be alternately switched on in the rest time of the positive output period;
the controller is further configured to, during each negative output cycle:
firstly, controlling Q3 to be switched on and Q4 to be switched off in first preset time, and controlling Q1 and Q2 to be switched on alternately;
controlling Q2 to be switched on and Q1 to be switched off within the second preset time, and controlling Q3 and Q4 to be alternately switched on;
then controlling Q3 to be switched on and Q4 to be switched off in the rest time of the negative output period, and controlling Q1 and Q2 to be switched on alternately;
the first preset time is equal to a remaining time of the positive output period and a remaining time of the negative output period.
With reference to the first aspect, in a seventh possible implementation manner, the inverter circuit includes N inverter bridge arms and a capacitor C1-CNAnd N is greater than or equal to 3.
The upper half bridge arm of each inversion bridge arm comprises a switching tube Q1 and a switching tube Q2, the first end of Q1 is connected with the first end of the inversion bridge arm, the second end of Q1 is connected with the second end of Q2 through the middle point of the bridge arm of the inversion bridge arm, and the first end of Q2 is connected with the second end of the inversion bridge arm;
the first end of the first inverter bridge arm is connected with the positive input port of the inverter circuit and is connected with the second end of the first inverter bridge arm through a capacitor C1;
the first end of the Mth inverter bridge arm is connected with the bridge arm midpoint of the (M-1) th inverter bridge arm, and the second end of the Mth inverter bridge arm passes through a capacitor CMAnd the second ends of the (M-1) th inverter bridge arm are connected, the second end of the Nth inverter bridge arm is connected with a negative input port of an inverter circuit, and M is 2, 3, … and N.
Each switching tube included in the inverter circuit is connected with a diode in an anti-parallel mode.
With reference to the first aspect, in an eighth possible implementation manner, the multilevel inverter further includes a first filter inductor and a first filter capacitor. The first filter inductor is connected between the output end of the inverter circuit and the positive output port of the multi-level inverter; the first filter capacitor is connected between the true output port and the negative output port of the multilevel inverter.
And the resonant circuit formed by the first filter inductor and the first filter capacitor is used for converting the output of the inverter circuit into alternating current with a waveform approximate to a sine curve.
With reference to the first aspect, in a ninth possible implementation manner, the multilevel inverter further includes an AC-DC circuit; the positive input port of the AC-DC circuit is used for connecting AC input, the negative input port of the AC-DC circuit is used for connecting the middle point of a bridge arm, the positive output port of the AC-DC circuit is connected with the positive input port of the inverter circuit, and the negative output port of the DC-DC circuit is connected with the negative input port of the inverter circuit. The AC-DC circuit is used for converting alternating current provided by alternating current input into direct current and transmitting the direct current to the inverter circuit.
With reference to the first aspect, in a tenth possible implementation manner, the structure of the AC-DC circuit is symmetrical to the inverter circuit along the converter bridge arm. By utilizing the AC-DC circuit, the current conversion bridge arm can also realize the offset of power frequency current, thereby reducing the loss of a switching tube of the current conversion bridge arm and improving the efficiency.
With reference to the first aspect, in an eleventh possible implementation manner, the controller is further configured to control an operating state of the AC-DC circuit.
In a second aspect, the present application further provides a control method of a multi-level inverter, for controlling the multi-level inverter, the multi-level inverter being applied to a single bus system, the method comprising the following steps:
controlling the potential of the negative output end of the multi-level inverter to be the potential of the negative input port of the inverter circuit in the positive output period of the inverter circuit of the multi-level inverter;
and in the negative output period of the inverter circuit, controlling the potential of the negative output end of the multi-level inverter to be the potential of the positive input port of the inverter circuit.
According to the method, two levels are additionally added on the basis of the original level quantity output by the inverter circuit by changing the potential reference point. Therefore, the number of switching tubes required by the inverter circuit can be reduced by half, the capacitance required to be used is reduced, and the size and the cost of the multi-level inverter are reduced.
With reference to the second aspect, in a first possible implementation manner, the multi-level inverter further includes a converter bridge arm, where the converter bridge arm includes an upper half bridge arm and a lower half bridge arm, a first end of the upper half bridge arm is connected to the positive input port of the inverter circuit, a second end of the upper half bridge arm is connected to the first end of the lower half bridge arm through a bridge arm midpoint, a second end of the lower half bridge arm is connected to the negative input port of the inverter circuit, and the bridge arm midpoint is connected to the negative output port of the multi-level inverter.
In the positive output period of the inverter circuit of the multi-level inverter, controlling the potential of the negative output end of the multi-level inverter to be the potential of the negative input port of the inverter circuit, specifically comprising:
and controlling the upper half-bridge arm to be switched off and the lower half-bridge arm to be switched on in the positive output period of the inverter circuit.
In the negative output cycle of the inverter circuit, the potential of the negative output end of the multi-level inverter is controlled to be the potential of the positive input port of the inverter circuit, and the method specifically comprises the following steps:
and controlling the upper half-bridge arm to be switched on and the lower half-bridge arm to be switched off in the negative output period of the inverter circuit.
With reference to the second aspect, in a second possible implementation manner, the multi-level inverter is a five-level inverter, and the inverter circuit includes a first capacitor, a second capacitor, and switching transistors Q1-Q4, where each switching transistor is connected in anti-parallel with a diode. The first end of the first capacitor and the first end of the Q1 are connected with a positive input port of the multilevel inverter, the second end of the first capacitor is connected with the first end of the second capacitor through a first node, the second end of the second capacitor and the second end of the Q2 are connected with a negative input port of the multilevel inverter, the first node is connected with the first end of the Q4, the second end of the Q4 is connected with the second end of the Q3, and the first end of the Q3 is connected with the output end of the inverter circuit. The second terminal of the Q1 is connected to the output terminal of the inverter circuit and the first terminal of the Q2, in which case the method comprises the steps of:
during each positive output period:
firstly, controlling Q1 to be turned off, controlling Q3 to be turned on, and controlling Q2 and Q4 to be alternately turned on within a first preset time; controlling the Q1 and the Q3 to be alternately switched on within a second preset time, controlling the Q2 to be switched off and controlling the Q4 to be switched on; then controlling the Q1 to be turned off, the Q3 to be turned on, and the Q2 and the Q4 to be alternately turned on during the remaining time of each positive output period;
during each of the negative output periods:
firstly, controlling the Q2 to be turned off within a first preset time, controlling the Q4 to be turned on, and controlling the Q1 and the Q3 to be alternately turned on; controlling the Q2 and the Q4 to be alternately switched on within a second preset time, controlling the Q1 to be switched off and controlling the Q3 to be switched on; the Q2 is then controlled to turn off, the Q4 is controlled to turn on, and the Q1 and Q3 are controlled to turn on alternately for the remainder of each positive output period.
Wherein the first preset time is equal to the remaining time.
With reference to the second aspect, in a third possible implementation manner, the multi-level inverter is a five-level inverter, and the inverter circuit includes a first capacitor, a second capacitor, and switching tubes Q1-Q4, where each switching tube is connected in anti-parallel to a diode. The first end of the first capacitor and the first end of the Q1 are connected to the positive input port of the multilevel inverter, the second end of the first capacitor is connected to the first end of the second capacitor through a first node, the second end of the second capacitor and the second end of the Q4 are connected to the negative input port of the multilevel inverter, the first node is connected to the second end of the Q2, the first end of the Q2 is connected to the second end of the Q1 and the first end of the Q3, and the second end of the Q3 is connected to the first end of the Q4 and the output end of the inverter circuit, at this time, the method includes the following steps:
during each positive output period:
firstly, controlling Q1 to be turned off and Q2 to be turned on within a first preset time, and controlling Q3 and Q4 to be alternately turned on;
controlling Q3 to be switched on and Q4 to be switched off within second preset time, and controlling Q1 and Q2 to be alternately switched on;
then controlling Q1 to be switched off, Q2 to be switched on, and controlling Q3 and Q4 to be alternately switched on in the rest time of the positive output period;
during each negative output cycle:
firstly, controlling Q3 to be switched on and Q4 to be switched off in first preset time, and controlling Q1 and Q2 to be switched on alternately;
controlling Q2 to be switched on and Q1 to be switched off within the second preset time, and controlling Q3 and Q4 to be alternately switched on;
then controlling Q3 to be switched on and Q4 to be switched off in the rest time of the negative output period, and controlling Q1 and Q2 to be switched on alternately;
the first preset time is equal to a remaining time of the positive output period and a remaining time of the negative output period.
In a third aspect, the present application further provides an Uninterruptible Power Supply (UPS) including the multi-level inverter provided in the foregoing implementation manner, and further including a rectifier, a bypass circuit, and a battery. The first end of the bypass circuit is connected with the input end of the rectifier, and the second end of the bypass circuit is connected with the output end of the multi-level inverter. The input end of the rectifier is connected with an alternating current power supply; the rectifier converts alternating current provided by the alternating current power supply into direct current and transmits the direct current to the battery and the multi-level inverter. The bypass circuit is used to enable the ac power source to directly power the load when enabled. The battery is used for outputting direct current to the multi-level inverter when the rectifier stops working.
By using the multi-level inverter, the number of the levels output by the multi-level inverter is increased by changing the reference point of the potential, so that the number of the switching tubes used in the inverter circuit can be reduced by half, the size and the cost of the multi-level inverter are reduced, and the size and the cost of an uninterruptible power supply are further reduced.
With reference to the third aspect, in a first possible implementation, a rectifier is integrated with a multilevel inverter, the rectifier comprising an AC-DC circuit. The AC-DC circuit and the inverter circuit are symmetrical along the converter bridge arm. The positive input port of the AC-DC circuit is used for connecting an alternating current power supply, the negative input port of the AC-DC circuit is connected with the middle point of a bridge arm of a converter bridge arm, the positive output port of the AC-DC circuit is connected with the positive input port of the inverter circuit, and the negative output port of the DC-DC circuit is connected with the negative input port of the inverter circuit. The AC-DC circuit is used for converting alternating current provided by the alternating current power supply into direct current and then transmitting the direct current to the inverter circuit.
By using the AC-DC circuit symmetrical to the inverter circuit, the current conversion bridge arm can also realize the offset of power frequency current, thereby reducing the loss of a switching tube of the current conversion bridge arm and improving the efficiency.
Drawings
Fig. 1 is a schematic diagram of a three-level inverter with an inverter circuit adopting T-type connection according to the prior art;
fig. 2 is a schematic diagram of a three-level inverter with an inverter circuit adopting an I-type connection according to the prior art;
FIG. 3 is a schematic diagram of a diode-clamped five-level inverter according to the prior art;
FIG. 4 is a schematic diagram of a flying capacitor type five-level inverter circuit according to the prior art;
FIG. 5 is a schematic diagram of an exemplary uninterruptible power supply provided herein;
fig. 6 is a schematic diagram of a multilevel inverter provided in an embodiment of the present application;
fig. 7 is a schematic diagram of another multi-level inverter provided in an embodiment of the present application;
fig. 8 is a schematic diagram of a five-level inverter according to an embodiment of the present disclosure;
FIG. 9 is a timing diagram of control signals according to an embodiment of the present disclosure;
fig. 10A is a first diagram of an operating state of a five-level inverter according to an embodiment of the present disclosure;
fig. 10B is a diagram illustrating a second operating state of the five-level inverter according to the embodiment of the present application;
fig. 10C is a diagram of a third operating state of the five-level inverter according to the embodiment of the present application;
fig. 10D is a diagram of a working state of a five-level inverter according to an embodiment of the present application;
fig. 10E is a diagram illustrating an operating state of a five-level inverter according to an embodiment of the present application;
fig. 10F is a diagram six of an operating state of a five-level inverter according to an embodiment of the present application;
fig. 10G is a seventh diagram of an operating state of the five-level inverter according to the embodiment of the present application;
fig. 10H is an operating state diagram eight of a five-level inverter according to an embodiment of the present application;
fig. 11 is a schematic diagram of another multi-level inverter provided in an embodiment of the present application;
fig. 12 is a schematic diagram of another five-level inverter provided in the embodiments of the present application;
fig. 13A is a first schematic diagram of another five-level inverter according to an embodiment of the present disclosure;
fig. 13B is a second schematic diagram of another five-level inverter according to the embodiment of the present application;
fig. 13C is a schematic diagram three of another five-level inverter provided in the embodiment of the present application;
fig. 13D is a fourth schematic diagram of another five-level inverter provided in the embodiment of the present application;
fig. 13E is a fifth schematic diagram of another five-level inverter provided in the embodiment of the present application;
fig. 13F is a sixth schematic diagram of another five-level inverter provided in the embodiment of the present application;
fig. 13G is a seventh schematic diagram of another five-level inverter provided in the embodiment of the present application;
fig. 13H is a schematic diagram eight of another five-level inverter provided in the embodiment of the present application;
fig. 13I is a ninth schematic diagram of another five-level inverter provided in the embodiment of the present application;
fig. 13J is a schematic diagram ten of another five-level inverter provided in the embodiment of the present application;
fig. 13K is a schematic diagram eleven of another five-level inverter provided in the embodiment of the present application;
fig. 13L is a schematic diagram twelve of another five-level inverter provided in the embodiment of the present application;
fig. 13M is a thirteenth schematic diagram of another five-level inverter provided in the embodiment of the present application;
fig. 13N is a fourteenth schematic diagram of another five-level inverter provided in the embodiment of the present application;
fig. 13O is a schematic diagram fifteen of another five-level inverter provided in the embodiment of the present application;
fig. 13P is a schematic diagram sixteen of another five-level inverter provided in the embodiment of the present application;
fig. 14 is a schematic diagram of another multi-level inverter provided in an embodiment of the present application;
fig. 15A is a schematic diagram of a multi-level inverter according to an embodiment of the present application;
fig. 15B is a schematic diagram of another multi-level inverter provided in the embodiments of the present application;
fig. 16 is a schematic diagram of a control method of a multilevel inverter according to an embodiment of the present disclosure;
fig. 17 is a schematic diagram of another control method of a multi-level inverter according to an embodiment of the present application;
fig. 18 is a schematic diagram of an uninterruptible power supply according to an embodiment of the present disclosure.
Detailed Description
In order to make those skilled in the art better understand the technical solution provided by the embodiments of the present application, an application scenario of the multilevel inverter provided by the present application is first described below.
The multi-level inverter is applied to occasions such as an uninterruptible power supply, a photovoltaic power generation system, an electric vehicle and the like, and in order to output alternating current with a waveform approximate to a sine curve, the number of levels is generally an odd number of three, five, seven or more, so that the symmetry of control signals in a positive output half period and a negative output half period is realized.
The multi-level inverter will be described below as an example of an application of the multi-level inverter to an Uninterruptible Power Supply (UPS).
Referring to fig. 5, a schematic diagram of an exemplary ups provided herein is shown.
The uninterruptible power supply 100 specifically includes: rectifier 101, multilevel inverter 102, battery 103, and bypass circuit 104.
The rectifier 101 is configured to convert ac power provided by the power supply 200 into dc power and transmit the dc power to the battery 103 to charge the battery 103, and convert ac power into dc power and transmit the dc power to the multilevel inverter 102.
The multilevel inverter 102 converts the obtained dc power into ac power and supplies the load 300 of the ups.
The battery 103 is used to output direct current to the multilevel inverter 102 when the rectifier 101 stops operating.
The bypass circuit 104 has one end connected to the input terminal of the rectifier 101 and the other end connected to the output terminal of the inverter 102.
The bypass circuit 104 is used to cause the power supply 200 to directly power the load 300 when enabled.
Specifically, the ups 100 changes the operating state by controlling the states of the main switch S1, the battery switch S2, and the bypass switch S3, as described in detail below.
When the power supply 200 is supplying power and the UPS is not faulted, the main circuit of the UPS is operating, i.e., the main switch S1 is closed and both the battery switch S2 and the bypass switch S3 are open. At this time, the ac power input to the UPS from the power supply 200 supplies power to the load 300 through the rectifier 101 and the multilevel inverter 102, and the battery 103 is charged through the rectifier 101, and the UPS can output a stable voltage to the load 300.
When the input of the power supply 200 fails, the power supply 200 is required to stop supplying power, or the rectifier 101 fails, the load 30 is supplied with power from the battery 103 of the UPS. At this time, the battery switch S2 is closed, the main switch S1 and the bypass switch S3 are both opened, and the multilevel inverter 102 converts the dc power provided by the battery 103 into ac power to supply power to the load 300.
When the multilevel inverter 102 fails, the bypass circuit 104 needs to be started, the bypass switch S3 is turned on, the main switch S1 and the battery switch S2 are both closed, and the power source 200 directly supplies power to the load 300.
In other possible implementations, the previous stage of the multilevel inverter 102 further includes a DC-DC circuit for performing DC conversion on the DC power, for example, the DC-DC circuit is a Boost (Boost) circuit for boosting the DC power and then transmitting the boosted DC power to the multilevel inverter 102.
Each power device in the multilevel inverter 102 (i.e., the controllable switch tube included in the multilevel inverter) suffers lower voltage drop than a conventional two-level inverter, so that a device with a low voltage withstanding specification can be used to realize high-voltage high-power output. The number of levels of the multi-level inverter is increased, the output voltage waveform can be improved, the distortion of the output waveform is reduced, and the switching frequency and the loss of a power device can be reduced. However, when the number of levels of the multi-level inverter is gradually increased from three, the number of power devices required by the multi-level inverter is increased in a double manner, and the size, the control complexity and the cost of the multi-level inverter are greatly increased.
In order to solve the above problems, the present application provides a multi-level inverter, a control method of the multi-level inverter, and an uninterruptible power supply, where the multi-level inverter uses a single bus system, and a converter bridge arm is used to change a reference point of the system to achieve multi-level output, so as to reduce the number of switching devices used in a multi-level inverter circuit and reduce the cost of the multi-level inverter, which is specifically described below with reference to embodiments.
The terms "first", "second", and the like in the description of the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated.
In the present application, unless expressly stated or limited otherwise, the term "coupled" is to be construed broadly, e.g., "coupled" may be a fixed connection, a removable connection, or an integral part; either directly or indirectly through intervening media or devices.
At present, the implementation scheme of the three-level inverter is mature, the number of the used switching tubes is four, and the number is small, and the embodiments of the present application aim to reduce the number of the switching tubes used by the inverter with higher number of levels, that is, the multi-level inverter provided in the following embodiments of the present application refers to an inverter with a number of levels greater than or equal to five, which is not described in detail below, and is specifically described below with reference to the accompanying drawings.
Referring to fig. 6, the figure is a schematic diagram of a multilevel inverter provided in an embodiment of the present application.
The multilevel inverter includes an inverter circuit 10, a converter leg 20, and a controller 40.
The positive input port of the inverter circuit 10 is connected to the positive input port (corresponding to BUS + in the figure) of the multilevel inverter, the negative input port of the inverter circuit 10 is connected to the negative input port (corresponding to BUS-in the figure) of the multilevel inverter, and the output port of the inverter circuit is connected to the positive output port of the multilevel inverter.
The converter bridge arm 20 comprises an upper half bridge arm and a lower half bridge arm, wherein a first end of the upper half bridge arm is connected with a positive input port of the multi-level inverter, a second end of the upper half bridge arm is connected with a first end of the lower half bridge arm through a bridge arm midpoint, a second end of the lower half bridge arm is connected with a negative input port of the multi-level inverter, and the bridge arm midpoint is connected with a negative output port of the multi-level inverter.
The controller 40 controls the upper half bridge arm to be disconnected and the lower half bridge arm to be connected in the positive output period of the inverter circuit 10, and the negative output port is connected to the negative input port of the multi-level inverter through the lower half bridge arm at this time, that is, the potential reference of the negative output port of the inverter circuit 10 at this timeThe point is the negative input port of the multi-level inverter, and the output voltage of the multi-level inverter can be expressed as (V)out+-VBUS-)。
The controller controls the upper half bridge arm to be conducted and the lower half bridge arm to be closed in a negative output period of the inverter circuit 10, the negative output port is connected with the positive input port of the multi-level inverter through the upper half bridge arm at the moment, namely, the potential reference point of the negative output port of the inverter circuit 10 is the positive input port of the multi-level inverter at the moment, and the output voltage of the multi-level inverter can be represented as (V)out+-VBUS+)。
Therefore, by changing the potential reference point, two levels are additionally added on the basis of the number of levels output from the inverter circuit 10. When the inverter circuit 10 uses the three-level topology shown in fig. 1 or fig. 2, the multi-level inverter can achieve five-level output, and when the inverter circuit 10 uses the five-level topology shown in fig. 3 or fig. 4, the multi-level inverter can achieve seven-level output, and so on, the multi-level inverter can output more levels by using the topology with less output levels, so that the number of switching tubes required by the inverter circuit 10 can be reduced by half, the capacitance required to be used is reduced, and the volume and the cost of the multi-level inverter are reduced.
The controller may be an Application Specific Integrated Circuit (ASIC), a Programmable Logic Device (PLD), a Digital Signal Processor (DSP), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), a General Array Logic (GAL), or any combination thereof, and the embodiment of the present invention is not limited thereto.
The inverter circuit 301 includes a switching tube, and the embodiment of the present application does not specifically limit the type of the controllable switching tube, and may be, for example, one or a combination of more of an insulated gate bipolar transistor, a metal oxide semiconductor field effect transistor, a silicon carbide field effect transistor, and the like.
The controller can send a control signal to the switching tube to control the working state of the controllable switching tube. In some embodiments, the control signal is a Pulse Width Modulation (PWM) signal.
In some embodiments, the upper half bridge arm includes a first switch tube M1, and the lower half bridge arm includes a second switch tube M2. Wherein M1 and M2 are connected in anti-parallel with one of the two tubes, respectively. The diode may be a parasitic diode (also referred to as a body diode) of the switching tube, or a separately disposed diode, which is not particularly limited in the embodiments of the present application.
The first end of the M1 is connected with the first end of the upper half bridge arm, the second end of the M1 is connected with the first end of the M2 through the middle point of the bridge arm, the second end of the M2 is connected with the second end of the lower half bridge arm, taking M1 and M2 as MOS tubes, specifically NMOS tubes as examples, the first end is the drain electrodes of M1 and M2, and the second end is the source electrodes of M1 and M2.
The controller controls M1 to be open to turn off the upper half bridge arm and controls M2 to be closed to turn on the lower half bridge arm during the positive output period of inverter circuit 10. The controller controls M1 to be closed to turn on the upper half bridge arm and controls M2 to be opened to turn off the lower half bridge arm in a negative output period of the inverter circuit 10.
Referring to fig. 7, a schematic diagram of another multilevel inverter provided in the embodiments of the present application is shown.
The illustrated multi-level inverter differs from fig. 6 in that a resonant circuit 30 is also included. The resonant circuit 30 comprises in particular a first filter inductance L1 and a first filter capacitance C1.
Wherein, L1 is connected between the output terminal of the inverter circuit 10 and the positive output port of the multilevel inverter, and C1 is connected between the positive output port and the negative output port of the multilevel inverter.
The resonance circuit 30 is used to convert the output of the inverter circuit 10 into an alternating current whose waveform approximates a sine curve.
The operation principle of the multilevel inverter will be described below with reference to specific implementations.
First, a five-level inverter will be described as an example.
Referring to fig. 8, the diagram is a schematic diagram of a five-level inverter provided in an embodiment of the present application.
The inverter circuit of the five-level inverter specifically comprises a first capacitor C1, a second capacitor C2 and switching tubes Q1-Q4. Wherein, each switch tube is connected in anti-parallel with a diode respectively. The diode may be a body diode of the switching tube, or a separately provided diode, and the embodiment of the present application is not particularly limited.
A first terminal of the first capacitor C1 and a first terminal of the Q1 are connected to the positive input port of the multilevel inverter, and a second terminal of the first capacitor C1 is connected to a first terminal of the second capacitor C2 through a first node.
The second end of the second capacitor C2 and the second end of the Q2 are connected to the negative input port of the multi-level inverter, the first node is connected to the first end of the Q4, the second end of the Q4 is connected to the second end of the Q3, and the first end of the Q3 is connected to the output end of the inverter circuit 10.
A second terminal of Q1 is connected to the output of inverter circuit 10 and to a first terminal of Q2.
Taking the switching transistors Q1-Q4 as NMOS transistors for example, the first terminals of Q1-Q4 are drain electrodes, and the second terminals of Q1-Q4 are source electrodes.
The controller is used for controlling the switching tubes Q1-Q4 and the switching tubes M1 and M2 of the commutating bridge arms, and will be described in detail below.
The voltage across the C1 is BUS2, the voltage across the C2 is BUS1, the types of C1 and C2 which are commonly used are the same, and the capacitance values are the same, so the BUS1 and the BUS2 are usually the same.
Referring to fig. 9, a timing diagram of a control signal provided in the embodiment of the present application is shown.
See also the operating state diagrams of the five-level inverter shown in fig. 10A-10B.
For convenience of understanding, the Dead time (Dead time) set in the control signal of each switching tube is not directly shown in the timing diagram shown in fig. 9, and the specific length of the Dead time is not limited in the embodiment of the present application and can be determined according to the specification of the switching tube in practical application. The operating state diagrams of the five-level inverter at dead time are shown in fig. 10B, D, F and H in sequence. In the above operating state diagram, only the on-off state of the switching tube is shown, and the diode for freewheeling is not shown.
The controller, during each positive output cycle:
the controller controls M1 to be open and M2 to be closed;
firstly, controlling Q1 to be turned off, controlling Q3 to be turned on and controlling Q2 and Q4 to be alternately turned on within a first preset time (the time length is equal to the length from zero time to t 2);
controlling Q1 and Q3 to be alternately switched on within a second preset time (the time length is equal to the length from the time t2 to the time t 4), controlling Q2 to be switched off, and controlling Q4 to be switched on;
q1 is then controlled to turn off, Q3 to turn on, and Q2 and Q4 to turn on alternately for the remainder of each positive output period (the length of time is equal to the length from time t4 to time t 5).
The controller is further configured to, during each negative output cycle:
the controller controls the M1 to be closed and controls the M2 to be opened in the negative output period of the inverter circuit 10;
firstly, controlling Q2 to be turned off, controlling Q4 to be turned on, and controlling Q1 and Q3 to be alternately turned on within first preset time;
controlling Q2 and Q4 to be alternately switched on within a second preset time, controlling Q1 to be switched off and controlling Q3 to be switched on;
q2 is then controlled to turn off, Q4 is controlled to turn on, and Q1 and Q3 are controlled to turn on alternately for the remainder of each positive output cycle.
The following description will be given by taking a positive output period as an example, and the negative output period is similar, which is not described again in this embodiment:
in 0-t1, Q1 is turned off, Q3 is turned on, Q2 is in an off state, Q4 is in an on state, the working state of the five-level inverter is shown in FIG. 10A, C1 and C2 are in a charging state, the voltage across C1 is BUS2, the voltage across C2 is BUS1, L and Co are charged simultaneously, the charging voltage of Co is BUS1, and the freewheeling circuit is shown by a dotted line in the figure.
Then Q1 and Q2 remain off, Q3 remains on, and Q4 switches to off state before Q2 turns on, which corresponds to fig. 10B, and the duration is the dead time of the switching tube Q4.
Q1 then remains off, Q3 remains on, and Q2 switches to the off state, corresponding to fig. 10C, with L and Co discharging energy and the freewheeling circuit shown in dashed lines.
Then Q1 and Q2 remain off, Q3 remains on, and Q2 switches to off state before Q4 turns on, which corresponds to fig. 10D, and the lead time is the dead time of the switching tube Q2.
The above process completes a first control cycle, including 'energy storage time-dead time-free wheeling time-dead time', and the above first control cycle is repeatedly completed within the time of 0-t2, namely, the process of increasing the output voltage from 0 to BUS1 in the positive output cycle is realized.
Similarly, the above first control cycle is repeatedly completed within the time t4-t5, i.e., the process of the output voltage dropping to 0 by the BUS1 for the remaining time of the positive output cycle is realized.
In t2-t3, keeping Q2 off and Q4 on, first controlling Q1 to be on and Q3 to be off, at the moment, C1 and C2 are in a charging state, and L and Co are charged simultaneously, the freewheeling circuit is shown by a dotted line in FIG. 10E, and the charging voltage of Co is BUS1+ BUS 2.
Q1 then switches to the off state before Q3 switches to on, which corresponds to fig. 10F for the dead time of Q1.
Q1 is then maintained off, Q2 is off and Q4 is on, Q3 switches on, freewheeling at this time with the anti-parallel diode of Q2, and the freewheeling circuit is shown in dashed lines in fig. 10G.
Q3 then switches to the off state before Q1 switches to on, which corresponds to fig. 10H for the dead time of Q3.
The above process completes a second control cycle, including 'energy storage time-dead time-free wheeling time-dead time', and the second control cycle is repeatedly completed within the time of t2-t4, namely, the process that the output voltage is from BUS1 to BUS1+ BUS2 in the positive output cycle is realized.
In summary, the converter bridge arm of the five-level inverter switches the working state in the positive and negative output periods of the inverter circuit, so that the potential reference point of the negative output end is changed, and the number of the output levels of the multi-level inverter is increased, so that the inverter circuit of the five-level inverter only needs to use the topology of the three-level inverter circuit, the number of the used switching tubes is reduced by half, and the cost of the multi-level inverter is reduced.
Based on the implementation manner of the five-level inverter provided in the above embodiments, the embodiments of the present application further provide a multi-level inverter capable of implementing level output of seven levels or more, which is specifically described below with reference to the accompanying drawings.
Referring to fig. 11, a schematic diagram of another multilevel inverter provided in the embodiments of the present application is shown.
The inverter circuit 10 of the illustrated multilevel inverter includes a first branch, a second branch, and N third branches.
Wherein N is an integer greater than or equal to 3.
The first branch circuit comprises a switching tube Q5, a first end of a Q5 is connected with a positive input port of the inverter circuit 10, and a second end of a Q5 is connected with an output end of the inverter circuit.
The second branch comprises a switching tube Q6, a first end of a Q6 is connected with the output end of the inverter circuit 10, and a second end of a Q6 is connected with the negative input port of the inverter circuit.
The circuit structures of the N third branches are the same. Each third branch comprises switching tubes Q7 and Q8, a first end of Q7 is connected to a first end of the third branch, a second end of Q7 is connected to a second end of Q8, and a first end of Q8 is connected to a second end of the third branch.
The first end of the first third branch circuit passes through a first capacitor C1The first ends of the Mth third branch are connected with the first ends of the (M-1) th third branch through an Mth capacitor, and the first ends of the Nth third branch are connected with the first ends of the (N +1) th capacitor CN+1And connecting the second end of the second branch, wherein M is 2, 3, … and N.
And second ends of the N third branches are connected with a negative output port of the inverter circuit 10.
The switching tubes included in the first branch, the second branch and the third branch are respectively connected with a diode in an anti-parallel mode, the diode can be a body diode of the switching tube or a separately arranged diode, and the embodiment of the application is not particularly limited.
The converter bridge arm of the multilevel inverter switches the working state in the positive and negative output period of the inverter circuit 10, and further changes the potential reference point of the negative output end, which specifically comprises the following steps: when the upper half bridge arm of the converter bridge arm is disconnected and the lower half bridge arm of the converter bridge arm is connected, the potential reference point of the negative output end of the multi-level inverter is the negative input port of the inverter circuit; when the upper half bridge arm of the converter bridge arm is switched on and the lower half bridge arm is switched off, the potential reference point of the negative output end of the multi-level inverter is the positive input port of the inverter circuit. By changing the reference point of the electric potential, the number of the electric levels output by the multi-level inverter is increased, the number of the switching tubes used in the inverter circuit can be reduced by half, and the cost of the multi-level inverter is reduced.
Another implementation of the five-level inverter is described below with reference to the drawings.
Referring to fig. 12, a schematic diagram of another five-level inverter provided in the embodiments of the present application is shown.
See also the operating state diagrams of the five-level inverter shown in fig. 13A to 13P.
In the above operating state diagram, only the on-off state of the switching tube is shown, and the diode for freewheeling is not shown.
The operating state diagrams of the five-level inverter at dead time are shown in fig. 13B, D, F, H, J, L, N and P in sequence.
The inverter circuit of the five-level inverter comprises a first capacitor C1, a second capacitor C2 and switching tubes Q1-Q4, wherein each switching tube is connected with a diode in an anti-parallel mode.
A first end of the first capacitor C1 and a first end of the Q1 are connected to a positive input port of the multi-level inverter, a second end of the first capacitor C1 is connected to a first end of the second capacitor C2 through a first node, and a second end of the second capacitor C2 and a second end of the Q4 are connected to a negative input port of the multi-level inverter.
The first node is connected with the second end of the Q2, the first end of the Q2 is connected with the second end of the Q1 and the first end of the Q3, and the second end of the Q3 is connected with the first end of the Q4 and the output end of the inverter circuit.
The controller is specifically configured to, during each positive output cycle:
firstly, controlling Q1 to be turned off and Q2 to be turned on within a first preset time, and controlling Q3 and Q4 to be alternately turned on;
controlling Q3 to be switched on and Q4 to be switched off within second preset time, and controlling Q1 and Q2 to be alternately switched on;
q1 is then controlled to turn off, Q2 to turn on, and Q3 and Q4 are controlled to turn on alternately for the remainder of the positive output period.
The controller is further configured to, during each negative output cycle:
firstly, controlling Q3 to be switched on and Q4 to be switched off in first preset time, and controlling Q1 and Q2 to be switched on alternately;
controlling Q2 to be switched on and Q1 to be switched off within a second preset time, and controlling Q3 and Q4 to be alternately switched on;
then Q3 is controlled to be on, Q4 is controlled to be off, and Q1 and Q2 are controlled to be alternately on during the rest of the negative output period.
Wherein the first preset time is equal to the remaining time of the positive output period and the remaining time of the negative output period.
The following is specifically described with reference to the operation state diagram.
The controller, during each positive output cycle:
the controller controls M1 to be open and M2 to be closed;
q1 and Q4 are controlled to be closed firstly, Q2 and Q3 are controlled to be conductive, at the moment, the working state of the five-level inverter is shown in figure 13A, C1 and C2 are in a charging state, the voltage of two ends of C1 is BUS2, the voltage of two ends of C2 is BUS1, meanwhile, L and Co are charged, the charging voltage of Co is BUS1, and a follow current loop is shown by a dotted line in the figure.
Then, before the Q4 is turned on, the Q3 is controlled to be turned off, and the process corresponds to fig. 13B, and the duration is the dead time of the switching tube Q3.
Q1 and Q3 then remain off, Q2 remains on, and Q4 is controlled to switch to the on state, at which time L and Co release energy and the freewheel loop is shown in dashed lines in fig. 13C.
Then Q1 and Q3 remain off, Q2 remains on, and Q4 is controlled to turn off before Q3 turns on, which corresponds to FIG. 13D, with lead time being the dead time of Q4.
The above process completes a first control cycle, including "energy storage time-dead time-free wheeling time-dead time", and the above first control cycle is repeatedly completed within a first preset time, that is, the process of increasing the output voltage from 0 to BUS1 in the positive output cycle is realized.
Similarly, the above first control cycle is repeatedly completed for the remaining time of the positive output cycle, i.e., the process of the output voltage falling from the BUS1 to 0 for the remaining time of the positive output cycle is realized.
In a second preset time, the controller firstly controls Q1 and Q3 to be closed, Q2 and Q4 to be opened, at the moment, C1 and C2 are in a charging state, the voltage across C1 is BUS2, the voltage across C2 is BUS1, L and Co are charged simultaneously, the charging voltage of Co is BUS1+ BUS2, and a freewheeling circuit is shown by a dotted line in FIG. 13E.
The controller then controls Q2 and Q4 to remain open, Q3 to remain closed, and Q1 to open before Q2 closes, which corresponds to fig. 13F, with Q1 opening earlier for a dead time of Q1.
The controller then controls Q1 and Q4 to remain open, Q3 to remain closed, and Q2 to switch to a closed state, at which time L and Co discharge and the freewheel loop freewheels with the anti-parallel diode of Q4, see fig. 13G.
The controller then controls Q1 and Q4 to remain open, Q3 to remain closed, and Q2 to open before Q1 closes, which corresponds to fig. 13H with Q2 opening earlier for a dead time of Q2.
The above process completes a second control cycle, including "energy storage time-dead time-free wheeling time-dead time", and the above second control cycle is repeatedly completed within a second preset time of the positive output cycle, that is, the process from the BUS1 to the BUS1+ the BUS2 of the output voltage in the positive output cycle is realized.
The control process in the negative output period is explained below.
The controller controls M1 to close and M2 to open.
The controller firstly controls Q1 and Q4 to be disconnected, controls Q2 and Q3 to be connected, at the moment, the working state of the five-level inverter is shown in figure 13I, C1 and C2 are in a charging state, the voltage at two ends of C1 is-BUS 2, the voltage at two ends of C2 is-BUS 1, meanwhile, L and Co are charged, the charging voltage of Co is-BUS 1, and a freewheeling circuit is shown by a dotted line in the figure.
wherein-BUS 1-BUS2 is BUS-.
Q1 and Q4 then remain off, Q3 remains on, and Q2 switches to the off state before Q1 switches to the on state, corresponding to fig. 13J, with Q2 turning off earlier for the dead time of Q2.
Q2 and Q4 then remain off, Q3 remains on, and Q1 switches to the on state, at which time L and Co release energy and the freewheel loop is shown in dashed lines in fig. 13K.
Q2 and Q4 then remain off, Q3 remains on, and Q1 first switches to the off state between Q2 switching to the on state, corresponding to fig. 13L, with Q1 turning off earlier for the dead time of Q1.
The above process completes a third control cycle, including 'energy storage time-dead time-free flow time-dead time', and the above third control cycle is repeatedly completed within the first preset time of the negative output cycle, that is, the process of reducing the output voltage from 0 to-BUS 1 in the negative output cycle is realized.
Similarly, the above third control cycle is repeatedly completed within the remaining time of the negative output cycle, i.e., the process of the output voltage rising from the-BUS 1 to 0 within the remaining time of the negative output cycle is realized.
In the second preset time of the negative output cycle, the controller firstly controls Q1 and Q3 to be disconnected, and then controls Q2 and Q4 to be closed, at this time, C1 and C2 are in a charging state, the voltage at two ends of C1 is-BUS 2, the voltage at two ends of C2 is-BUS 1, meanwhile, L and Co are charged, a freewheeling circuit is shown by a dotted line in FIG. 13M, and the charging voltage of Co is-BUS 1-BUS 2.
Then the controller controls Q1 and Q3 to be kept open, controls Q2 to be kept closed, and controls Q4 to be switched to be in an off state before Q3 is switched to be in an on state, and the process corresponds to the process of FIG. 13N, and the time for Q4 to be switched off in advance is the dead time of Q4.
The controller then controls Q1 and Q4 to remain open, Q2 to remain closed and Q3 to switch to the on state, at which time L and Co release energy and the freewheel loop freewheels as shown by the dashed line in fig. 13O using the anti-parallel diode of Q1.
Then the controller controls Q1 and Q4 to remain open, Q2 to remain closed, and Q3 to turn off early before Q4 switches to the on state, with Q3 turning off early for the dead time of Q3.
The above process completes a fourth control cycle, including "energy storage time-dead time-free wheeling time-dead time", and the fourth control cycle is completed repeatedly within the second preset time of the negative output cycle, that is, the process that the output voltage is within-BUS 1 to-BUS 1-BUS2 in the negative output cycle is realized.
In summary, the converter bridge arm of the five-level inverter switches the working state in the positive and negative output periods of the inverter circuit, so that the potential reference point of the negative output end is changed, and the number of the output levels of the multi-level inverter is increased, so that the inverter circuit of the five-level inverter only needs to use the topology of the three-level inverter circuit, the number of the used switching tubes is reduced by half, and the cost of the multi-level inverter is reduced.
Another multi-level inverter capable of outputting seven levels or more is described below with reference to the drawings.
Referring to fig. 14, a schematic diagram of another multi-level inverter provided in the embodiments of the present application is shown.
The inverter circuit 10 of the multilevel inverter comprises N inverter bridge arms and a capacitor C1-CN。
Wherein N is an integer greater than or equal to 3.
The circuit structure of each inverter bridge arm is the same.
The upper half bridge arm of each inversion bridge arm comprises switching tubes Q1 and Q2, the first end of Q1 is connected with the first end of the inversion bridge arm, the second end of Q1 is connected with the second end of Q2 through the bridge arm midpoint of the inversion bridge arm, and the first end of Q2 is connected with the second end of the inversion bridge arm.
The first end of the first inverter bridge arm is connected with the positive input port of the inverter circuit and is connected with the second end of the first inverter bridge arm through a capacitor C1.
The first end of the Mth inverter bridge arm is connected with the bridge arm midpoint of the (M-1) th inverter bridge arm, and the second end of the Mth inverter bridge arm passes through a capacitor CMAnd the second end of the (M-1) th inverter bridge arm is connected, and the second end of the Nth inverter bridge arm is connected with the negative input port of the inverter circuit.
Wherein M is 2, 3, …, N.
Each switching tube included in the inverter circuit is connected with a diode in an anti-parallel mode.
The converter bridge arm of the multi-level inverter switches the working state in the positive and negative output periods of the inverter circuit, so as to change the potential reference point of the negative output end, and the method specifically comprises the following steps: when the upper half bridge arm of the converter bridge arm is disconnected and the lower half bridge arm of the converter bridge arm is connected, the potential reference point of the negative output end of the multi-level inverter is the negative input port of the inverter circuit; when the upper half bridge arm of the converter bridge arm is switched on and the lower half bridge arm is switched off, the potential reference point of the negative output end of the multi-level inverter is the positive input port of the inverter circuit. And then through changing the reference point of the electric potential, increase the quantity of the level that the multi-level inverter outputs, for example when the multi-level inverter needs to output five levels, the inverter circuit only needs to use three-level topology, when the multi-level inverter needs to output seven levels, the inverter circuit only needs to use five-level topology, therefore, can reduce the quantity of the switch tube used in the inverter circuit by half with this scheme, have reduced the cost of the multi-level inverter.
When the multilevel inverter provided in the embodiment of the present application is applied to an uninterruptible power supply, an input end of an inverter circuit is connected to a direct current input, as shown in the corresponding description of fig. 5, when the power supply is normally powered and the UPS has no fault, the direct current input is provided after an alternating current is converted into a direct current by a rectification circuit at a previous stage, and therefore, in some embodiments, the multilevel inverter may further be integrated with the rectification circuit at the previous stage, that is, the multilevel inverter may further include an AC-DC circuit, and at this time, an AC-DC-AC converter is formed by the integration, which is specifically described below with reference to the accompanying drawings.
Referring to fig. 15A, a schematic diagram of a multi-level inverter according to an embodiment of the present disclosure is shown.
The illustrated multi-level inverter differs from that shown in fig. 7 in that an AC-DC circuit 40 is also included.
The positive input end of the AC-DC circuit 40 is used for connecting an alternating current input, and the negative input end of the AC-DC circuit 40 is used for connecting the bridge arm midpoint of the converter bridge arm. A positive output port of the AC-DC circuit 40 is connected to a positive input port of the inverter circuit 10, and a negative output port of the AC-DC circuit 40 is connected to a negative input port of the inverter circuit 10.
The AC-DC circuit 40 is used to convert AC power supplied from AC input into DC power and transmit the DC power to the inverter circuit 10.
In some embodiments, the structure of the AC-DC circuit is symmetrical to the inverter circuit 10 along the converter bridge arm 20, so that the converter bridge arm can offset the power frequency current, thereby reducing the loss of the switching tube of the converter bridge arm and improving the efficiency.
A five-level inverter will be described below with reference to a specific implementation of the AC-DC circuit 40.
Referring to fig. 15B, a schematic diagram of another multi-level inverter provided in the embodiments of the present application is shown.
The AC-DC circuit 40 includes switching tubes M3-M6, a second filter inductor L2, and a second filter capacitor Ci.
The switching tubes M3-M6 are connected in anti-parallel with a diode, which may be a body diode of the switching tube, or a separately provided diode, and the embodiment of the present application is not particularly limited.
The positive input port of the AC-DC circuit 40 is connected to the second end of the M3 through a second filter inductor L2, the first end of the M3 is connected to the positive input port of the inverter circuit 10, the second end of the M3 is connected to the first end of the M4 and the first end of the M5, the second end of the M4 is connected to the negative input port of the DC-DC circuit 40 and the bridge arm midpoint, the second end of the M5 is connected to the second end of the M6, and the first end of the M6 is connected to the capacitor midpoint of the inverter circuit 10.
The second filter capacitance Ci is connected between the positive input port and the negative input port of the AC-DC circuit 40.
By utilizing the AC-DC circuit, the current conversion bridge arm can also realize the offset of power frequency current, thereby reducing the loss of a switching tube of the current conversion bridge arm and improving the efficiency.
Based on the multi-level inverter provided by the above embodiments, the embodiments of the present application further provide a control method of the multi-level inverter, which is specifically described below with reference to the accompanying drawings.
Referring to fig. 16, the figure is a flowchart of a control method of a multilevel inverter according to an embodiment of the present application.
The method comprises the following steps:
s1401: and in the positive output period of the inverter circuit of the multi-level inverter, controlling the potential of the negative output end of the multi-level inverter to be the potential of the negative input port of the inverter circuit.
V for potential of negative input port of multi-level inverterBUS-Indicating that the potential of the positive output port of the multilevel inverter is Vout+That is, the output voltage of the multilevel inverter at this time can be expressed as (V)out+-VBUS-)。
S1402: and in the negative output period of the inverter circuit, controlling the potential of the negative output end of the multi-level inverter to be the potential of the positive input port of the inverter circuit.
V for potential of positive input port of multilevel inverterBUS+Indicating that the potential of the positive output port of the multilevel inverter is Vout+That is, the output voltage of the multilevel inverter at this time can be expressed as (V)out+-VBUS+)。
By changing the potential reference point, two levels are additionally added on the basis of the original level quantity output by the inverter circuit. Therefore, the number of switching tubes required by the inverter circuit can be reduced by half, the capacitance required to be used is reduced, and the size and the cost of the multi-level inverter are reduced.
The following description is made with reference to specific implementations of the multilevel inverter.
The multi-level inverter comprises a current conversion bridge arm, and the current conversion bridge arm comprises an upper half bridge arm and a lower half bridge arm. The first end of the upper half bridge arm is connected with a positive input port of the inverter circuit, the second end of the upper half bridge arm is connected with the first end of the lower half bridge arm through a bridge arm midpoint, the second end of the lower half bridge arm is connected with a negative input port of the inverter circuit, and the bridge arm midpoint is connected with a negative output port of the multi-level inverter.
Referring to fig. 17, the figure is a schematic diagram of another control method of a multilevel inverter according to an embodiment of the present application.
The method comprises the following steps:
s1501: and controlling the upper half-bridge arm to be switched off and the lower half-bridge arm to be switched on in the positive output period of the inverter circuit.
The negative output port is connected with the negative input port of the multi-level inverter through the lower half-bridge arm, namely the potential reference point of the negative output port of the inverter circuit is the negative input port of the multi-level inverter, and the output voltage of the multi-level inverter can be expressed as (V)out+-VBUS-)。
S1502: and controlling the upper half-bridge arm to be switched on and the lower half-bridge arm to be switched off in the negative output period of the inverter circuit.
At this time, the negative output port is connected with the positive input port of the multi-level inverter through the upper half bridge arm, that is, the potential reference point of the negative output port of the inverter circuit is the positive input port of the multi-level inverter, and the output voltage of the multi-level inverter can be expressed as (V)out+-VBUS+)。
In some embodiments, the multi-level inverter is a five-level inverter, and the inverter circuit includes a first capacitor, a second capacitor, and switching transistors Q1-Q4, each of which is connected in anti-parallel with a diode. The first end of the first capacitor and the first end of the Q1 are connected with a positive input port of the multilevel inverter, the second end of the first capacitor is connected with the first end of the second capacitor through a first node, the second end of the second capacitor and the second end of the Q2 are connected with a negative input port of the multilevel inverter, the first node is connected with the first end of the Q4, the second end of the Q4 is connected with the second end of the Q3, and the first end of the Q3 is connected with the output end of the inverter circuit. A second terminal of Q1 is connected to the output of the inverter circuit and to a first terminal of Q2.
The method then also comprises the following steps:
during each positive output period:
firstly, controlling Q1 to be turned off, controlling Q3 to be turned on, and controlling Q2 and Q4 to be alternately turned on within a first preset time;
controlling Q1 and Q3 to be alternately switched on within a second preset time, controlling Q2 to be switched off and controlling Q4 to be switched on;
q1 is then controlled to turn off, Q3 is controlled to turn on, and Q2 and Q4 are controlled to turn on alternately for the remainder of each positive output cycle.
During each of the negative output periods:
firstly, controlling Q2 to be turned off, controlling Q4 to be turned on, and controlling Q1 and Q3 to be alternately turned on within first preset time; controlling Q2 and Q4 to be alternately switched on within a second preset time, controlling Q1 to be switched off and controlling Q3 to be switched on;
q2 is then controlled to turn off, Q4 is controlled to turn on, and Q1 and Q3 are controlled to turn on alternately for the remainder of each positive output cycle.
Wherein the first preset time is equal to the remaining time.
In other embodiments, the multi-level inverter is a five-level inverter, and the inverter circuit includes a first capacitor, a second capacitor, and switching transistors Q1-Q4, each of which is connected in anti-parallel with a respective diode. The first end of the first capacitor and the first end of the Q1 are connected with a positive input port of the multilevel inverter, the second end of the first capacitor is connected with the first end of the second capacitor through a first node, the second end of the second capacitor and the second end of the Q4 are connected with a negative input port of the multilevel inverter, the first node is connected with the second end of the Q2, the first end of the Q2 is connected with the second end of the Q1 and the first end of the Q3, and the second end of the Q3 is connected with the first end of the Q4 and an output end of the inverter circuit.
The method then also comprises the following steps:
during each positive output period:
firstly, controlling Q1 to be turned off and Q2 to be turned on within a first preset time, and controlling Q3 and Q4 to be alternately turned on;
controlling Q3 to be switched on and Q4 to be switched off within second preset time, and controlling Q1 and Q2 to be alternately switched on;
then controlling Q1 to be switched off, Q2 to be switched on, and controlling Q3 and Q4 to be alternately switched on in the rest time of the positive output period;
during each negative output cycle:
firstly, controlling Q3 to be switched on and Q4 to be switched off in first preset time, and controlling Q1 and Q2 to be switched on alternately;
controlling Q2 to be switched on and Q1 to be switched off within the second preset time, and controlling Q3 and Q4 to be alternately switched on;
then controlling Q3 to be switched on and Q4 to be switched off in the rest time of the negative output period, and controlling Q1 and Q2 to be switched on alternately;
the first preset time is equal to a remaining time of the positive output period and a remaining time of the negative output period.
The method switches the working state by controlling the converter bridge arm in the positive and negative output periods of the inverter circuit, so as to change the potential reference point of the negative output end, and specifically comprises the following steps: when the upper half bridge arm of the converter bridge arm is disconnected and the lower half bridge arm of the converter bridge arm is connected, the potential reference point of the negative output end of the multi-level inverter is the negative input port of the inverter circuit; when the upper half bridge arm of the converter bridge arm is switched on and the lower half bridge arm is switched off, the potential reference point of the negative output end of the multi-level inverter is the positive input port of the inverter circuit, the number of switching tubes required by the inverter circuit can be reduced by half, and the cost of the multi-level inverter is reduced.
Based on the multi-level inverter provided by the above embodiments, the embodiments of the present application further provide an uninterruptible power supply, which is specifically described below with reference to the accompanying drawings.
Referring to fig. 18, a schematic diagram of an uninterruptible power supply according to an embodiment of the present disclosure is shown.
The uninterruptible power supply 100 includes a rectifier 101, a multilevel inverter 102, a battery 103, and a bypass circuit 104.
A first terminal of the bypass circuit 104 is connected to the input terminal of the rectifier 101 and the ac power source through the main circuit switch S1, and a second terminal of the bypass circuit 104 is connected to the output terminal of the multilevel inverter 102.
The battery 103 is connected to the input of the multilevel inverter 102 through a battery switch S2.
The bypass circuit 104 is provided with a bypass switch S3.
The controller of the ups 100 changes the operating state by controlling the states of the main switch S1, the battery switch S2, and the bypass switch S3, as described in more detail below.
When the alternating current power supply is normally powered and the UPS is not in fault, the main circuit of the UPS works, namely the main circuit switch S1 is closed, and the battery switch S2 and the bypass switch S3 are both opened.
At this time, the ac power inputted from the ac power supply is supplied to the load through the rectifier 101 and the multilevel inverter 102, and the battery 103 is charged through the rectifier 101, and the UPS can output a stable voltage to the load 300.
When the ac power fails, or the ac power is required to stop supplying power, or the rectifier 101 fails, power is supplied to the load by the battery 103 of the UPS. At this time, the rectifier 101 stops working, the battery switch S2 is closed, the main switch S1 and the bypass switch S3 are both opened, and the multilevel inverter 102 converts the dc power provided by the battery 103 into ac power to supply power to the load.
When the multilevel inverter 102 fails, the bypass circuit 104 needs to be started, the bypass switch S3 is turned on, the main switch S1 and the battery switch S2 are both closed, and the ac power supply directly supplies power to the load.
For a specific implementation manner of the multilevel inverter 102, reference may be made to the relevant description in the above embodiments, and the embodiments of the present application are not described herein again.
The controller of the ups 100 may be integrated with the controller of the multilevel inverter 102.
The multi-level inverter of the uninterruptible power supply comprises a converter bridge arm, wherein the converter bridge arm switches working states in a positive output period and a negative output period of an inverter circuit so as to change a potential reference point of a negative output end, and the converter bridge arm specifically comprises the following components: when the upper half bridge arm of the converter bridge arm is disconnected and the lower half bridge arm of the converter bridge arm is connected, the potential reference point of the negative output end of the multi-level inverter is the negative input port of the inverter circuit; when the upper half bridge arm of the converter bridge arm is switched on and the lower half bridge arm is switched off, the potential reference point of the negative output end of the multi-level inverter is the positive input port of the inverter circuit. By changing the reference point of the potential, the number of levels output by the multi-level inverter is increased, for example, when the multi-level inverter needs to output five levels, the inverter circuit only needs to use a three-level topology, and when the multi-level inverter needs to output seven levels, the inverter circuit only needs to use a five-level topology.
By utilizing the multi-level inverter, the number of switching tubes used in the inverter circuit can be reduced by half, the size and the cost of the multi-level inverter are reduced, and the size and the cost of an uninterruptible power supply are further reduced.
In some embodiments, a rectifier is integrated with a multi-level inverter, the rectifier including an AC-DC circuit.
The positive input port of the AC-DC circuit is used for connecting an alternating current power supply, the negative input port of the AC-DC circuit is used for connecting the middle point of a bridge arm, the positive output port of the AC-DC circuit is connected with the positive input port of the inverter circuit, and the negative output port of the AC-DC circuit is connected with the negative input port of the inverter circuit. The AC-DC circuit is used for converting alternating current provided by the alternating current power supply into direct current and then transmitting the direct current to the inverter circuit.
The AC-DC circuit and the inverter circuit are symmetrical along the converter bridge arm. Therefore, the power frequency current of the converter bridge arm can be offset, the loss of a switching tube of the converter bridge arm is reduced, and the efficiency is improved.
It should be understood that in the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" for describing an association relationship of associated objects, indicating that there may be three relationships, e.g., "a and/or B" may indicate: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In addition, some or all of the units and modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
The foregoing is directed to embodiments of the present application and it is noted that numerous modifications and adaptations may be made by those skilled in the art without departing from the principles of the present application and are intended to be within the scope of the present application.

Claims (16)

1. A multilevel inverter, applied to a single bus system, comprising: the converter bridge arm, the inverter circuit and the controller;
a positive input port of the inverter circuit is connected with a positive input port of the multi-level inverter, a negative input port of the inverter circuit is connected with a negative input port of the multi-level inverter, and an output end of the inverter circuit is connected with a positive output port of the multi-level inverter;
the converter bridge arm comprises an upper half bridge arm and a lower half bridge arm, wherein a first end of the upper half bridge arm is connected with a positive input port of the multi-level inverter, a second end of the upper half bridge arm is connected with a first end of the lower half bridge arm through a bridge arm midpoint, a second end of the lower half bridge arm is connected with a negative input port of the multi-level inverter, and the bridge arm midpoint is connected with a negative output port of the multi-level inverter;
the controller is used for controlling the upper half bridge arm to be disconnected and the lower half bridge arm to be connected in a positive output period of the inverter circuit; and controlling the upper half bridge arm to be connected and the lower half bridge arm to be disconnected in a negative output period of the inverter circuit.
2. The multilevel inverter according to claim 1, wherein the upper half bridge leg comprises a switching tube M1, the lower half bridge leg comprises a switching tube M2, and the M1 and M2 are connected in anti-parallel with one diode, respectively;
the controller controls the M1 to be open and the M2 to be closed in a positive output period of the inverter circuit; in the negative output period of the inverter circuit, the M1 is controlled to be closed, and the M2 is controlled to be opened.
3. The multilevel inverter according to claim 1, wherein the multilevel inverter is a five-level inverter, the inverter circuit comprises a first capacitor, a second capacitor and switching transistors Q1-Q4, each of the switching transistors is connected in anti-parallel with a diode;
a first end of the first capacitor and a first end of the Q1 are connected to a positive input port of the multilevel inverter, a second end of the first capacitor is connected to a first end of the second capacitor through a first node, a second end of the second capacitor and a second end of the Q2 are connected to a negative input port of the multilevel inverter, the first node is connected to a first end of the Q4, a second end of the Q4 is connected to a second end of the Q3, and a first end of the Q3 is connected to an output end of the inverter circuit;
the second end of the Q1 is connected to the output of the inverter circuit and the first end of the Q2.
4. The multilevel inverter of claim 3, wherein the controller is to, during each of the positive output periods:
firstly, controlling the Q1 to be turned off within a first preset time, controlling the Q3 to be turned on, and controlling the Q2 and the Q4 to be alternately turned on; controlling the Q1 and the Q3 to be alternately switched on within a second preset time, controlling the Q2 to be switched off and controlling the Q4 to be switched on; then controlling the Q1 to be turned off, the Q3 to be turned on, and the Q2 and the Q4 to be alternately turned on during the remaining time of each positive output period;
the controller is further configured to, during each of the negative output cycles:
firstly, controlling the Q2 to be turned off within a first preset time, controlling the Q4 to be turned on, and controlling the Q1 and the Q3 to be alternately turned on; controlling the Q2 and the Q4 to be alternately switched on within a second preset time, controlling the Q1 to be switched off and controlling the Q3 to be switched on; then controlling the Q2 to be switched off, the Q4 to be switched on, and the Q1 and the Q3 to be alternately switched on in the rest time of each negative output period;
the first preset time is equal to a remaining time of the positive output period and a remaining time of the negative output period.
5. The multilevel inverter according to claim 1, wherein the inverter circuit comprises a first branch, a second branch and N third branches, wherein N is a positive integer greater than or equal to 2;
the first branch circuit comprises a switching tube Q5, a first end of the Q5 is connected with a positive input port of the inverter circuit, and a second end of the Q5 is connected with an output end of the inverter circuit;
the second branch comprises a switching tube Q6, a first end of the Q6 is connected with an output end of the inverter circuit, and a second end of the Q6 is connected with a negative input port of the inverter circuit;
each of the third branches comprises switching tubes Q7 and Q8, a first end of the Q7 is connected to a first end of the third branch, a second end of the Q7 is connected to a second end of the Q8, and a first end of the Q8 is connected to a second end of the third branch;
the first end of the first branch is connected to the first end of the first branch through a first capacitor, the first end of the mth third branch is connected to the first end of the (M-1) th third branch through an mth capacitor, the first end of the nth third branch is connected to the second end of the second branch through an (N +1) th capacitor, and M is 2, 3, …, N;
second ends of the N third branches are connected with a negative output port of the inverter circuit;
each switching tube included in the inverter circuit is connected with a diode in an anti-parallel mode.
6. The multilevel inverter according to claim 1, wherein the multilevel inverter is a five-level inverter, the inverter circuit comprises a first capacitor, a second capacitor and switching transistors Q1-Q4, each of the switching transistors is connected in anti-parallel with a diode;
the first end of the first capacitor and the first end of the Q1 are connected with a positive input port of the multi-level inverter, the second end of the first capacitor is connected with the first end of the second capacitor through a first node, the second end of the second capacitor and the second end of the Q4 are connected with a negative input port of the multi-level inverter, the first node is connected with the second end of the Q2, the first end of the Q2 is connected with the second end of the Q1 and the first end of the Q3, and the second end of the Q3 is connected with the first end of the Q4 and an output end of the inverter circuit.
7. The multilevel inverter of claim 3, wherein the controller is to, during each of the positive output periods:
firstly, controlling the Q1 to be switched off and the Q2 to be switched on within a first preset time, and controlling the Q3 and the Q4 to be alternately switched on; controlling the Q3 to be switched on and the Q4 to be switched off within a second preset time, and controlling the Q1 and the Q2 to be alternately switched on; then controlling the Q1 to be switched off, the Q2 to be switched on, and the Q3 and the Q4 to be alternately switched on in the rest time of the positive output period;
the controller is further configured to, during each of the negative output cycles:
firstly, controlling the Q3 to be switched on and the Q4 to be switched off within the first preset time, and controlling the Q1 and the Q2 to be alternately switched on; controlling the Q2 to be switched on, the Q1 to be switched off, and controlling the Q3 and the Q4 to be alternately switched on within the second preset time; then controlling the Q3 to be switched on, the Q4 to be switched off, and controlling the Q1 and the Q2 to be switched on alternately in the rest time of the negative output period;
the first preset time is equal to a remaining time of the positive output period and a remaining time of the negative output period.
8. Multilevel inverter according to claim 1, characterized in that the inverter circuit comprises N inverter legs and a capacitor C1-CNN is an integer greater than or equal to 3;
each upper half bridge arm of the inverter bridge arm comprises a switching tube Q1 and a switching tube Q2, a first end of the Q1 is connected with a first end of the inverter bridge arm, a second end of the Q1 is connected with a second end of the Q2 through a bridge arm midpoint of the inverter bridge arm, and a first end of the Q2 is connected with the second end of the inverter bridge arm;
the first end of the first inverter bridge arm is connected with the positive input port of the inverter circuit and is connected with the second end of the first inverter bridge arm through a capacitor C1;
the first end of the Mth inverter bridge arm is connected with the bridge arm midpoint of the (M-1) th inverter bridge arm, and the second end of the Mth inverter bridge arm passes through a capacitor CMConnecting second ends of an (M-1) th inverter bridge arm, connecting second ends of an Nth inverter bridge arm with a negative input port of the inverter circuit, wherein M is 2, 3, …, N;
each switching tube included in the inverter circuit is connected with a diode in an anti-parallel mode.
9. The multilevel inverter according to any of claims 1 to 8, further comprising a first filter inductor and a first filter capacitor;
the first filter inductor is connected between the output end of the inverter circuit and the positive output port of the multi-level inverter; the first filter capacitor is connected between a true output port and a negative output port of the multilevel inverter.
10. The multilevel inverter according to any of claims 1-9, further comprising an AC-DC circuit;
a positive input port of the AC-DC circuit is used for connecting an alternating input, a negative input port of the AC-DC circuit is used for connecting the middle point of the bridge arm, a positive output port of the AC-DC circuit is connected with a positive input port of the inverter circuit, and a negative output port of the DC-DC circuit is connected with a negative input port of the inverter circuit;
the AC-DC circuit is used for converting alternating current provided by the alternating current input into direct current and then transmitting the direct current to the inverter circuit.
11. The multilevel inverter of claim 10, wherein the AC-DC circuit is configured to be symmetrical to the inverter circuit along the converter leg.
12. Multilevel inverter according to claim 10 or 11, wherein the controller is further configured to control the operating state of the AC-DC circuit.
13. A control method of a multilevel inverter, wherein the multilevel inverter is applied to a single bus system, the method comprising:
controlling the potential of a negative output end of a multi-level inverter to be the potential of a negative input port of an inverter circuit in a positive output period of the inverter circuit of the multi-level inverter;
and in the negative output period of the inverter circuit, controlling the potential of the negative output end of the multi-level inverter to be the potential of the positive input port of the inverter circuit.
14. The control method according to claim 13, wherein the multilevel inverter further comprises a converter bridge arm, the converter bridge arm comprises an upper half bridge arm and a lower half bridge arm, a first end of the upper half bridge arm is connected to a positive input port of the inverter circuit, a second end of the upper half bridge arm is connected to a first end of the lower half bridge arm through a bridge arm midpoint, a second end of the lower half bridge arm is connected to a negative input port of the inverter circuit, and the bridge arm midpoint is connected to a negative output port of the multilevel inverter; in a positive output period of an inverter circuit of the multilevel inverter, controlling a potential of a negative output end of the multilevel inverter to be a potential of a negative input port of the inverter circuit, specifically including:
controlling the upper half bridge arm to be disconnected and the lower half bridge arm to be connected in a positive output period of the inverter circuit;
in the negative output period of the inverter circuit, controlling the potential of the negative output end of the multilevel inverter to be the potential of the positive input port of the inverter circuit, specifically including:
and controlling the upper half bridge arm to be connected and the lower half bridge arm to be disconnected in a negative output period of the inverter circuit.
15. An uninterruptible power supply comprising the multi-level inverter according to any one of claims 1 to 9, wherein a load is connected to an output of the multi-level inverter, and further comprising: a rectifier, a bypass circuit and a battery;
the first end of the bypass circuit is connected with the input end of the rectifier, and the second end of the bypass circuit is connected with the output end of the multi-level inverter;
the input end of the rectifier is connected with an alternating current power supply;
the rectifier is used for converting alternating current provided by the alternating current power supply into direct current and transmitting the direct current to the battery and the multi-level inverter;
the bypass circuit is used for enabling the alternating current power supply to directly supply power to the load when being started;
and the battery is used for outputting direct current to the multi-level inverter when the rectifier stops working.
16. The uninterruptible power supply of claim 15, wherein the rectifier is integrated with the multilevel inverter, the rectifier comprising an AC-DC circuit;
the AC-DC circuit and the inverter circuit are symmetrical along the converter bridge arm;
a positive input port of the AC-DC circuit is used for connecting the alternating current power supply, a negative input port of the AC-DC circuit is used for connecting the middle point of the bridge arm, a positive output port of the AC-DC circuit is connected with a positive input port of the inverter circuit, and a negative output port of the DC-DC circuit is connected with a negative input port of the inverter circuit;
the AC-DC circuit is used for converting the alternating current provided by the alternating current power supply into direct current and then transmitting the direct current to the inverter circuit.
CN202011375682.6A 2020-11-30 2020-11-30 Multi-level inverter and control method thereof Pending CN112615556A (en)

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