CN105703656A - Inversion unit, control method thereof and inverter - Google Patents
Inversion unit, control method thereof and inverter Download PDFInfo
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- CN105703656A CN105703656A CN201410420860.0A CN201410420860A CN105703656A CN 105703656 A CN105703656 A CN 105703656A CN 201410420860 A CN201410420860 A CN 201410420860A CN 105703656 A CN105703656 A CN 105703656A
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Abstract
The invention relates to an inversion unit. The inversion unit comprises a bus capacitor C1, a bus capacitor C2, a tri-level module and an H-bridge module. The bus capacitor C1 and the bus capacitor C2 are in series connection. A positive electrode terminal of the bus capacitor C1 is in connection with a positive electrode terminal of a dc source; a negative electrode terminal of the bus capacitor C2 is in connection with a negative electrode terminal of the dc source; positive electrode terminals and negative electrode terminals of the bus capacitor C1 and the bus capacitor C2 are all in connection with an input terminal of the tri-level module. A collector of a transistor S1, and an emitter of a transistor S3 of the H-bridge module are both in connection with an output terminal of the tri-level module. Voltage values at two ends of the bus capacitor C1, the bus capacitor C2 and a flying capacitor Cph are all Vdc/2, wherein Vdc is a voltage value at two ends of the dc source. Correspondingly, the invention also provides a method of controlling the inversion unit and an inverter comprising the inversion unit. The inverter does not need to employ clamp diodes and independent dc sources in large quantity and is easy to control.
Description
Technical field
The present invention relates to electric and electronic technical field, be specifically related to a kind of inversion unit and control method thereof, and include the inverter of described inversion unit。
Background technology
Along with the minimizing day by day of traditional energy, power system is faced with huge change。The technology such as photovoltaic generation, wind-power electricity generation does not consume the advantages such as fuel, noiseless, pollution-free and sustainable development have become as the developing direction of Future Power System because having。
The research of its structure with control method, as the nucleus equipment of photovoltaic generating system Yu grid interface, is extremely important by combining inverter in improving the generating efficiency of power system, reduction cost etc.。Wherein, harmonic wave of output voltage is little, electromagnetic interference is little because having for multi-electrical level inverter, can improve power quality, reduces the many advantages such as the wave filter volume higher hamonic wave with control generation, is widely used in high-power occasion。But, owing to existing diode clamp bit-type five-electrical level inverter needs to adopt a fairly large number of clamp diode, existing electric capacity flies to control complexity across type five-electrical level inverter, existing H bridge cascade connection type five-electrical level inverter needs to adopt a fairly large number of independent DC power supply (wherein each H bridge module is required for adopting independent DC source), thus inhibits five-electrical level inverter popularization in actual production and use。
Summary of the invention
The technical problem to be solved is for drawbacks described above existing in prior art, one is provided not need to adopt a fairly large number of clamp diode and a fairly large number of independent DC power supply, and control simple inversion unit and control method thereof, and include the inverter of described inversion unit。
Solve the technology of the present invention problem be the technical scheme is that
Described inversion unit includes bus capacitor C1, bus capacitor C2, three level block and H bridge module, described H bridge module includes transistor S1And with the diode D of its reverse parallel connection1, transistor S2And with the diode D of its reverse parallel connection2, transistor S3And with the diode D of its reverse parallel connection3, transistor S4And with the diode D of its reverse parallel connection4, and striding capacitance Cph,
Described bus capacitor C1With bus capacitor C2Series connection, and bus capacitor C1Positive terminal be connected with the positive terminal of DC source, bus capacitor C2Negative pole end be connected with the negative pole end of DC source, bus capacitor C1, bus capacitor C2Positive terminal and negative pole end be all connected with the input of three level block；
In described H bridge module, described transistor S1Colelctor electrode and transistor S3Emitter stage connect, described transistor S1Emitter stage, striding capacitance CphPositive terminal and transistor S2Emitter stage connect, described transistor S3Colelctor electrode, striding capacitance CphNegative pole end and transistor S4Colelctor electrode connect, described transistor S2Colelctor electrode and transistor S4Emitter stage be all connected with exchange output node, and transistor S1Colelctor electrode and transistor S3Emitter stage be all connected with the outfan of three level block；
Described bus capacitor C1, bus capacitor C2With striding capacitance CphThe magnitude of voltage at two ends is Vdc/ 2, and VdcMagnitude of voltage for described DC source two ends。
The present invention also provides for the control method of above-mentioned inversion unit, and described control method is:
Each semiconductor components and devices in described inversion unit is carried out on or off control, so that the output voltage values of described inversion unit respectively Vdc、Vdc/2、0、-Vdc/ 2 and-Vdc, the output voltage values of described inversion unit is the voltage difference between described exchange output node and neutral point。
The present invention also provides for a kind of inverter, and including three-phase inversion unit, every phase inversion unit all adopts above-mentioned inversion unit。
Beneficial effect:
Inverter of the present invention is when single-phase and heterogeneous application, compared with prior art, the semiconductor components and devices adopted is less, especially with clamp diode negligible amounts (even can not adopt), and only need to adopt an independent DC source, thus greatly reduce volume and the cost of inverter, also reduce the loss of inverter simultaneously, improve the efficiency of inverter；
The control mode of inverter of the present invention is simple, easy, is beneficial to popularization and uses。
Accompanying drawing explanation
Fig. 1 is the structural representation of inversion unit described in the embodiment of the present invention 1；
Fig. 2 is the expansion structure schematic diagram of inversion unit described in the embodiment of the present invention 1；
Fig. 3 is the topology diagram of inversion unit described in the embodiment of the present invention 2；
Fig. 4 to Figure 13 is followed successively by inversion unit shown in Fig. 3 and is in first operation mode equivalent circuit diagram to the tenth operation mode；
Wherein, the A figure corresponding current of Fig. 4 to Figure 13 is flowed to AC load by inversion unit, and the B figure corresponding current of Fig. 4 to Figure 13 is flowed to inversion unit by AC load；
Figure 14 is the three-phase topology diagram of inverter described in the embodiment of the present invention 2；
Figure 15 is the topology diagram of inversion unit described in the embodiment of the present invention 3；
Figure 16 is the three-phase topology diagram of inverter described in the embodiment of the present invention 3；
Figure 17 is the topology diagram of inversion unit described in the embodiment of the present invention 4；
Figure 18 is the three-phase topology diagram of inverter described in the embodiment of the present invention 4。
Detailed description of the invention
For making those skilled in the art be more fully understood that technical scheme, below in conjunction with drawings and Examples, the present invention is described in further detail。
Embodiment 1:
As it is shown in figure 1, the present embodiment provides a kind of inversion unit, it includes bus capacitor C1, bus capacitor C2, three level block and H bridge module。
Wherein, described H bridge module includes transistor S1And with the diode D of its reverse parallel connection1, transistor S2And with the diode D of its reverse parallel connection2, transistor S3And with the diode D of its reverse parallel connection3, transistor S4And with the diode D of its reverse parallel connection4, and striding capacitance Cph；
Described bus capacitor C1With bus capacitor C2Series connection, and bus capacitor C1Positive terminal be connected with the positive terminal of DC source E, bus capacitor C2Negative pole end be connected with the negative pole end of DC source E, bus capacitor C1, bus capacitor C2Positive terminal and negative pole end be all connected with the input (i.e. " in " in Fig. 1) of three level block；
In described H bridge module, described transistor S1Colelctor electrode and transistor S3Emitter stage connect, described transistor S1Emitter stage, striding capacitance CphPositive terminal and transistor S2Emitter stage connect, described transistor S3Colelctor electrode, striding capacitance CphNegative pole end and transistor S4Colelctor electrode connect, described transistor S2Colelctor electrode and transistor S4Emitter stage all with exchange output node A be connected, in other words, transistor S2Colelctor electrode and transistor S4The connection node of emitter stage be exchange output node A and transistor S1Colelctor electrode and transistor S3Emitter stage be all connected with the outfan (i.e. " out " in Fig. 1) of three level block；
Described bus capacitor C1, bus capacitor C2With striding capacitance CphThe magnitude of voltage at two ends is Vdc/ 2, and VdcMagnitude of voltage for DC source E two ends。
In the present embodiment, described three level block can adopt the existing circuit module that can export three kinds of magnitudes of voltage, and its structure and annexation belong to the known general knowledge of this area, repeat no more。
Preferably, the transistor adopted in the present embodiment is insulated gate bipolar transistor。
Each transistor of adopting in the present embodiment and can only with one group (as shown in Figure 1) with the diode of its reverse parallel connection。Preferably, each transistor of adopting in the present embodiment and the diode with its reverse parallel connection may be used without at least two groups, and this at least two group transistor and adopting with the diode of its reverse parallel connection is connected and/or the connected mode of parallel connection, when this at least two group transistor and the diode with its reverse parallel connection are sequentially connected in series, described inversion unit can be made to realize higher voltage output, and then middle high-pressure field can be applied to。Here, at least two group transistors and with the Diode series of its reverse parallel connection and/or in parallel refer to, this at least two group transistor and the diode with its reverse parallel connection are sequentially connected in series, or this at least two group transistor and and the diode of its reverse parallel connection between all in parallel, or some group transistor and with the diodes in parallel of its reverse parallel connection after again with all the other group transistors and with the Diode series of its reverse parallel connection。
The bus capacitor C adopted in the present embodiment1, bus capacitor C2, striding capacitance CphCan respectively only with an electric capacity (as shown in Figure 1)。Preferably, the bus capacitor C adopted in the present embodiment1, bus capacitor C2, striding capacitance CphAlso can respectively by the sub-capacitances in series of at least two and/or compose in parallel, to meet practical engineering application。Here, the sub-capacitances in series of at least two and/or parallel connection refer to the sub-electric capacity of this at least two and are sequentially connected in series, or all in parallel between the sub-electric capacity of this at least two, or after certain a little Capacitance parallel connection again with its minor capacitances in series。Such as, bus capacitor C1Including four sub-electric capacity, respectively sub-electric capacity C11To sub-electric capacity C14, these four sub-electric capacity can be made to be sequentially connected in series, or make this four sub-Capacitance parallel connections, or make sub-electric capacity C11With sub-electric capacity C12Parallel connection, sub-electric capacity C13With sub-electric capacity C14Parallel connection, and the sub-electric capacity C after parallel connection11With sub-electric capacity C12Again with in parallel after sub-electric capacity C13With sub-electric capacity C14Series connection, or make sub-electric capacity C11, sub-electric capacity C12With sub-electric capacity C13After parallel connection again with sub-electric capacity C14Series connection, etc.。
The present embodiment also provides for the control method of a kind of inversion unit, and this control method is: each semiconductor components and devices in above-mentioned inversion unit is carried out on or off control, so that the output voltage values of described inversion unit respectively Vdc、Vdc/2、0、-Vdc/ 2 and-Vdc, the output voltage values of described inversion unit is the voltage difference between described exchange output node and neutral point。It is to say, above-mentioned inversion unit is five level inverse conversion unit。
Further, H bridge module in described inversion unit not only can adopt one (as shown in Figure 1), also can adopt at least two, this at least two H bridge module is sequentially connected in series (as shown in Figure 2), and the H bridge module of these series connection has two terminations, visible, inversion unit shown in Fig. 2 is the expansion structure of inversion unit shown in Fig. 1。This at least two H bridge module is followed successively by the H bridge module 1 ... in Fig. 2, H bridge module n, and n takes the integer more than or equal to 2, is wherein arranged in the transistor S of the H bridge module (i.e. the H bridge module 1 of Fig. 2) of an end1Colelctor electrode and transistor S3Emitter stage be all connected with the outfan of three level block, be arranged in the transistor S of the H bridge module (i.e. H bridge module n of Fig. 2) of another end2Colelctor electrode and transistor S4Emitter stage all with exchange output node A be connected, the transistor S of remaining each H bridge module1Colelctor electrode and transistor S3The transistor S of previous H bridge module of the equal series connection with it of emitter stage2Colelctor electrode, transistor S4Emitter stage connect, the transistor S of each H bridge module2Colelctor electrode and transistor S4The transistor S of later H bridge module of the equal series connection with it of emitter stage1Colelctor electrode, transistor S3Emitter stage connect。Here, for " H bridge module " and with its " the previous H bridge module connected ", should " previous H bridge module of series connection " relative to this " H bridge module " closer to three level block, such as, should " the previous H bridge module of series connection " be the H bridge module 1 in Fig. 2, should " H bridge module " be the H bridge module 2 in Fig. 2；For " H bridge module " and with its " the later H bridge module connected ", it is somebody's turn to do " the later H bridge module of series connection " relative to this " H bridge module " closer to exchanging output node A, such as, should " the later H bridge module of series connection " be the H bridge module 2 in Fig. 2, should " H bridge module " be the H bridge module 1 in Fig. 2。
The present embodiment also provides for a kind of inverter, and including three-phase inversion unit, wherein every phase inversion unit all adopts above-mentioned inversion unit (can be the inversion unit only with a H bridge module, it is also possible to for adopting the inversion unit of at least two H bridge module)。
Embodiment 2:
The present embodiment provides a kind of inversion unit, including bus capacitor C1, bus capacitor C2, three level block and H bridge module, three level block therein are T-shaped three level block 1 shown in Fig. 3。
Specifically, these T-shaped three level block 1 include transistor S5And with the diode D of its reverse parallel connection5, transistor S6And with the diode D of its reverse parallel connection6, transistor S7And with the diode D of its reverse parallel connection7, and transistor S8And with the diode D of its reverse parallel connection8。
Described transistor S6Colelctor electrode respectively with bus capacitor C1Negative pole end and bus capacitor C2Positive terminal connect, described transistor S6Emitter stage and transistor S7Emitter stage connect, described transistor S5Colelctor electrode and bus capacitor C1Positive terminal connect, described transistor S8Emitter stage and bus capacitor C2Negative pole end connect, described transistor S5Emitter stage, transistor S7Colelctor electrode and transistor S8Colelctor electrode all with the transistor S of H bridge module1Colelctor electrode, transistor S3Emitter stage connect。Here, transistor S5Colelctor electrode, transistor S6Colelctor electrode and transistor S8The input of extremely described T-shaped three level block 1 of transmitting, transistor S5Emitter stage, transistor S7Colelctor electrode and transistor S8The node that connects of colelctor electrode be the outfan of described T-shaped three level block 1。
It should be noted that other components and parts in inversion unit described in the present embodiment, such as bus capacitor C1, bus capacitor C2All identical with embodiment 1 with H bridge module, its annexation and composition, repeat no more。
The present embodiment also provides for the control method of above-mentioned inversion unit, and this control method is: the transistor S to described inversion unit1To transistor S8In any number of carry out on or off control so that the output voltage values of described inversion unit respectively Vdc、Vdc/2、0、-Vdc/ 2 and-Vdc。That is, the inversion unit that the present embodiment provides is five level inverse conversion unit, compared with prior art, only need to adopt an independent DC source E, clamp diode need not be adopted, make that the semiconductor components and devices in the five-electrical level inverter of five level inverse conversion unit and composition thereof described in the present embodiment is less, small volume, less costly, loss is less, efficiency is higher simultaneously。It should be noted that in the present embodiment and following each embodiment, control to adopt the existing chip with control function or circuit module to realize to the on or off of transistor each in inversion unit, this belongs to the known general knowledge of this area, repeats no more。
The concrete control method of above-mentioned five level inverse conversion unit is described below in conjunction with Fig. 4 to Figure 13, so that the output voltage U of described five level inverse conversion unitAOValue respectively Vdc、Vdc/2、0、-Vdc/ 2 and-Vdc, wherein UAORepresent the voltage difference between exchange output node A and the neutral point O in described five level inverse conversion unit。
As shown in Figure 4, described five level inverse conversion unit are in the first operation mode:
Control transistor S2, transistor S3With transistor S5Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load (namely being flowed to exchange output node A by inversion unit) by inversion unit, then as shown in Figure 4 A, the path of electric current is: bus capacitor C1Positive terminal → transistor S5→ diode D3→ striding capacitance Cph→ diode D2→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be Vdc；If electric current is flowed to inversion unit (namely being flowed to inversion unit by exchange output node A) by AC load, then as shown in Figure 4 B, the path of electric current is: exchange output node A → transistor S2→ striding capacitance Cph→ transistor S3→ diode D5→ bus capacitor C1Positive terminal。
As it is shown in figure 5, described five level inverse conversion unit are in the second operation mode:
Control the transistor S of described inversion unit2, transistor S3, transistor S6With transistor S7Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then as shown in Figure 5A, the path of electric current is: bus capacitor C1Negative pole end → transistor S6→ diode D7→ diode D3→ striding capacitance Cph→ diode D2→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be Vdc/ 2；If electric current is flowed to inversion unit by AC load, then as shown in Figure 5 B, the path of electric current is: exchange output node A → transistor S2→ striding capacitance Cph→ transistor S3→ transistor S7→ diode D6→ bus capacitor C1Negative pole end。
As shown in Figure 6, described five level inverse conversion unit are in the 3rd operation mode:
Control the transistor S of described inversion unit3, transistor S4With transistor S5Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then as shown in Figure 6A, the path of electric current is: bus capacitor C1Positive terminal → transistor S5→ diode D3→ transistor S4→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be Vdc/ 2；If electric current is flowed to inversion unit by AC load, then as shown in Figure 6B, the path of electric current is: exchange output node A → diode D4→ transistor S3→ diode D5→ bus capacitor C1Positive terminal。
As it is shown in fig. 7, described five level inverse conversion unit are in the 4th operation mode:
Control the transistor S of described inversion unit1, transistor S2With transistor S5Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then as shown in Figure 7 A, the path of electric current is: bus capacitor C1Positive terminal → transistor S5→ transistor S1→ diode D2→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be Vdc/ 2；If electric current is flowed to inversion unit by AC load, then as shown in Figure 7 B, the path of electric current is: exchange output node A → transistor S2→ diode D1→ diode D5→ bus capacitor C1Positive terminal。
As shown in Figure 8, described five level inverse conversion unit are in the 5th operation mode:
Control the transistor S of described inversion unit3, transistor S4, transistor S6With transistor S7Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then as shown in Figure 8 A, the path of electric current is: bus capacitor C1Negative pole end → transistor S6→ diode D7→ diode D3→ transistor S4→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be 0；If electric current is flowed to inversion unit by AC load, then as shown in Figure 8 B, the path of electric current is: exchange output node A → diode D4→ transistor S3→ transistor S7→ diode D6→ bus capacitor C1Negative pole end。
As it is shown in figure 9, described five level inverse conversion unit are in the 6th operation mode:
Control the transistor S of described inversion unit1, transistor S2, transistor S6With transistor S7Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then as shown in Figure 9 A, the path of electric current is: bus capacitor C1Negative pole end → transistor S6→ diode D7→ transistor S1→ diode D2→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be 0；If electric current is flowed to inversion unit by AC load, then as shown in Figure 9 B, the path of electric current is: exchange output node A → transistor S2→ diode D1→ transistor S7→ diode D6→ bus capacitor C1Negative pole end。
As shown in Figure 10, described five level inverse conversion unit are in the 7th operation mode:
Control the transistor S of described inversion unit1, transistor S4, transistor S6With transistor S7Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then as shown in Figure 10 A, the path of electric current is: bus capacitor C1Negative pole end → transistor S6→ diode D7→ transistor S1→ striding capacitance Cph→ transistor S4→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-Vdc/ 2；If electric current is flowed to inversion unit by AC load, then as shown in Figure 10 B, the path of electric current is: exchange output node A → diode D4→ striding capacitance Cph→ diode D1→ transistor S7→ diode D6→ bus capacitor C1Negative pole end。
As shown in figure 11, described five level inverse conversion unit are in the 8th operation mode:
Control the transistor S of described inversion unit3, transistor S4With transistor S8Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then as shown in Figure 11 A, the path of electric current is: bus capacitor C2Negative pole end → diode D8→ diode D3→ transistor S4→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-Vdc/ 2；If electric current is flowed to inversion unit by AC load, then as shown in Figure 11 B, the path of electric current is: exchange output node A → diode D4→ transistor S3→ transistor S8→ bus capacitor C2Negative pole end。
As shown in figure 12, described five level inverse conversion unit are in the 9th operation mode:
Control the transistor S of described inversion unit1, transistor S2With transistor S8Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then as illustrated in fig. 12, the path of electric current is: bus capacitor C2Negative pole end → diode D8→ transistor S1→ diode D2→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-Vdc/ 2；If electric current is flowed to inversion unit by AC load, then as shown in Figure 12 B, the path of electric current is: exchange output node A → transistor S2→ diode D1→ transistor S8→ bus capacitor C2Negative pole end。
As shown in figure 13, described five level inverse conversion unit are in the tenth operation mode:
Control the transistor S of described inversion unit1, transistor S4With transistor S8Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then as shown in FIG. 13A, the path of electric current is: bus capacitor C2Negative pole end → diode D8→ transistor S1→ striding capacitance Cph→ transistor S4→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-Vdc；If electric current is flowed to inversion unit by AC load, then as shown in Figure 13 B, the path of electric current is: exchange output node A → diode D4→ striding capacitance Cph→ diode D1→ transistor S8→ bus capacitor C2Negative pole end。
Can be seen that, each operation mode of above-mentioned five level inverse conversion unit includes meritorious operation mode (namely in circuit, electric current is identical with the direction of voltage) and idle operation mode (namely in circuit electric current and voltage in opposite direction), thus can meet AC load or AC network to idle demand。
As shown in figure 14, the present embodiment also provides for a kind of inverter, and described inverter includes three-phase inversion unit, i.e. A phase inversion unit in Figure 14, B phase inversion unit and C phase inversion unit, and wherein every phase inversion unit all adopts above-mentioned five level inverse conversion unit。
The present embodiment also provides for the expansion structure of above-mentioned five level inverse conversion unit, i.e. N level inverse conversion unit, it includes above-mentioned five level inverse conversion unit and ((N-7)/2+1) individual above-mentioned H bridge module, N takes the odd number more than or equal to 7, and should be sequentially connected in series by ((N-7)/2+1) individual H bridge module, the H bridge module of these series connection has two terminations, and meets the transistor S of the H bridge module being positioned at an end1Colelctor electrode and transistor S3Emitter stage all with the transistor S of the H bridge module in described five level inverse conversion unit2Colelctor electrode, transistor S4Emitter stage connect, be positioned at the transistor S of the H bridge module of another end2Colelctor electrode and transistor S4Emitter stage all with exchange output node A be connected, the transistor S of remaining each H bridge module1Colelctor electrode and transistor S3The transistor S of previous H bridge module of the equal series connection with it of emitter stage2Colelctor electrode, transistor S4Emitter stage connect, the transistor S of each H bridge module2Colelctor electrode and transistor S4The transistor S of later H bridge module of the equal series connection with it of emitter stage1Colelctor electrode, transistor S3Emitter stage connect。The control method of this N level inverse conversion unit can be released according to the control method of five level inverse conversion unit in the present embodiment by those skilled in the art, repeats no more。
The present embodiment also provides for a kind of inverter, and described inverter includes three-phase inversion unit, and wherein every phase inversion unit all adopts above-mentioned N level inverse conversion unit, and N takes the odd number more than or equal to 7。
Additive method in the present embodiment, structure and effect are all identical with embodiment 1, repeat no more here。
Embodiment 3:
The present embodiment provides a kind of inversion unit, including bus capacitor C1, bus capacitor C2, three level block and H bridge module, three level block therein are T-shaped three level block 2 shown in Figure 15。
Specifically, these T-shaped three level block 2 include transistor S5And with the diode D of its reverse parallel connection5, transistor S8And with the diode D of its reverse parallel connection8, and two-way power switch pipe SW1,
Described two-way power switch pipe SW1One end respectively with bus capacitor C1Negative pole end and bus capacitor C2Positive terminal connect, described transistor S5Colelctor electrode and bus capacitor C1Positive terminal connect, described transistor S8Emitter stage and bus capacitor C2Negative pole end connect, described transistor S5Emitter stage, two-way power switch pipe SW1The other end and transistor S8Colelctor electrode all with the transistor S of H bridge module1Colelctor electrode, transistor S3Emitter stage connect。Here, transistor S5Colelctor electrode, two-way power switch pipe SW1One end and transistor S8The input of extremely described T-shaped three level block 2 of transmitting, transistor S5Emitter stage, two-way power switch pipe SW1The other end and transistor S8The node that connects of colelctor electrode be the outfan of described T-shaped three level block 2。
It can be seen that compared with the structure of the structure of T-shaped three level block 2 three level block 1 T-shaped with described in embodiment 2 described in the present embodiment, differ only in: adopt two-way power switch pipe SW1Instead of transistor S6And with the diode D of its reverse parallel connection6, and transistor S7And with the diode D of its reverse parallel connection7, in other words, differ only in: described in the present embodiment, T-shaped three level block 2 do not include the diode D in T-shaped three level block 1 described in embodiment 26With diode D7。
It should be noted that other components and parts in inversion unit described in the present embodiment, such as bus capacitor C1, bus capacitor C2All identical with embodiment 1 with H bridge module, its annexation and composition, repeat no more。
The present embodiment also provides for the control method of above-mentioned inversion unit, and this control method is: the transistor S to described inversion unit1To transistor S5, transistor S8With two-way power switch pipe SW1In any number of carry out on or off control so that the output voltage values of described inversion unit respectively Vdc、Vdc/2、0、-Vdc/ 2 and-Vdc。It is to say, the inversion unit that the present embodiment provides is five level inverse conversion unit, it compared with prior art only need to adopt an independent DC source E, it is not necessary to adopts clamp diode。
The concrete control method of above-mentioned five level inverse conversion unit is described below, so that the output voltage U of described five level inverse conversion unitAOValue respectively Vdc、Vdc/2、0、-Vdc/ 2 and-Vdc, wherein UAORepresent the voltage difference exchanging between output node A and neutral point O in described five level inverse conversion unit。
Described five level inverse conversion unit are in the first operation mode:
Control transistor S2, transistor S3With transistor S5Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load (namely being flowed to exchange output node A by inversion unit) by inversion unit, then the path of electric current is: bus capacitor C1Positive terminal → transistor S5→ diode D3→ striding capacitance Cph→ diode D2→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be Vdc；If electric current is flowed to inversion unit (namely being flowed to inversion unit by exchange output node A) by AC load, then the path of electric current is: exchange output node A → transistor S2→ striding capacitance Cph→ transistor S3→ diode D5→ bus capacitor C1Positive terminal。
Described five level inverse conversion unit are in the second operation mode:
Control the transistor S of described inversion unit2, transistor S3With two-way power switch pipe SW1Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C1Negative pole end → two-way power switch pipe SW1→ diode D3→ striding capacitance Cph→ diode D2→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be Vdc/ 2；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → transistor S2→ striding capacitance Cph→ transistor S3→ two-way power switch pipe SW1→ bus capacitor C1Negative pole end。
Described five level inverse conversion unit are in the 3rd operation mode:
Control the transistor S of described inversion unit3, transistor S4With transistor S5Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C1Positive terminal → transistor S5→ diode D3→ transistor S4→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be Vdc/ 2；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → diode D4→ transistor S3→ diode D5→ bus capacitor C1Positive terminal。
Described five level inverse conversion unit are in the 4th operation mode:
Control the transistor S of described inversion unit1, transistor S2With transistor S5Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C1Positive terminal → transistor S5→ transistor S1→ diode D2→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be Vdc/ 2；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → transistor S2→ diode D1→ diode D5→ bus capacitor C1Positive terminal。
Described five level inverse conversion unit are in the 5th operation mode:
Control the transistor S of described inversion unit3, transistor S4With two-way power switch pipe SW1Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C1Negative pole end → two-way power switch pipe SW1→ diode D3→ transistor S4→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be 0；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → diode D4→ transistor S3→ two-way power switch pipe SW1→ bus capacitor C1Negative pole end。
Described five level inverse conversion unit are in the 6th operation mode:
Control the transistor S of described inversion unit1, transistor S2With two-way power switch pipe SW1Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C1Negative pole end → two-way power switch pipe SW1→ transistor S1→ diode D2→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be 0；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → transistor S2→ diode D1→ two-way power switch pipe SW1→ bus capacitor C1Negative pole end。
Described five level inverse conversion unit are in the 7th operation mode:
Control the transistor S of described inversion unit1, transistor S4With two-way power switch pipe SW1Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C1Negative pole end → two-way power switch pipe SW1→ transistor S1→ striding capacitance Cph→ transistor S4→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-Vdc/ 2；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → diode D4→ striding capacitance Cph→ diode D1→ two-way power switch pipe SW1→ bus capacitor C1Negative pole end。
Described five level inverse conversion unit are in the 8th operation mode:
Control the transistor S of described inversion unit3, transistor S4With transistor S8Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C2Negative pole end → diode D8→ diode D3→ transistor S4→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-Vdc/ 2；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → diode D4→ transistor S3→ transistor S8→ bus capacitor C2Negative pole end。
Described five level inverse conversion unit are in the 9th operation mode:
Control the transistor S of described inversion unit1, transistor S2With transistor S8Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C2Negative pole end → diode D8→ transistor S1→ diode D2→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-Vdc/ 2；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → transistor S2→ diode D1→ transistor S8→ bus capacitor C2Negative pole end。
Described five level inverse conversion unit are in the tenth operation mode:
Control the transistor S of described inversion unit1, transistor S4With transistor S8Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C2Negative pole end → diode D8→ transistor S1→ striding capacitance Cph→ transistor S4→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-Vdc；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → diode D4→ striding capacitance Cph→ diode D1→ transistor S8→ bus capacitor C2Negative pole end。
Can be seen that, each operation mode of above-mentioned five level inverse conversion unit includes meritorious operation mode (namely in circuit, electric current is identical with the direction of voltage) and idle operation mode (namely in circuit electric current and voltage in opposite direction), thus can meet AC load or AC network to idle demand。
As shown in figure 16, the present embodiment also provides for a kind of inverter, and described inverter includes three-phase inversion unit, i.e. A phase inversion unit in Figure 16, B phase inversion unit and C phase inversion unit, and wherein every phase inversion unit all adopts above-mentioned five level inverse conversion unit。
The present embodiment also provides for the expansion structure of above-mentioned five level inverse conversion unit, i.e. N level inverse conversion unit, it includes above-mentioned five level inverse conversion unit and ((N-7)/2+1) individual above-mentioned H bridge module, N takes the odd number more than or equal to 7, and should be sequentially connected in series by ((N-7)/2+1) individual H bridge module, the H bridge module of these series connection has two terminations, and meets the transistor S of the H bridge module being positioned at an end1Colelctor electrode and transistor S3Emitter stage all with the transistor S of the H bridge module in described five level inverse conversion unit2Colelctor electrode, transistor S4Emitter stage connect, be positioned at the transistor S of the H bridge module of another end2Colelctor electrode and transistor S4Emitter stage all with exchange output node A be connected, the transistor S of remaining each H bridge module1Colelctor electrode and transistor S3The transistor S of previous H bridge module of the equal series connection with it of emitter stage2Colelctor electrode, transistor S4Emitter stage connect, the transistor S of each H bridge module2Colelctor electrode and transistor S4The transistor S of later H bridge module of the equal series connection with it of emitter stage1Colelctor electrode, transistor S3Emitter stage connect。The control method of this N level inverse conversion unit can be released according to the control method of five level inverse conversion unit in the present embodiment by those skilled in the art, repeats no more。
The present embodiment also provides for a kind of inverter, and described inverter includes three-phase inversion unit, and wherein every phase inversion unit all adopts above-mentioned N level inverse conversion unit, and N takes the odd number more than or equal to 7。
Additive method in the present embodiment, structure and effect are all identical with embodiment 1, repeat no more here。
Embodiment 4:
The present embodiment provides a kind of inversion unit, including bus capacitor C1, bus capacitor C2, three level block and H bridge module, three level block therein are I type three level block shown in Figure 17。
Specifically, this I type three level block includes transistor S5And with the diode D of its reverse parallel connection5, transistor S6And with the diode D of its reverse parallel connection6, transistor S7And with the diode D of its reverse parallel connection7, transistor S8And with the diode D of its reverse parallel connection8, diode D9With diode D10,
Described transistor S5Colelctor electrode and bus capacitor C1Positive terminal connect, described transistor S5Emitter stage and transistor S6Colelctor electrode connect, described transistor S6Emitter stage and transistor S7Colelctor electrode connect, described transistor S7Emitter stage and transistor S8Colelctor electrode connect, described transistor S8Emitter stage and bus capacitor C2Negative pole end connect, described diode D9Negative pole respectively with transistor S5Emitter stage and transistor S6Colelctor electrode connect, described diode D10Positive pole respectively with transistor S7Emitter stage and transistor S8Colelctor electrode connect, described diode D9Positive pole and diode D10Negative pole all with bus capacitor C1Negative pole end, bus capacitor C2Positive terminal connect。Here, transistor S5Colelctor electrode, diode D9Positive pole, diode D10Negative pole and transistor S8The input of transmitting extremely described I type three level block, transistor S6Emitter stage and transistor S7The node that connects of colelctor electrode be the outfan of described I type three level block。Described diode D9With diode D10For clamp diode。
It should be noted that other components and parts in inversion unit described in the present embodiment, such as bus capacitor C1, bus capacitor C2All identical with embodiment 1 with H bridge module, its annexation and composition, repeat no more。
The present embodiment also provides for the control method of above-mentioned inversion unit, and this control method is: the transistor S to described inversion unit1To transistor S8In any number of carry out on or off control so that the output voltage values of described inversion unit respectively Vdc、Vdc/2、0、-Vdc/ 2 and-Vdc。It is to say, the inversion unit that the present embodiment provides is five level inverse conversion unit, it compared with prior art only need to adopt an independent DC source E and two clamp diodes。
The concrete control method of above-mentioned five level inverse conversion unit is described below, so that the output voltage U of described five level inverse conversion unitAOValue respectively Vdc、Vdc/2、0、-Vdc/ 2 and-Vdc, wherein UAORepresent the voltage difference exchanging between output node A and neutral point O in described five level inverse conversion unit。
Described five level inverse conversion unit are in the first operation mode:
Control transistor S2, transistor S3, transistor S5With transistor S6Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load (namely being flowed to exchange output node A by inversion unit) by inversion unit, then the path of electric current is: bus capacitor C1Positive terminal → transistor S5→ transistor S6→ diode D3→ striding capacitance Cph→ diode D2→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be Vdc；If electric current is flowed to inversion unit (namely being flowed to inversion unit by exchange output node A) by AC load, then the path of electric current is: exchange output node A → transistor S2→ striding capacitance Cph→ transistor S3→ diode D6→ diode D5→ bus capacitor C1Positive terminal。
Described five level inverse conversion unit are in the second operation mode:
Control the transistor S of described inversion unit2, transistor S3, transistor S6With transistor S7Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C1Negative pole end → diode D9→ transistor S6→ diode D3→ striding capacitance Cph→ diode D2→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be Vdc/ 2；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → transistor S2→ striding capacitance Cph→ transistor S3→ transistor S7→ diode D10→ bus capacitor C1Negative pole end。
Described five level inverse conversion unit are in the 3rd operation mode:
Control the transistor S of described inversion unit3, transistor S4, transistor S5With transistor S6Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C1Positive terminal → transistor S5→ transistor S6→ diode D3→ transistor S4→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be Vdc/ 2；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → diode D4→ transistor S3→ diode D6→ diode D5→ bus capacitor C1Positive terminal。
Described five level inverse conversion unit are in the 4th operation mode:
Control the transistor S of described inversion unit1, transistor S2Transistor S5With transistor S6Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C1Positive terminal → transistor S5→ transistor S6→ transistor S1→ diode D2→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be Vdc/ 2；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → transistor S2→ diode D1→ diode D6→ diode D5→ bus capacitor C1Positive terminal。
Described five level inverse conversion unit are in the 5th operation mode:
Control the transistor S of described inversion unit3, transistor S4, transistor S6With transistor S7Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C1Negative pole end → diode D9→ transistor S6→ diode D3→ transistor S4→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be 0；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → diode D4→ transistor S3→ transistor S7→ diode D10→ bus capacitor C1Negative pole end。
Described five level inverse conversion unit are in the 6th operation mode:
Control the transistor S of described inversion unit1, transistor S2, transistor S6With transistor S7Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C1Negative pole end → diode D9→ transistor S6→ transistor S1→ diode D2→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be 0；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → transistor S2→ diode D1→ transistor S7→ diode D10→ bus capacitor C1Negative pole end。
Described five level inverse conversion unit are in the 7th operation mode:
Control the transistor S of described inversion unit1, transistor S4, transistor S6With transistor S7Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C1Negative pole end → diode D9→ transistor S6→ transistor S1→ striding capacitance Cph→ transistor S4→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-Vdc/ 2；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → diode D4→ striding capacitance Cph→ diode D1→ transistor S7→ diode D10→ bus capacitor C1Negative pole end。
Described five level inverse conversion unit are in the 8th operation mode:
Control the transistor S of described inversion unit3, transistor S4, transistor S7With transistor S8Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C2Negative pole end → diode D8→ diode D7→ diode D3→ transistor S4→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-Vdc/ 2；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → diode D4→ transistor S3→ transistor S7→ transistor S8→ bus capacitor C2Negative pole end。
Described five level inverse conversion unit are in the 9th operation mode:
Control the transistor S of described inversion unit1, transistor S2, transistor S7With transistor S8Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C2Negative pole end → diode D8→ diode D7→ transistor S1→ diode D2→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-Vdc/ 2；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → transistor S2→ diode D1→ transistor S7→ transistor S8→ bus capacitor C2Negative pole end。
Described five level inverse conversion unit are in the tenth operation mode:
Control the transistor S of described inversion unit1, transistor S4, transistor S7With transistor S8Conducting, and control the shutoff of all the other transistors。If electric current is flowed to AC load by inversion unit, then the path of electric current is: bus capacitor C2Negative pole end → diode D8→ diode D7→ transistor S1→ striding capacitance Cph→ transistor S4→ exchange output node A, now, the output voltage U of described five level inverse conversion unitAOValue be-Vdc；If electric current is flowed to inversion unit by AC load, then the path of electric current is: exchange output node A → diode D4→ striding capacitance Cph→ diode D1→ transistor S7→ transistor S8→ bus capacitor C2Negative pole end。
Can be seen that, each operation mode of above-mentioned five level inverse conversion unit includes meritorious operation mode (namely in circuit, electric current is identical with the direction of voltage) and idle operation mode (namely in circuit electric current and voltage in opposite direction), thus can meet AC load or AC network to idle demand。
As shown in figure 18, the present embodiment also provides for a kind of inverter, and described inverter includes three-phase inversion unit, i.e. A phase inversion unit in Figure 18, B phase inversion unit and C phase inversion unit, and wherein every phase inversion unit all adopts above-mentioned five level inverse conversion unit。
The present embodiment also provides for the expansion structure of above-mentioned five level inverse conversion unit, i.e. N level inverse conversion unit, it includes above-mentioned five level inverse conversion unit and ((N-7)/2+1) individual above-mentioned H bridge module, N takes the odd number more than or equal to 7, and should be sequentially connected in series by ((N-7)/2+1) individual H bridge module, the H bridge module of these series connection has two terminations, and meets the transistor S of the H bridge module being positioned at an end1Colelctor electrode and transistor S3Emitter stage all with the transistor S of the H bridge module in described five level inverse conversion unit2Colelctor electrode, transistor S4Emitter stage connect, be positioned at the transistor S of the H bridge module of another end2Colelctor electrode and transistor S4Emitter stage all with exchange output node A be connected, the transistor S of remaining each H bridge module1Colelctor electrode and transistor S3The transistor S of previous H bridge module of the equal series connection with it of emitter stage2Colelctor electrode, transistor S4Emitter stage connect, the transistor S of each H bridge module2Colelctor electrode and transistor S4The transistor S of later H bridge module of the equal series connection with it of emitter stage1Colelctor electrode, transistor S3Emitter stage connect。The control method of this N level inverse conversion unit can be released according to the control method of five level inverse conversion unit in the present embodiment by those skilled in the art, repeats no more。
The present embodiment also provides for a kind of inverter, and described inverter includes three-phase inversion unit, and wherein every phase inversion unit all adopts above-mentioned N level inverse conversion unit, and N takes the odd number more than or equal to 7。
Additive method in the present embodiment, structure and effect are all identical with embodiment 1, repeat no more here。
It is understood that the principle that is intended to be merely illustrative of the present of embodiment of above and the illustrative embodiments that adopts, but the invention is not limited in this。For those skilled in the art, without departing from the spirit and substance in the present invention, it is possible to make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention。
Claims (11)
1. an inversion unit, it is characterised in that include bus capacitor C1, bus capacitor C2, three level block and H bridge module, described H bridge module includes transistor S1And with the diode D of its reverse parallel connection1, transistor S2And with the diode D of its reverse parallel connection2, transistor S3And with the diode D of its reverse parallel connection3, transistor S4And with the diode D of its reverse parallel connection4, and striding capacitance Cph,
Described bus capacitor C1With bus capacitor C2Series connection, and bus capacitor C1Positive terminal be connected with the positive terminal of DC source, bus capacitor C2Negative pole end be connected with the negative pole end of DC source, bus capacitor C1, bus capacitor C2Positive terminal and negative pole end be all connected with the input of three level block；
In described H bridge module, described transistor S1Colelctor electrode and transistor S3Emitter stage connect, described transistor S1Emitter stage, striding capacitance CphPositive terminal and transistor S2Emitter stage connect, described transistor S3Colelctor electrode, striding capacitance CphNegative pole end and transistor S4Colelctor electrode connect, described transistor S2Colelctor electrode and transistor S4Emitter stage be all connected with exchange output node, and transistor S1Colelctor electrode and transistor S3Emitter stage be all connected with the outfan of three level block；
Described bus capacitor C1, bus capacitor C2With striding capacitance CphThe magnitude of voltage at two ends is Vdc/ 2, and VdcMagnitude of voltage for described DC source two ends。
2. inversion unit according to claim 1, it is characterised in that
Described three level block include transistor S5And with the diode D of its reverse parallel connection5, transistor S6And with the diode D of its reverse parallel connection6, transistor S7And with the diode D of its reverse parallel connection7, and transistor S8And with the diode D of its reverse parallel connection8,
Described transistor S6Colelctor electrode respectively with bus capacitor C1Negative pole end and bus capacitor C2Positive terminal connect, described transistor S6Emitter stage and transistor S7Emitter stage connect, described transistor S5Colelctor electrode and bus capacitor C1Positive terminal connect, described transistor S8Emitter stage and bus capacitor C2Negative pole end connect, described transistor S5Emitter stage, transistor S7Colelctor electrode and transistor S8Colelctor electrode all with the transistor S of H bridge module1Colelctor electrode, transistor S3Emitter stage connect。
3. inversion unit according to claim 1, it is characterised in that
Described three level block include transistor S5And with the diode D of its reverse parallel connection5, transistor S8And with the diode D of its reverse parallel connection8, and two-way power switch pipe SW1,
Described two-way power switch pipe SW1One end respectively with bus capacitor C1Negative pole end and bus capacitor C2Positive terminal connect, described transistor S5Colelctor electrode and bus capacitor C1Positive terminal connect, described transistor S8Emitter stage and bus capacitor C2Negative pole end connect, described transistor S5Emitter stage, two-way power switch pipe SW1The other end and transistor S8Colelctor electrode all with the transistor S of H bridge module1Colelctor electrode, transistor S3Emitter stage connect。
4. inversion unit according to claim 1, it is characterised in that
Described three level block include transistor S5And with the diode D of its reverse parallel connection5, transistor S6And with the diode D of its reverse parallel connection6, transistor S7And with the diode D of its reverse parallel connection7, transistor S8And with the diode D of its reverse parallel connection8, diode D9With diode D10,
Described transistor S5Colelctor electrode and bus capacitor C1Positive terminal connect, described transistor S5Emitter stage and transistor S6Colelctor electrode connect, described transistor S6Emitter stage and transistor S7Colelctor electrode connect, described transistor S7Emitter stage and transistor S8Colelctor electrode connect, described transistor S8Emitter stage and bus capacitor C2Negative pole end connect, described diode D9Negative pole respectively with transistor S5Emitter stage and transistor S6Colelctor electrode connect, described diode D10Positive pole respectively with transistor S7Emitter stage and transistor S8Colelctor electrode connect, described diode D9Positive pole and diode D10Negative pole all with bus capacitor C1Negative pole end, bus capacitor C2Positive terminal connect。
5. the inversion unit according to any one of Claims 1 to 4, it is characterised in that the transistor adopted in described inversion unit is insulated gate bipolar transistor。
6. the inversion unit according to any one of Claims 1 to 4, it is characterised in that
Described H bridge module in described inversion unit adopts at least two, and this at least two H bridge module is sequentially connected in series, and the H bridge module of these series connection has two terminations, is wherein positioned at the transistor S of the H bridge module of an end1Colelctor electrode and transistor S3Emitter stage be all connected with the outfan of three level block, be positioned at the transistor S of the H bridge module of another end2Colelctor electrode and transistor S4Emitter stage all with exchange output node be connected, the transistor S of remaining each H bridge module1Colelctor electrode and transistor S3The transistor S of previous H bridge module of the equal series connection with it of emitter stage2Colelctor electrode, transistor S4Emitter stage connect, the transistor S of each H bridge module2Colelctor electrode and transistor S4The transistor S of later H bridge module of the equal series connection with it of emitter stage1Colelctor electrode, transistor S3Emitter stage connect。
7. the control method of inversion unit as according to any one of Claims 1 to 5, it is characterized in that, described control method is: each semiconductor components and devices in described inversion unit is carried out on or off control, so that the output voltage values of described inversion unit respectively Vdc、Vdc/2、0、-Vdc/ 2 and-Vdc, the output voltage values of described inversion unit is the voltage difference between described exchange output node and neutral point。
8. control method according to claim 7, it is characterised in that described control method is used for controlling inversion unit as claimed in claim 2, specifically includes:
Control the transistor S of described inversion unit2, transistor S3With transistor S5Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is Vdc；
Control the transistor S of described inversion unit2, transistor S3, transistor S6With transistor S7Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is Vdc/ 2；Or, control the transistor S of described inversion unit3, transistor S4With transistor S5Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is Vdc/ 2；Or, control the transistor S of described inversion unit1, transistor S2With transistor S5Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is Vdc/ 2；
Control the transistor S of described inversion unit3, transistor S4, transistor S6With transistor S7Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is 0；Or, control the transistor S of described inversion unit1, transistor S2, transistor S6With transistor S7Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is 0；
Control the transistor S of described inversion unit1, transistor S4, transistor S6With transistor S7Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-Vdc/ 2；Or, control the transistor S of described inversion unit3, transistor S4With transistor S8Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-Vdc/ 2；Or, control the transistor S of described inversion unit1, transistor S2With transistor S8Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-Vdc/ 2；
Control the transistor S of described inversion unit1, transistor S4With transistor S8Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-Vdc。
9. control method according to claim 7, it is characterised in that described control method is used for controlling inversion unit as claimed in claim 3, specifically includes:
Control the transistor S of described inversion unit2, transistor S3With transistor S5Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is Vdc；
Control the transistor S of described inversion unit2, transistor S3With two-way power switch pipe SW1Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is Vdc/ 2；Or, control the transistor S of described inversion unit3, transistor S4With transistor S5Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is Vdc/ 2；Or, control the transistor S of described inversion unit1, transistor S2With transistor S5Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is Vdc/ 2；
Control the transistor S of described inversion unit3, transistor S4With two-way power switch pipe SW1Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is 0；Or, control the transistor S of described inversion unit1, transistor S2With two-way power switch pipe SW1Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is 0；
Control the transistor S of described inversion unit1, transistor S4With two-way power switch pipe SW1Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-Vdc/ 2；Or, control the transistor S of described inversion unit3, transistor S4With transistor S8Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-Vdc/ 2；Or, control the transistor S of described inversion unit1, transistor S2With transistor S8Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-Vdc/ 2；
Control the transistor S of described inversion unit1, transistor S4With transistor S8Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-Vdc。
10. control method according to claim 7, it is characterised in that described control method is used for controlling inversion unit as claimed in claim 4, specifically includes:
Control the transistor S of described inversion unit2, transistor S3, transistor S5With transistor S6Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is Vdc；
Control the transistor S of described inversion unit2, transistor S3, transistor S6With transistor S7Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is Vdc/ 2；Or, control the transistor S of described inversion unit3, transistor S4, transistor S5With transistor S6Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is Vdc/ 2；Or, control the transistor S of described inversion unit1, transistor S2, transistor S5With transistor S6Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is Vdc/ 2；
Control the transistor S of described inversion unit3, transistor S4, transistor S6With transistor S7Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is 0；Or, control the transistor S of described inversion unit1, transistor S2, transistor S6With transistor S7Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is 0；
Control the transistor S of described inversion unit1, transistor S4, transistor S6With transistor S7Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-Vdc/ 2；Or, control the transistor S of described inversion unit3, transistor S4, transistor S7With transistor S8Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-Vdc/ 2；Or, control the transistor S of described inversion unit1, transistor S2, transistor S7With transistor S8Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-Vdc/ 2；
Control the transistor S of described inversion unit1, transistor S4, transistor S7With transistor S8Conducting, and control the shutoff of all the other transistors, then the output voltage values of described inversion unit is-Vdc。
11. an inverter, including three-phase inversion unit, it is characterised in that every phase inversion unit all adopts the inversion unit as according to any one of claim 1～6。
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