CN112614787B - Packaging method for chip packaging - Google Patents
Packaging method for chip packaging Download PDFInfo
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- CN112614787B CN112614787B CN202011617859.9A CN202011617859A CN112614787B CN 112614787 B CN112614787 B CN 112614787B CN 202011617859 A CN202011617859 A CN 202011617859A CN 112614787 B CN112614787 B CN 112614787B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 117
- 239000002184 metal Substances 0.000 claims abstract description 117
- 230000003071 parasitic effect Effects 0.000 claims abstract description 38
- 239000003990 capacitor Substances 0.000 claims description 8
- 238000000926 separation method Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- -1 moisture Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000004224 protection Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1405—Shape
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a packaging method of chip packaging, which comprises the steps of performing primary Bump on parasitic capacitance on a chip on a wafer to form a first metal Bump, performing secondary Bump on the first metal Bump to form a second metal Bump, forming annular concave between the first metal Bump and the second metal Bump, and performing subsequent conventional chip packaging operation flow on the chip with the first metal Bump and the second metal Bump. The first metal convex points and the second metal convex points are formed through the primary Bump and the secondary Bump, annular depressions are formed between the first metal convex points and the second metal convex points, the annular depressions can be well combined with the plastic package body during plastic package, the plastic package body can be buckled by the annular depressions, the contact area between the annular depressions and the plastic package body is increased, the bonding degree is increased, the first metal convex points, the second metal convex points and the plastic package body are not easy to separate during the grinding process, the probability of separation between the first metal convex points and parasitic capacitance is also reduced, and the reliability of the chip is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a packaging method of chip packaging.
Background
With the development of electronic products, semiconductor technology has been widely used for manufacturing memories, central Processing Units (CPUs), liquid crystal display devices (LCDs), light Emitting Diodes (LEDs), laser diodes, and other devices or chip sets.
Because electronic components such as semiconductor components, micro-electromechanical components (MEMS) or optoelectronic components have very fine circuits and structures, in order to avoid pollution or corrosion of the electronic components by dust, acid-base substances, moisture, oxygen, etc., and further affect the reliability and life thereof, the technology needs to provide the functions of the electronic components such as electrical energy creation, signal transmission, heat dissipation, protection and support, etc. by using packaging technology.
Semiconductor packaging refers to the process of processing a wafer that passes testing to obtain individual chips according to product model and functional requirements. The packaging process is as follows: the wafer from the wafer front process is cut into small chips (Die) through the dicing process, then the cut chips are attached to the corresponding islands of the substrate (Lead frame) frame by glue, and then the bonding pads (Bond pads) of the chips are connected to the corresponding pins (Lead) of the substrate by using ultra-fine metal (gold tin copper aluminum) wires or conductive resin, and the required circuit is formed; and then packaging and protecting the independent wafer by using a plastic shell, performing a series of operations after plastic packaging, performing finished product testing after packaging, generally performing procedures such as checking in, testing Test and packaging, and finally warehousing and delivering.
In the field of chip packaging, before packaging the chip, a Bump needs to be performed on the chip on the wafer, namely, a metal Bump is arranged on a parasitic capacitance of the chip, and then a subsequent packaging operation is performed, but in the current Bump process, a metal Bump is directly arranged on the parasitic capacitance of the chip on the wafer, after plastic packaging, the metal Bump is easy to separate from the chip due to the influence of the subsequent process, particularly, the metal Bump is easy to be generated in the grinding process of a plastic package body, so that the reliability of the chip is reduced, and when the size control of the metal Bump and the bonding degree between the metal Bump and the chip need to be considered, different problems such as easy short circuit when the parasitic capacitance density on the chip is relatively large, small parasitic capacitance on the chip is formed, the basic surface between the metal Bump and the RDL rerouting wire is small, the bonding degree is reduced, and the requirement on the Bump process is easy to be considered, so that the difficulty in the Bump process is greatly increased, and a solution is required to be provided for the phenomenon.
Disclosure of Invention
The invention provides a packaging method for chip packaging, which aims at the defects existing in the prior art.
In order to solve the problems, the technical scheme adopted by the invention is as follows:
A packaging method of chip packaging includes carrying out primary Bump on parasitic capacitance on chip on wafer to form first metal Bump, carrying out secondary Bump on first metal Bump to form second metal Bump, forming annular concave between first metal Bump and second metal Bump, carrying out follow-up normal chip packaging operation flow on chip with first metal Bump and second metal Bump.
Further, the parasitic capacitance on the chip is completely covered by the first metal protruding point, so that the cohesiveness is increased.
Further, the first metal bump and the second metal bump are located on the same axis, and the axis is perpendicular to the surface formed by the wafer where the chip is located.
Further, in the secondary Bump, the size of the second metal Bump is designed to be the same as the size of the first metal Bump, or larger than the size of the first metal Bump, or smaller than the size of the first metal Bump.
Further, on the same wafer, the primary and secondary voltage are performed for the same parasitic capacitance in sequence, and then the primary and secondary voltage operation of the next parasitic capacitance is performed.
Further, on the same wafer, all parasitic capacitances on the wafer are subjected to primary voltage clamping and then subjected to secondary voltage clamping operation.
Compared with the prior art, the invention has the following beneficial effects: the first metal convex points and the second metal convex points are formed through the primary Bump and the secondary Bump, annular depressions are formed between the first metal convex points and the second metal convex points, the annular depressions can be well combined with the plastic package body during plastic package, the plastic package body can be buckled by the annular depressions, the contact area between the annular depressions and the plastic package body is increased, the bonding degree is increased, the first metal convex points, the second metal convex points and the plastic package body are not easy to separate during the grinding process, the probability of separation between the first metal convex points and parasitic capacitance is also reduced, and the reliability of the chip is improved.
The size of the second metal Bump is controlled through the secondary Bump, so that the problems that when parasitic capacitance on a chip to be packaged is very tight, the first metal Bump is tightly attached to the parasitic capacitance and is completely covered, the connection effectiveness between the first metal Bump and the parasitic capacitance is ensured, then the size of the second metal Bump is reduced, the distance between adjacent second metal bumps is increased, and when RDL is rerouted, the phenomenon that the adjacent second metal bumps are short-circuited can be effectively avoided, the reliability of the chip is increased, and the product yield is improved;
In order to ensure the high efficiency of the high-speed signal of the chip, the parasitic capacitance on the packaged chip is generally required to be designed to be very small, when the parasitic capacitance is very small, the first metal Bump covering the parasitic capacitance is very small.
Drawings
FIG. 1 is a schematic diagram of a first metal bump, a second metal bump and a chip according to a first embodiment;
FIG. 2 is a schematic diagram of a chip package according to a first embodiment;
FIG. 3 is a schematic diagram of a first metal bump, a second metal bump and a chip according to a second embodiment;
FIG. 4 is a schematic diagram of a chip package in a second embodiment;
fig. 5 is a schematic structural diagram of a first metal bump, a second metal bump and a chip in a third embodiment;
fig. 6 is a schematic structural diagram of a chip package in the third embodiment.
Detailed Description
The present invention will be described below in conjunction with specific embodiments, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functionality throughout.
The directional terms mentioned in this invention are, for example: the upper, lower, left, right, front, rear, inner, outer, front, back, side, etc. are only with reference to the directions of the drawings, and the embodiments and directional terms used below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present invention. In addition, various specific examples of processes and materials are provided herein, as will be appreciated by those of ordinary skill in the art as applications of other processes and/or use of other materials.
Embodiment one:
Referring to fig. 1 and fig. 2 together, fig. 1 is a schematic structural diagram of a first metal bump, a second metal bump and a chip in a first embodiment; fig. 2 is a schematic structural diagram of a chip package according to a first embodiment.
A packaging method of chip package comprises the steps of performing Bump on a wafer a once on a parasitic capacitor 11 on a chip 10 to form a first metal Bump 20, wherein the first metal Bump 20 completely covers the parasitic capacitor 11 on the chip 10, and the adhesion is increased.
And performing secondary Bump on the first metal Bump 20 to form a second metal Bump 30, wherein the first metal Bump 20 and the second metal Bump 30 are positioned on the same axis, and the axis is perpendicular to the surface formed by the wafer a where the chip 10 is positioned, so that the operation and the setting of process parameters are facilitated, and the production efficiency is improved.
The annular concave b is arranged between the first metal bump 20 and the second metal bump 30, the sizes of the first metal bump 20 and the second metal bump 30 are the same, and in the same space size, the annular concave b is designed to increase the connection surface between the first metal bump 20 and the second metal bump 30 and the plastic package material, as shown in fig. 2, so as to increase the stability and the bonding degree, prevent the first metal bump 20 and the second metal bump 30 from being separated from the plastic package material during the later grinding, and reduce the probability of disconnection between the first metal bump 20 and the chip 10 due to the external force of grinding, thereby improving the reliability of the chip and the product yield.
The first metal bump 20 and the second metal bump 30 are designed to be the same in size, so that the production efficiency is improved, and defective products are reduced.
For different wafer characteristics, and different metals as raw materials of the primary and secondary bus, the raw materials of the primary and secondary bus may be the same, or may be different, on the same wafer a, the primary and secondary bus are sequentially performed for the same parasitic capacitor 11, and then the primary and secondary bus operation of the next parasitic capacitor 11 is performed, or after all the parasitic capacitors 11 on the wafer a are subjected to the primary bus operation, the secondary bus operation is performed.
The chip 10 with the first and second metal bumps 20, 30 is subjected to subsequent chip conventional packaging operations such as flip-chip, fan-out packaging, etc.
Embodiment two:
Referring to fig. 3 and fig. 4 together, fig. 3 is a schematic structural diagram of a first metal bump, a second metal bump and a chip in a second embodiment; fig. 4 is a schematic structural diagram of a chip package in the second embodiment.
The operation of this embodiment is the same as that of the first embodiment, with the only differences as follows: in the secondary Bump process, the size of the second metal Bump 30 is designed to be smaller than that of the first metal Bump 20, when the parasitic capacitance 11 on the chip 10 to be packaged is very tight, as shown in fig. 4, the first metal Bump 20 is tightly attached to the parasitic capacitance 11 and completely covers the parasitic capacitance 11, so that the connection effectiveness between the first metal Bump 20 and the parasitic capacitance 11 is ensured, then the size of the second metal Bump 30 is reduced, the interval between the adjacent second metal bumps 30 is increased, and when RDL rewiring, the occurrence of short circuit phenomenon of the adjacent second metal Bump 30 can be effectively avoided, the reliability of the chip 10 is increased, and the product yield is improved.
Embodiment III:
Referring to fig. 5 and fig. 6 together, fig. 5 is a schematic structural diagram of a first metal bump, a second metal bump and a chip in a third embodiment; fig. 6 is a schematic structural diagram of a chip package in the third embodiment.
The operation of this embodiment is the same as that of the first embodiment, with the only differences as follows: in the secondary Bump, the size of the second metal Bump 30 is designed to be larger than that of the first metal Bump 20, in order to ensure the high efficiency of the high-speed signal of the chip 10, the parasitic capacitance 11 on the packaged chip 10 needs to be designed to be very small, and when the parasitic capacitance 11 is very small, the first metal Bump 20 covering the parasitic capacitance is very small.
Compared with the prior art, the invention has the following beneficial effects:
The first metal convex points and the second metal convex points are formed through the primary Bump and the secondary Bump, annular depressions are formed between the first metal convex points and the second metal convex points, the annular depressions can be well combined with the plastic package body during plastic package, the plastic package body can be buckled by the annular depressions, the contact area between the annular depressions and the plastic package body is increased, the bonding degree is increased, the first metal convex points, the second metal convex points and the plastic package body are not easy to separate during the grinding process, the probability of separation between the first metal convex points and parasitic capacitance is also reduced, and the reliability of the chip is improved.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (4)
1. A packaging method of chip packaging is characterized in that parasitic capacitance (11) on a chip (10) is subjected to primary Bump on a wafer (a) to form a first metal Bump (20), the first metal Bump (20) completely covers the parasitic capacitance (11) on the chip (10), the adhesion is increased, secondary Bump is performed on the first metal Bump (20) to form a second metal Bump (30), annular concave parts (b) are arranged between the first metal Bump (20) and the second metal Bump (30), the chip (10) with the first metal Bump (20) and the second metal Bump (30) is subjected to subsequent conventional chip packaging operation flow, and in the secondary Bump, the size of the second metal Bump (30) is designed to be larger than the size of the first metal Bump (20) or smaller than the size of the first metal Bump (20), when parasitic capacitance (11) on the chip (10) is compact, the size of the second metal Bump (30) is designed to be smaller than the size of the first metal Bump (20), circuit short circuit of adjacent second metal bumps (30) due to the fact that the distance is close to RDL rerouting is avoided, when the size of parasitic capacitance (11) on the chip (10) is small, the size of the second metal Bump (30) is designed to be larger than the size of the first metal Bump (20), the contact area between the second metal Bump (30) and RDL rerouting is increased, circuit breaking due to the too small size of the first metal bump (20) is avoided.
2. The method of packaging a chip package according to claim 1, wherein the first metal bump (20) and the second metal bump (30) are on the same axis, the axis being perpendicular to the face of the wafer (a) on which the chip (10) is located.
3. The method of claim 1, wherein the first and second Bump operations are performed on the same wafer (a) for the same parasitic capacitor (11) and then the first and second Bump operations are performed on the next parasitic capacitor (11).
4. The method of claim 1, wherein the parasitic capacitors (11) on the same wafer (a) are subjected to a first Bump operation and then to a second Bump operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011617859.9A CN112614787B (en) | 2020-12-31 | 2020-12-31 | Packaging method for chip packaging |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011617859.9A CN112614787B (en) | 2020-12-31 | 2020-12-31 | Packaging method for chip packaging |
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| Publication Number | Publication Date |
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| CN112614787A CN112614787A (en) | 2021-04-06 |
| CN112614787B true CN112614787B (en) | 2024-05-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202011617859.9A Active CN112614787B (en) | 2020-12-31 | 2020-12-31 | Packaging method for chip packaging |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7446419B1 (en) * | 2004-11-10 | 2008-11-04 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar of stacked metal balls |
| CN101809737A (en) * | 2007-08-16 | 2010-08-18 | 美光科技公司 | stacked microelectronic devices and methods for manufaturing staked microelectronic devices |
| CN105551986A (en) * | 2015-12-09 | 2016-05-04 | 南通富士通微电子股份有限公司 | COF (Chip on Flex) packaging method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070202680A1 (en) * | 2006-02-28 | 2007-08-30 | Aminuddin Ismail | Semiconductor packaging method |
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2020
- 2020-12-31 CN CN202011617859.9A patent/CN112614787B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7446419B1 (en) * | 2004-11-10 | 2008-11-04 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar of stacked metal balls |
| CN101809737A (en) * | 2007-08-16 | 2010-08-18 | 美光科技公司 | stacked microelectronic devices and methods for manufaturing staked microelectronic devices |
| CN105551986A (en) * | 2015-12-09 | 2016-05-04 | 南通富士通微电子股份有限公司 | COF (Chip on Flex) packaging method |
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| CN112614787A (en) | 2021-04-06 |
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