CN101162713A - Packaging structure and conducting wire rack thereof - Google Patents

Packaging structure and conducting wire rack thereof Download PDF

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Publication number
CN101162713A
CN101162713A CNA200610136000XA CN200610136000A CN101162713A CN 101162713 A CN101162713 A CN 101162713A CN A200610136000X A CNA200610136000X A CN A200610136000XA CN 200610136000 A CN200610136000 A CN 200610136000A CN 101162713 A CN101162713 A CN 101162713A
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CN
China
Prior art keywords
lead frame
bonding area
viscose
area territory
crystal bonding
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Granted
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CNA200610136000XA
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Chinese (zh)
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CN100552933C (en
Inventor
张本杰
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication of CN101162713A publication Critical patent/CN101162713A/en
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Publication of CN100552933C publication Critical patent/CN100552933C/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention provides a package structure and a wire holder of the same. The package structure comprises a wire holder, a chip and viscose, wherein, the wire holder is provided with a first surface and a corresponding second surface, the first surface is provided with a sticky crystal area, the wire holder comprises a plurality of holes and grooves, the holes go through the first and the second surfaces and encircles the sticky crystal area, the grooves are arranged on the first surface and are connected with adjacent holes to form an annular grain which encircles the sticky crystal area, the chip is arranged in the sticky crystal area, and viscose is arranged between the chip and the wire holder and is diffused in the annular grain.

Description

Encapsulating structure and lead frame thereof
[technical field]
The invention relates to a kind of encapsulating structure, and particularly relevant for a kind of encapsulating structure and lead frame thereof that prevents the viscose diffusion.
[background technology]
Semiconductor packaging is to utilize sealing to cover semiconductor chip (Chip), to avoid chip to make moist or to collide.Chip is by projection (Bump), lead frame (Lead Frame) or bonding wire structures such as (Wire), and the micromodule and the circuit of inside is electrically connected to the external world.When various electronic product was constantly weeded out the old and bring forth the new, the chip demand more is multiple grew up, and made semiconductor packaging in industrial technology development today, played the part of an epochmaking role.
Please refer to Fig. 1, Fig. 1 is a kind of end view of conventional package structure.Traditional encapsulating structure 100 comprises lead frame (Lead Frame) 110, chip 120, elargol 130 and sealing 140.Lead frame 110 has first surface 110a and opposing second surface 110b.The first surface 110a of lead frame 110 has crystal bonding area territory 110c.Chip 120 is arranged at crystal bonding area territory 110c.Elargol 130 is arranged between chip 120 and the lead frame 110.Sealing 140 covers chip 120, to avoid chip 120 to make moist or to collide.
Please refer to Fig. 2, it is the vertical view of lead frame, chip and the elargol of Fig. 1.Lead frame 110 comprises several through holes 111.Through hole 111 runs through first surface 110a and second surface 110b, and around crystal bonding area territory 110c.Wherein, the sealing 140 of Fig. 1 is more passed through through hole 111 from first surface 110a, and flow to the second surface 110b of lead frame 110, and it helps reinforced structure.
Yet elargol 130 is sticky shape liquid.In manufacture process, elargol 130 toward diffusion all around, sticks in the brilliant scope 110c and be difficult to maintain easily.Especially when chip 120 was arranged on the elargol 130, the range of scatter of elargol 130 was difficult to control more, as shown in Figures 1 and 2.
As mentioned above, how to strengthen the target that the structural strength of encapsulating structure 100 is made great efforts for a long time for industry.Above-mentioned through hole 111 is a kind of design of reinforced structure.Yet elargol 130 is spread in the phenomenon of lead frame 110, has a strong impact on the structural strength of encapsulating structure 100.As shown in Figure 1, in the zone of elargol 130 diffusions, sealing 140 can't cover well with lead frame 110.After making that sealing 140 is solidified, the inside of encapsulating structure 100 forms hole or crack, the structural strength of heavy damage encapsulating structure 100.Therefore how to overcome above-mentioned insoluble problem, in fact one of important directions of making great efforts for present industry.
[summary of the invention]
The object of the present invention is to provide a kind of encapsulating structure and lead frame thereof, make encapsulating structure have the effect that effective control viscose spreads, significantly reduces manufacturing cost and improves the structural strength of encapsulating structure.
According to purpose of the present invention, the present invention proposes a kind of encapsulating structure.This encapsulating structure comprises lead frame, chip and viscose.Lead frame has first surface and opposing second surface.First surface has the crystal bonding area territory.Lead frame comprises several through holes and several grooves.Through hole runs through first surface and second surface, and around the crystal bonding area territory.Groove is arranged at first surface.Groove connects adjacent through hole, and forms an annular lines, and annular lines is around the crystal bonding area territory.Chip is arranged at the crystal bonding area territory.Viscose is arranged between chip and the lead frame, and viscose is spread in the annular lines.
According to purpose of the present invention, the present invention proposes a kind of lead frame.This lead frame has first surface and opposing second surface.First surface has the crystal bonding area territory.Lead frame is in order to carries chips.Chip is bonding on the crystal bonding area territory with viscose.Lead frame comprises several through holes and several grooves.Through hole runs through first surface and second surface, and around the crystal bonding area territory.Groove is arranged at first surface.Groove connects adjacent through hole, and forms an annular lines.The annular lines is around the crystal bonding area territory.Wherein, viscose is spread in the annular lines.
Compared with prior art, encapsulating structure of the present invention and lead frame thereof can effectively be controlled the structural strength that viscose spreads, significantly reduces manufacturing cost and improves encapsulating structure.
[description of drawings]
Fig. 1 is a kind of end view of conventional package structure.
Fig. 2 is the vertical view of lead frame, chip and elargol shown in Figure 1.
Fig. 3 is the schematic diagram according to the encapsulating structure of preferred embodiment of the present invention.
Fig. 4 is the vertical view of lead frame, chip and the viscose of Fig. 3.
Fig. 5 A to 5E is the manufacturing flow chart of the encapsulating structure of present embodiment.
[embodiment]
Please be simultaneously with reference to Fig. 3 and Fig. 4, Fig. 3 is the schematic diagram according to the encapsulating structure of preferred embodiment of the present invention.Fig. 4 is the vertical view of lead frame, chip and the viscose of Fig. 3.As shown in Figure 3, encapsulating structure 200 comprises lead frame (Lead Frame) 210, chip 220 and viscose 230 at least.Lead frame 210 has first surface 210a and opposing second surface 210b.The first surface 210a of lead frame 210 has crystal bonding area territory 210c.Chip 220 is arranged at crystal bonding area territory 210c.Viscose 230 is arranged between chip 220 and the lead frame 210.
As shown in Figure 4, lead frame 210 comprises several through holes 211 and several grooves 212.Through hole 211 runs through first surface 210a and second surface 201b, and around crystal bonding area territory 210c.Groove 212 is arranged at first surface 210a.Groove 212 connects adjacent through hole 211, and forms an annular lines, and annular lines is around crystal bonding area territory 210c.Wherein, viscose 230 is spread in the annular lines.
For the manufacture process of understanding encapsulating structure 200 more and the diffusion process of viscose 230, below in conjunction with accompanying drawing and describe the manufacturing process of the encapsulating structure 200 of present embodiment in detail.
Please refer to Fig. 5 A to 5E, it shows the manufacturing flow chart of the encapsulating structure of present embodiment.At first, shown in Fig. 5 A, provide lead frame 210.As mentioned above, lead frame 210 comprises groove 212.Groove 212 can be formed by etching (Etching) processing procedure or laser processing procedure.But the generation type of groove 212 is not limited thereto.In addition, lead frame 210 more comprises several pins 250.Pin 250 is the periphery of radial arrangement in crystal bonding area territory 210c, as shown in Figure 4.
Then, shown in Fig. 5 B, coating viscose 230 is in the 210c of crystal bonding area territory.In the present embodiment, viscose 230 is elargol (Epoxy).
Then, shown in Fig. 5 C, chip 220 is arranged in the 210c of crystal bonding area territory.Chip 220 has active surface 220a and non-active surface 220b.Active surface 220a has several connection pads 220c.Viscose 230 is arranged between the non-active surface 220b and lead frame 210 of chip 220, in order to chip 220 is bonding in the 210c of crystal bonding area territory.
Wherein, shown in Fig. 4 and Fig. 5 C.Because groove 212 and through hole 211 be around crystal bonding area territory 210c, and form annular lines.Make viscose 230 by crystal bonding area territory 210c when the outdiffusion, only terminate in annular lines.Therefore, in the manufacture process of encapsulating structure 200, the diffusion phenomena of viscose 230 can obtain to improve significantly.
Preferably, for minimizing viscose 230 diffusible zones (zone in the annular lines), annular lines is approximate with crystal bonding area territory 210c in fact, is all quadrangle.Make the phenomenon of viscose 230 diffusions can obtain best the improvement.
Then, shown in Fig. 5 D, engage (wire bonding) connection pad 220c and pin 250 with bonding wire 260 routings.
Then, shown in Fig. 5 E, cover chip 220 with encapsulating material 240.Wherein, encapsulating material 240 covers first surface 210a, second surface 210b, through hole 211, groove 212 and the part pin 250 of lead frame 210.The pin 250 that exposes is in order to electrically connect with the external world.Then, with encapsulating material 240 curing moldings, and the pin 250 that will expose is bent into L type or J type.So far, promptly finish encapsulating structure 200.
According to above embodiment, though viscose of the present invention is to be that example explains with the elargol, right viscose of the present invention also can be the liquid state colloid of various bonding chip and substrate.So long as utilize groove design of the present invention, and form a ring-type lines, to reach the purpose that prevents the viscose diffusion, neither disengaging technical scope of the present invention.
Disclosed encapsulating structure of the above embodiment of the present invention and lead frame thereof, it utilizes groove to connect the design of adjacent through hole, makes encapsulating structure have the following advantages:
The first, effectively control the viscose diffusion: for a long time, in the manufacture process of encapsulating structure, the problem of viscose diffusion is perplexing the semiconductor packages industry always.The present invention utilizes groove and through hole to form the ring-type lines, makes the range of scatter of viscose only terminate in the interior zone of ring-type lines, controls the viscose diffusion phenomena effectively.
The second, significantly reduce manufacturing cost: in the manufacture process of traditional encapsulating structure, can't replace under the situation of liquid viscose with solid-state viscose, the viscose diffusion phenomena influence the fraction defective of production widely.Moreover the defective products of viscose diffusion can't heavy industry (Rework), needs directly to scrap processing.Therefore, use lead frame of the present invention, can significantly produce fraction defective with falling, more reduce manufacturing cost simultaneously.
Three, improve the structural strength of encapsulating structure: in encapsulating structure of the present invention, encapsulating material can cover well with lead frame.Make that encapsulating structure inside can not form hole or crack after the encapsulation material solidifies, effectively improve the structural strength of encapsulating structure.

Claims (10)

1. encapsulating structure, it comprises lead frame, chip and viscose, this lead frame has first surface and opposing second surface, this first surface has the crystal bonding area territory, this lead frame comprises several through holes, these through holes run through this first surface and this second surface, and around this crystal bonding area territory; Aforementioned chip is arranged at this crystal bonding area territory; Aforementioned viscose is arranged between this chip and this lead frame; It is characterized in that: this lead frame also comprises some grooves, and it is arranged at aforementioned first surface, and those grooves connect adjacent through hole, and form an annular lines, and this annular lines is around this crystal bonding area territory, and this viscose is spread in this annular lines.
2. encapsulating structure as claimed in claim 1 is characterized in that: this lead frame also comprises some radial arrangement in the overseas lead pin that encloses of this crystal bonding area, and aforementioned annular lines comes down to perpendicular to those lead pins.
3. encapsulating structure as claimed in claim 1 is characterized in that: this crystal bonding area territory is a quadrangle, and this annular lines is essentially quadrangle.
4. encapsulating structure as claimed in claim 1 is characterized in that: aforementioned this viscose is an elargol, and aforementioned grooves is formed with etch process or with the laser processing procedure.
5. as claim 1 a described encapsulating structure, it is characterized in that: this encapsulating structure more comprises the encapsulating material that covers this chip.
6. lead frame, this lead frame has first surface and opposing second surface, this first surface has the crystal bonding area territory, this lead frame is in order to carries chips, this chip is bonding on this crystal bonding area territory with viscose, this lead frame comprises several through holes, and those through holes run through this first surface and this second surface, and around this crystal bonding area territory; It is characterized in that: this lead frame also comprises some grooves, and it is arranged at this first surface, and those grooves connect those adjacent through holes, and form an annular lines, and this annular lines is around this crystal bonding area territory; Aforementioned viscose is spread in this annular lines.
7. lead frame as claimed in claim 6 is characterized in that: it also comprises some the lead pins of radial arrangement in the periphery in this crystal bonding area territory, and this annular lines is in fact perpendicular to those lead pins.
8. lead frame as claimed in claim 6 is characterized in that: this crystal bonding area territory is a quadrangle, and this annular lines is essentially quadrangle.
9. lead frame as claimed in claim 6 is characterized in that: aforementioned this viscose is an elargol, and those grooves are formed with etch process or with the laser processing procedure.
10. lead frame as claimed in claim 6 is characterized in that: this chip is covered by encapsulating material.
CNB200610136000XA 2006-10-12 2006-10-12 Encapsulating structure and lead frame thereof Active CN100552933C (en)

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CN101162713A true CN101162713A (en) 2008-04-16
CN100552933C CN100552933C (en) 2009-10-21

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105904099A (en) * 2016-05-09 2016-08-31 环维电子(上海)有限公司 SIP module manufacturing method and elargol groove cutting method and system
CN110170599A (en) * 2019-05-13 2019-08-27 珠海市捷锐科技有限公司 Small-sized Reed pipe forming machine

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105904099A (en) * 2016-05-09 2016-08-31 环维电子(上海)有限公司 SIP module manufacturing method and elargol groove cutting method and system
CN110170599A (en) * 2019-05-13 2019-08-27 珠海市捷锐科技有限公司 Small-sized Reed pipe forming machine
CN110170599B (en) * 2019-05-13 2024-01-05 珠海市捷锐科技有限公司 Small reed pipe forming machine

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