CN1126029C - Method and appts. for access complex vector located in DSP memory - Google Patents
Method and appts. for access complex vector located in DSP memory Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/35—Indirect addressing
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- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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Abstract
A method and apparatus for efficiently accessing the real parts and the imaginary parts of complex vector components in a digital signal processor memory is implemented through the incorporation of a new processor addressing, the fixed displacement mode. An additional register, the fixed displacement register, and an additional control flag, the fixed displacement configuration bit are needed. The method of employment requires only a single address register, and does not require use of the normal offset register used for indexed addressing, leaving the offset register to be used for simultaneous post modification and/or bit reversal. Dual memory spaces sharing a common address space are not required, thereby simplifying memory management, and the method and apparatus are compatible with all addressing.
Description
Technical field
The present invention relates to the method that processor storage addressing and memory address produce, particularly be stored in the complex vector located access method in the digital signal processor storer.
Background technology
In US 4 809 156, described one and be used for the circuit that computer system produces memory address.Address produces logic and comprises two multiplexers (Multiplexer) and a totalizer, this totalizer be used for the memory address register of output storage address and link to each other to central processing unit.The interchangeable input of a multiplexer is to come from shift register (Displacement Register) and extended register.Switching between two registers is to be controlled by sign bit, and this sign bit is produced by comparer (Comparator), and the input value of comparer exists totalizer and base address register.Comparer produces a symbol detection output signal, and there is the value of the symbol in the flag register in its reflection.This symbol decision is selected shift register or is selected the input of extended register as totalizer.
Fig. 1 illustrates the address-generation unit (AGU) 102 of the processor (for example digital signal processor) of typical prior art.Term " processor " refers to any data processing device in this article, digital signal processor for example, but be not limited thereto.AGU102 comprises the registers group that is used for the memory data visit usually.Typical registers group, each comprises three registers:
1, an address register (pointer) 104 is represented with Rn;
2, an offset register 106 is represented with Nn; With
3, a buffer length register 108 is represented with Mn.
Wherein n=1...k is the subscript of group, and K is the group number that exists in the processor address generation unit.
Any diversity of its position in the storer of processor represented in this article in term " array (Array) ", is to want an index with respect to the fixed base address so that visit its each position, and wherein index is the integral multiple of a routine.Term " vector (Vector) " representative in this article is stored in any diversity of the data value in such array, and any data value of such vector represented in this article in term " component (Component) ", and any paired data value represented in this article in term " plural number (Complex number) ".This data value is expressed as " first (First part) " and " second portion (Second part) " in this article; Be included in the logarithm of being formed by " real part " and " imaginary part " on the common mathematical meaning, but be not limited thereto.Any paired vector of the component of equal number represented in this article in term " complex vector located (Complex vector) ".Any storage array in processor represented in this article in term " first array (First array) ", and it comprises first's (perhaps vector) of a complex vector located vectorial centering.And any storage array in processor represented in this article in term " second array (Second array) ", and it comprises the second portion (perhaps vector) of a complex vector located vectorial centering.Complex vector located can a composition by the vector of the plural number on common mathematical meaning; Its complex vector located real number exists in first array, and complex vector located imaginary number exists in second array.Another kind of selection can be arranged, complex vector located can a composition by the vector of the plural number on the common mathematical meaning; Its complex vector located real number exists in second array, and complex vector located imaginary number exists in first array.Further change is that complex vector located can be made up of two vectors of any a plurality of data values according to the present invention, they do not need to represent the plural number under common mathematical meaning.In addition, represent in the storer in this article about the term in the processor storage " access (Access) " and " visit (Accessing) " and existing the numerical value in the storer to take out.
When being operated in when complex vector located, first array and second array normally are placed on the different addresses in the storer, and perhaps at different storage spaces, this is decided according to the memory architecture of processor.For visit with the indirect addressing mode one complex vector located, need two different address registers; An address register is used for first array, and another is used for second array.A restriction of this method is that address register is expensive resources very in digital signal processor.When first array and second array are in same storer, can carry out access with single address register and an offset register.This method can be used, if address register itself points to first array, and offset register comprises the skew between first array and second array.In the case, can visit first array, and visit second array with the index indirect addressing mode of address register and its offset register (Rn+Nn just) with the indirect addressing of address register (Rn).Yet anti-(bit-reversal) on the throne and revise in (post-modification-by-step) addressing mode offset register by the step back and use can not be used for the index indirect addressing mode.Therefore, when using the index indirect addressing mode, for two address registers of the complex vector located needs of access.This situation appears in the algorithm of quick Fourier transformation (FFT), has used the anti-addressing mode in position there; Appear in the simplification of sophisticated signal, used there by the step back and revised addressing mode, or the like.(summary in this field and the description of already present digital signal processor architecture can be found in " digital signal processor buyer guide ", and this book is published by Berkeley designing technique company (Berkeley Design TechnologyInc.) 1995.
Most of existing digital signals are repaired device and are not solved the problem of this memory access; Therefore, complex vector located for visiting one, when offset register in use, need two different address registers.An already present solution is shown among Fig. 2, it be used for the DSP56 of Motorola * * * series processors.This method is used two data storeies: X one storer 202 and Y one storer 204, they have identical address space 206.It also requires the assembly language grammer (not being shown among Fig. 2) and an address-generation unit (as being shown among Fig. 1) of a special use.The complete description of this architecture sees in the DSP56000 24 bit digital signal processor family handbooks, is published by Motorola Inc. (semiconductor products sector, DSP branch, Texas, Austin); It is comprising the reference material that this paper will set forth.In this prior art solutions, the architecture of address-generation unit is such: address register 208 (R0) points to two identical address, and these two is X-storer 202 and Y-storer.Therefore, being positioned at different storage spaces still can conduct interviews with address register 208 (R0) separately simultaneously at the first complex vector located array and second array of same position.As being shown in Fig. 2, address register points to address OX0002, but it and address space do not have concrete relation.Pointing to the specific memory space is done by the assembly language operational code.For example, 202, the second arrays are positioned at Y-storer 204 if first array is positioned at the X-storer; And first array stores complex vector located real part, and second array stores complex vector located imaginary part; So the real part of address OX0002 is sent to register A and imaginary part is sent to register B, can carry out with following assembler code:
move?X(R0)，A；
move?Y(R0)，B；
This solution has two problems: at first, two parts (pointing to first array and second array respectively) of vector must be positioned at the same position of different memory.This can cause the application efficiency of storer not high (space is arranged in storer), makes it be difficult to finish relocating of when needing storer simultaneously.For example, if desired first array at X-storer 202 is relocated, so also need second array at the Y-storer is relocated, to keep the two in same address.
Recognized widely and what be of great benefit to is that a kind of visit complex vector located effective ways in processor storage are arranged that it only requires the individual address register, do not require and use offset register and do not require that a plurality of storeies share same address space.The present invention satisfies this purpose.
Summary of the invention
The invention provides a kind of processor, include: an address-generation unit, it is used for calculating visit and is stored in the complex vector located real part of storer of described processor and the memory address of imaginary part, said complex vector located be have identical data value number vectorial right, said processing has the index indirect addressing ability, and make the fixed displacement mode effective, this fixed displacement mode has the state of selecting from the group of enabled state and non-enabled state, wherein said address-generation unit includes: an address register; At least one programmable fixed displacement register; A control register contains that to indicate the fixed displacement mode be in enabled state or at the fixed displacement configuration zone bit of enabled state not; A buffer length register; With an offset register, it is different from said fixed displacement register.With instruction with non-index indirect addressing mode, the real part of visit complex data value, with instruction with index indirect addressing mode, the imaginary part of visit complex data value.
The invention provides a kind of method of carrying out the fixed displacement mode in processor, this processor has: address register, at least one fixed displacement register able to programme, control register, a buffer length register and an offset register that is different from said fixed displacement register that contains the fixed displacement configuration zone bit of the state of pointing out the fixed displacement mode.This processor has the instruction that can use the index indirect addressing mode, this method includes the following step: deposit (a) that a base address enters address register and a fixed displacement enters the fixed displacement register, (b) check the current ordcurrent order that is used for the index indirect addressing mode, (c) check fixed displacement configuration zone bit, if (d) current ordcurrent order is used the index indirect address mode, and the fixed displacement configuration bit is set up, and produces a memory address that equals said base address and said fixed displacement sum.
The invention provides a kind of method by the complex vector located complex data value of processor access, the complex data value has the real part that has the base address and by the imaginary part of a fixed displacement value of base address offset, wherein the instruction of carrying out by processor can be from the group that index indirect addressing mode and non-index indirect addressing mode are formed the selective addressing mode, this method includes the following step: a) deposit the base address and enter address register; B) deposit the fixed displacement amount at least one fixed displacement register; C) select the enabled state of fixed displacement mode, the enabled state of wherein said selection fixed displacement mode comprises the following steps: i) fixed displacement configuration zone bit is set; Ii) use the index indirect addressing mode; D) with instruction with non-index indirect addressing mode, the real part of visit complex data value; E) with instruction with index indirect addressing mode, the imaginary part of visit complex data value.
Like this, the present invention has successfully solved the present known configuration and the shortcoming of method.At first, the present invention is complex vector located with visiting under the registers group of an address-generation unit which kind of addressing mode in office.Secondly, the present invention does not propose any restriction to the real part of complex vector located (for example its first array and second array) and the storage allocation of imaginary part, storage space and address is not proposed any restriction yet.
Description of drawings
In this article, the present invention is illustrated with reference to the accompanying drawings with way of example, and they are:
Fig. 1 illustrates the address-generation unit of the digital signal processor of a prior art.
Fig. 2 illustrates the stored configuration of the digital signal processing of prior art.
Fig. 3 illustrates the new characteristic according to address-generation unit in the digital signal processor of the present invention.
Fig. 4 is the process flow diagram that a fixing displacement address produces algorithm.
Fig. 5 illustrates an example of memory state.
Fig. 6 illustrates the architecture of two data storage spaces.
Embodiment
Principle and operation according to a method and apparatus of the present invention, can explain with accompanying drawing and corresponding explanation, the pith of unit address generation unit of the present invention is shown among Fig. 3, the step of method of the present invention illustrates that in the process flow diagram of Fig. 4 they are carried out in digital signal processor or other treatment in accordance with the present invention devices.These steps realize the fixed displacement mode, and it is a kind of new processor mode according to the present invention.
As illustrated, at first need the additional hardware capabilities that provides certain at Fig. 3.Particularly, this processor must have a fixed displacement register 310 in address-generation unit 302, represent with Rf1.The fixed displacement register should be a software programmable, as every other register in address-generation unit 302.Also possible, but optional, use fixed displacement register more than one, wherein Fu Jia a plurality of fixed displacement registers 312,314 and 316 are used Rf2, Rf3......Rfn respectively
nRepresent, the with dashed lines frame table shows in the drawings.Omission mark ... point out that more additional fastening shift register can add.Registers group 322 comprises Rn, Nn, Mn and Rf1.The present invention requires processor that the ability of index indirect addressing mode is arranged, and it can be realized by any known method in this field.Should notice that fixed displacement register 310 is different with offset register 306.Fixed displacement register 310 is finished different functions with offset register 306, and they are to be used independently of each other.
In addition, this processor needs a new mode, is referred to herein as " fixed displacement mode ".This fixed displacement mode has two states: one is enabled state, and one is non-enabled state; They can be controlled by the fixed displacement configuration bit 320 that joins control register 318.The fixed displacement configuration bit plays a part controlled flag in this method.Below the operation in the method for the invention of fixed displacement mode is specified in.Control register 318 can be a control register that has existed through revising in the design of the processor that has existed, and also can be a new control register.And the processor that is provided needs realizes the fixedly hardware of displacement mode implementation step (face as follows).Realize that these hardware facilities to carry out following step, can use multiple well-known technology in this area.
The step of method that the realization fixed displacement mode of being carried out by processor according to the present invention produces memory address is as follows, and is shown among Fig. 4.
1, the registers group in depositing step 402 322 is deposited into address-generation unit 302 (Fig. 3).This step is deposited the base address and is entered address register 304, and address offset enters offset register 306, and buffer length enters buffer length register 308 and the fixed displacement amount enters fixed displacement register 310.
2, check at decision-point 404 whether current ordcurrent order uses the index indirect addressing mode.
If 3 do not use the index indirect addressing mode, just produce step 408 in the address and produce the address with usual way, the method is well-known in this area.
If 4 index indirect addressing modes are used, check at decision-point 406 whether fixed displacement configuration bit 302 (Fig. 3) are set.
If 5 fixed displacement configuration bits 320 are not provided with, the fixed displacement mode is in the disable state, and address-generation unit 302 operates in memory address by usual way and produces step 410.At this moment, new characteristic described herein is moved, and reference address is formed by Rn+Nn, and it does not change the value of Rn register 304 (Fig. 3).When fixed displacement configuration bit 302 was eliminated, offset register Nn 306 (Fig. 3) was all back modifications and the source of indirect indexed addressing mode.
If 6 fixed displacement configuration bits are set, like this, the fixed displacement mode is in enabled state; The offset source that the memory address of all index indirect addressing modes produces is fixed displacement register 310 (Rfn), rather than offset register 306 (Nn); This process produces in the step 412 in the address carries out.The address that is produced is the content of fixed displacement register 310 and the content sum of address register.Reference address Rn+Rfn does not change the value of Rn register 304 (Fig. 3).
According to the present invention, the memory address production method is returning step 414 end.
Fixedly the shift configuration position is as a controlled flag, and when it was set, making fixedly, displacement mode was in enabled state; When it was removed, making fixedly, displacement mode was in the disable state.In any case fixedly displacement mode is effective in current ordcurrent order use index indirect address mode only.If the addressing mode that current ordcurrent order is used is not the index indirect addressing mode, fixedly displacement mode even it are neither be effective under enabled state.As well-known in this area, exist other addressing modes that are different from the index indirect addressing mode, include but not limited to directly address and back modification addressing mode.In an instruction, might comprise any of these addressing mode.Term " non-index indirect addressing (Non-indexing indirect addressing) " in this article refers to other any addressing modes that do not comprise the index indirect addressing mode.
Should be noted that assembly language can, whether support fixed displacement register 310 (Rf1) in the order but must produce in memory address.Term " assembly language " refers to the two in this article: assembler syntax support and the configuration that produces machine instruction.If the fixed displacement register supported in assembly language, to activate fixed displacement be to do that a single instruction limits rather than as having the processor mode of enabled state and disable state to assembler syntax so.Do not support that at assembly language it is enough that defined order only has offset register 306 (Nn) under the situation of fixing shift register.Because this has stipulated addressing mode.Hardware automatically uses offset register 306 or fixed displacement register 310 to be used for the generation of memory address according to the state of fixed displacement configuration bit 320.Be noted that also specifying different storage arrays is arbitrarily for " first array " or " second array ", and their content also is arbitrarily fully.
Obviously, the method according to this invention allows processor to visit two complex vector located parts effectively.For example, suppose that the state of address-generation unit and storer is as follows:
R1=1000 (address register 304 among Fig. 3)
N1=2 (offset register 306 among Fig. 3)
M1=is programmed to linear addressing mode (programming of buffer length register 308-reality is by manufacturing plant's decision among Fig. 3)
Rf1=50 (fixed displacement register 310 among Fig. 3)
Assembler code (pseudo-code) below carrying out:
Mov(R1)+N1，A；
MOV(R1+N1)，B；
Wherein A and B are the general-purpose registers (not being the register of address-generation unit 302) of processor, note, (R1)+and N1 is that addressing mode is revised in the back, the meaning is that memory access is to position R1, and R1 is after memory access, by increment N1.Notice that also (R1+N1) be the index indirect addressing mode, the meaning is that the visit of storer is to position R1+N1, during memory access or to keep R1 later on constant.
Situation when Fig. 5 illustrates two different values of fixing shift configuration position 320 has address 504 for storage area 502.In Fig. 5 and following Example, all data values and address location decimally represent, under two kinds of situations, below described maintenance:
Storage area 1000 forward to 1049, is designated as first array 518 from the address, and storage area is designated as second array 520 from the address 1050 forward.
Before carrying out, address register has individual initial value 506, equals 1000.Meaning is the memory location 512 that the initial value sensing of R1 equals 1000, and 1000 content is-348.
After first instruction is finished, value-348 is arranged among the register A, and R1 sensing address 1002 is deposited in the address, meaning is that R1 points to position 514 in the storer, it is 1002 that there is an address position 514, includes data value 4391.
After finishing execution, the final value of address register R1 is 510, and it equals 1002.This is because second instruction only comprises indexed addressing mode, and indexed addressing mode is the value that can not change an address register.
After carrying out the second instruction, the content-dependent of register B is in the fixed displacement mode.Below to the setting of fixing displacement mode with remove two kinds of situations and be described.
Fixedly the shift configuration position is not provided with:
In this case, fixedly the shift configuration position is (not being provided with) of removing.Therefore, fixedly displacement mode is in the disable state.The generation of memory address is according to usual way, and after second instruction carried out, register B had numerical value 4391, and it is from the memory location 514 of first array 518.
Fixedly the shift configuration position is provided with:
In this case, fixedly the shift configuration position is provided with.Therefore, the fixed displacement mode is to be in enabled state.Because the index indirect addressing mode is not used in first instruction, so be according to common mode to the generation of first instruction storage address.And the index indirect addressing mode is used in the second instruction, because fixedly the shift configuration position is (therefore, the fixed displacement mode is in the enabled state) that is provided with, the skew that memory address produces is gone to search by Rf1 again, and accessed content is-819 memory address 516.Therefore, in this situation, after second instruction carried out, the content of register B was-819, and it is the memory location 516 from second array 520.
So this is complex vector located real part and the imaginary part of accessing effectively.For example, if real part exists in second array 520, and imaginary part exists in first array 518; Initially set the fixed displacement configuration bit then, after carrying out above-mentioned two instructions, register A has one imaginary part in complex vector located all parts, and register B has a real part in complex vector located all parts.
In above-mentioned example, represented method is in a kind of simple memory architecture according to the present invention, i.e. the structure of single storage space.Today, advanced DSP algorithm requires that fairly perfect memory architecture is arranged, so the modern digital signal processor has two storage space structures.Fig. 6 provides an example, and it is complex vector located that it is that the method according to this invention is used for, and there is different storage spaces in its first array with second array.Address 606 is corresponding to data value content 608.In Fig. 6 and following example, all address location hexadecimal representations.
For method of the present invention being used for two storage space architectures, the arrangement of storer must be an order, and a storage space 602 is arranged here, with " X memory address space " expression, is used for first array 610, and its start address is OX0000; Simultaneously, a storage space 604 is arranged, with " Y memory address space " expression, be used for second array 612, its start address is OX8000.As requested, these addresses be shown in Fig. 6 be the order.Notice the most significant digit of its address (MSB) identifies use which storage space in this example.
In this configuration, the base address of complex vector located real part can be placed in the X space 602, and for example, among the OX0002 of address, and the base address of complex vector located imaginary part can be placed on the Y space, for example, and in the OX8008 address.In order to be operated under the fixed displacement mode, need to be arranged to OX8006 (OX8008-OX0002) to fixed displacement bit register Rf, and the fixed displacement configuration bit 320 in the control register 318 (Fig. 3) is set.
Though that the present invention has described is limited embodiment, will be realized many variations of the present invention, modification and other application.
Claims (3)
1, a kind of processor includes:
An address-generation unit (302), it is used for calculating visit and is stored in the complex vector located real part of storer of described processor and the memory address of imaginary part; It is characterized in that: said complex vector located be have identical data value number vectorial right;
Said processing has the index indirect addressing ability, and makes the fixed displacement mode effective, and this fixed displacement mode has the state of selecting from the group of enabled state and non-enabled state;
Wherein said address-generation unit (302) includes:
An address register (304),
At least one programmable fixed displacement register (310,312,314,316),
A control register (318) contains that to indicate the fixed displacement mode be in enabled state or at the fixed displacement configuration zone bit (320) of enabled state not,
A buffer length register; With
An offset register (306), it is different from said fixed displacement register (310,312,314,316);
With instruction with non-index indirect addressing mode, the real part of visit complex data value;
With instruction with index indirect addressing mode, the imaginary part of visit complex data value.
2, in processor, carry out the method for fixed displacement mode, this processor has an address register (304), at least one fixed displacement register able to programme (310,312,314,316), control register (318), a buffer length register (318) and an offset register that is different from said fixed displacement register (310,312,314,316) that contains the fixed displacement configuration zone bit (320) of the state of pointing out the fixed displacement mode; It is characterized in that: processor has the instruction that can use the index indirect addressing mode, and this method includes the following step:
Deposit (a) that (S402) base address enters address register (304) and a fixed displacement enters fixed displacement register (310,312,314,316),
(b) check that (S404) is used for the current ordcurrent order of index indirect addressing mode,
(c) check (S406) fixed displacement configuration zone bit (320) and
(d) indirect address mode if the current ordcurrent order use indexes, and fixed displacement configuration bit (320) is set up, and produces the memory address that (S412) equals said base address and said fixed displacement sum.
3, by the method for the complex vector located complex data value of the described processor access of claim 1, it is characterized in that: the complex data value has the real part that has the base address and by the imaginary part of a fixed displacement value of base address offset;
Wherein the instruction of carrying out by processor can be from the group that index indirect addressing mode and non-index indirect addressing mode are formed the selective addressing mode;
This method includes the following step:
A) deposit the base address and enter address register (304);
B) deposit the fixed displacement amount at least one fixed displacement register (310,312,314,316);
C) enabled state of selection fixed displacement mode, the enabled state of wherein said selection fixed displacement mode comprises the following steps:
I) fixed displacement configuration zone bit (320) is set; With
Ii) use the index indirect addressing mode;
D) with instruction with non-index indirect addressing mode, the real part of visit complex data value;
E) with instruction with index indirect addressing mode, the imaginary part of visit complex data value.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15210498A | 1998-09-14 | 1998-09-14 | |
| US09/152,104 | 1998-09-14 |
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|---|---|
| CN1318167A CN1318167A (en) | 2001-10-17 |
| CN1126029C true CN1126029C (en) | 2003-10-29 |
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| CN99810889A Expired - Fee Related CN1126029C (en) | 1998-09-14 | 1999-09-13 | Method and appts. for access complex vector located in DSP memory |
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| JP (1) | JP2002525708A (en) |
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| KR100800552B1 (en) * | 2005-06-13 | 2008-02-04 | 재단법인서울대학교산학협력재단 | Vector memory, processor including the vector memory, and data processing method therein |
| US20070198815A1 (en) * | 2005-08-11 | 2007-08-23 | Coresonic Ab | Programmable digital signal processor having a clustered SIMD microarchitecture including a complex short multiplier and an independent vector load unit |
| CN102629191B (en) * | 2011-04-25 | 2014-07-30 | 中国电子科技集团公司第三十八研究所 | Digital signal processor addressing method |
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|---|---|---|---|---|
| US4809156A (en) * | 1984-03-19 | 1989-02-28 | Trw Inc. | Address generator circuit |
| US5357618A (en) * | 1991-04-15 | 1994-10-18 | International Business Machines Corporation | Cache prefetch and bypass using stride registers |
| US5940876A (en) * | 1997-04-02 | 1999-08-17 | Advanced Micro Devices, Inc. | Stride instruction for fetching data separated by a stride amount |
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1999
- 1999-09-13 EP EP99947331A patent/EP1114367A1/en not_active Withdrawn
- 1999-09-13 JP JP2000570665A patent/JP2002525708A/en not_active Ceased
- 1999-09-13 WO PCT/EP1999/006764 patent/WO2000016194A1/en not_active Application Discontinuation
- 1999-09-13 KR KR1020017003242A patent/KR20010075083A/en not_active Application Discontinuation
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| CN1318167A (en) | 2001-10-17 |
| EP1114367A1 (en) | 2001-07-11 |
| KR20010075083A (en) | 2001-08-09 |
| JP2002525708A (en) | 2002-08-13 |
| WO2000016194A1 (en) | 2000-03-23 |
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