CN112601388A - Inner core board anti-stacking PCB and monitoring method - Google Patents
Inner core board anti-stacking PCB and monitoring method Download PDFInfo
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- CN112601388A CN112601388A CN202011227506.8A CN202011227506A CN112601388A CN 112601388 A CN112601388 A CN 112601388A CN 202011227506 A CN202011227506 A CN 202011227506A CN 112601388 A CN112601388 A CN 112601388A
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- core
- identification
- strip
- identification strip
- plates
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- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000012544 monitoring process Methods 0.000 title claims abstract description 14
- 238000003475 lamination Methods 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 230000002950 deficient Effects 0.000 abstract description 7
- 238000007689 inspection Methods 0.000 abstract description 5
- 238000013461 design Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
A PCB with an inner core plate for preventing from being folded in a wrong way and a monitoring method thereof are disclosed, wherein the PCB comprises a plurality of layers of core plates, the upper end and the lower end of each core plate are respectively provided with a marking strip, the marking strips at the upper end of each core plate are arranged in parallel with the side surfaces of the core plates, and the marking strip at the upper end of each core plate is positioned at the left side of the marking strip at the lower end; or in each core plate, the identification strip at the upper end of the core plate is positioned at the right side of the identification strip at the lower end; in any adjacent upper and lower layers of the core boards, the identification strip of the upper layer core board is positioned on the left side of the identification strip of the lower layer core board; or in any adjacent upper and lower layers of the core plates, the identification strip of the upper layer core plate is positioned at the right side of the identification strip of the lower layer core plate, and whether the core plates of the inner layers are overlapped or not is checked by checking the positions of the identification strips at the upper and lower ends of the core plates and the positions of the identification strips of the adjacent upper and lower layers of the core plates. Compared with the prior art, the inner core board has the advantages of simple structural design, high inspection speed and good effect, and can effectively prevent defective products from flowing into a client.
Description
Technical Field
The invention relates to the technical field of PCB manufacturing, in particular to a PCB with an inner core plate capable of preventing wrong lamination and a monitoring method.
Background
A Printed Circuit Board (PCB) is an important electronic component, is a support for an electronic component, and is a provider of electrical connection of the electronic component. At present, the multilayer board PCB with more than or equal to 6 layers has more than 2 core boards in the inner layer. And in the lamination process, the core plates are laminated according to the layer number sequence of the core plates, and then lamination is carried out. During production line operation, due to carelessness of staff, core plates are often mistakenly or reversely stacked, but once the defective products are pressed, the defective products are difficult to distinguish from the appearance, the defective products cannot be selected through electrical measurement, and the manufactured defective products easily flow to a client side to cause quality accidents.
Therefore, there is a need to provide a new PCB with inner core boards being resistant to wrong stacking and a monitoring method thereof to solve the above-mentioned technical problems.
Disclosure of Invention
The invention aims to solve the technical problem of providing the inner core board anti-stacking PCB and the monitoring method which have the advantages of simple structure, high inspection speed and good effect.
The technical scheme adopted by the invention for solving the technical problem is that the inner core board anti-stacking PCB comprises a plurality of layers of core boards, wherein the upper end and the lower end of each core board are respectively provided with a mark strip; or in each core plate, the identification strip at the upper end of the core plate is positioned at the right side of the identification strip at the lower end; in any adjacent upper and lower layers of the core boards, the identification strip of the upper layer core board is positioned on the left side of the identification strip of the lower layer core board; or in any two adjacent upper and lower layers of the core boards, the identification strip of the upper layer core board is positioned on the right side of the identification strip of the lower layer core board.
Preferably, all the identification strips are distributed along the side surface of the core plate in a diagonal line.
Preferably, the identification strip is a copper strip.
The invention also provides a monitoring method of the PCB with the inner core board capable of preventing the wrong lamination, which comprises the following steps:
checking the identification strips on the side surfaces of the core boards, and if in each core board, the identification strip on the upper end of the core board is positioned on the left side of the identification strip on the lower end; or in each core plate, the identification strip at the upper end of the core plate is positioned at the right side of the identification strip at the lower end; the core plates are not overlapped; otherwise, the core plate is reversely stacked;
checking any adjacent upper and lower layers of the core boards, if the identification strip of the upper layer of the core board is positioned on the left side of the identification strip of the lower layer of the core board; or the identification strip of the upper core plate is positioned on the right side of the identification strip of the lower core plate; the core plates are sequentially overlapped, otherwise, the core plates are sequentially overlapped;
in the two steps, the core plates are not overlapped and the core plates are sequentially overlapped, the core plates of the inner layer are overlapped, otherwise, the core plates of the inner layer are overlapped in a wrong way.
Preferably, when the inner core plates are stacked, the identification strips on the side surfaces of the core plates are distributed in a diagonal line.
Preferably, the identification strip is a copper strip.
Compared with the prior art, the core plates are provided with the identification strips at two ends, the core plates are overlapped and then checked whether to be overlapped or not by checking whether the identification strip at the upper end of each core plate is positioned at the right side or the left side of the identification strip at the lower end, and then the core plates are checked whether to be overlapped in sequence or not by checking whether the identification strip of each lower core plate is positioned at the left side or the right side of the identification strip of the upper core plate, only when the core plates are not overlapped and the core plates are overlapped in sequence, the inner core plates are overlapped, otherwise, the inner core plates are overlapped in a wrong way. The core board has the advantages of simple structural design, high inspection speed and good effect, and can effectively prevent defective products from flowing into the client.
Drawings
FIG. 1 is a schematic structural diagram of a logo strip on a core board according to the present invention;
FIG. 2 is a schematic structural diagram of a fourth embodiment of the present invention;
FIG. 3 is a schematic structural diagram according to a second embodiment of the present invention;
FIG. 4 is a schematic structural diagram according to a first embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a third embodiment of the present invention;
FIG. 6 is a schematic view of the core plates of the present invention stacked in an offset order;
fig. 7 is a schematic view of the core plate of the present invention in an inverted configuration.
In the figure:
1. core board, 2. identification strip.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Example one
Referring to fig. 1, the PCB with the inner core board for preventing the inner core board from being stacked in the embodiment includes a plurality of core boards 1, in the embodiment, the PCB is 8 layers, the number of the inner core boards 1 is 3, the upper end surface and the lower end surface of each core board 1 are respectively provided with a marking strip 2, each marking strip 2 is arranged at the edge of each core board 1, one end of each marking strip 2 is flush with the side surface of each core board 1, and referring to fig. 4, each core board 1 is provided with a marking strip 2 at the upper end of each core board 1, and the marking strip 2 at the lower end of each core board 1 is; in any adjacent upper and lower layers of core plates 1, the identification strip 2 of the upper layer of core plate 1 is positioned on the left side of the identification strip 2 of the lower layer of core plate 1;
all the identification strips 2 are distributed along the side surface of the core plate 1 in a diagonal line. The identification strip 2 is arranged to be an oblique line, so that the core plate is visual and clear when being checked, whether the core plate 1 is folded in a wrong way or not is favorably distinguished, and the checking efficiency is favorably improved.
The identification strip 2 is a copper strip.
The invention also provides a monitoring method of the PCB with the inner core board capable of preventing the wrong lamination, which comprises the following steps:
checking the identification strips 2 on the side surfaces of the core plates 1, if the identification strip 2 at the upper end of the core plate 1 is positioned at the left side of the identification strip 2 at the lower end in each core plate 1, the core plates 1 are not stacked, otherwise, the core plates 1 are stacked;
checking any adjacent upper and lower layers of core boards 1, if the identification strips 2 of the upper layer of core boards 1 are positioned at the left sides of the identification strips 2 of the lower layer of core boards 1, sequentially overlapping the core boards 1, otherwise, sequentially and incorrectly overlapping the core boards 1;
in the two steps, when the core boards 1 are not overlapped and the core boards 1 are sequentially overlapped, the core boards 1 in the inner layer are overlapped, otherwise, the core boards 1 in the inner layer are overlapped in a wrong way.
When the inner core boards 1 are stacked, the identification strips 2 on the side surfaces of the core boards 1 are distributed in a diagonal line. The oblique line is visual and clear, whether the core plates 1 are overlapped can be rapidly checked, and the checking efficiency is favorably improved.
The identification strip 2 is a copper strip.
Example two
This embodiment is substantially the same as the first embodiment, except that:
referring to fig. 3, in each core board 1, the identification strip 2 at the upper end of the core board 1 is positioned at the left side of the identification strip 2 at the lower end; in any adjacent upper and lower layers of core boards 1, the identification strip 2 of the upper layer of core board 1 is positioned at the right side of the identification strip 2 of the lower layer of core board 1.
In the monitoring method of the PCB with the inner core plates for preventing the wrong lamination, the identification strips 2 on the side surfaces of the core plates 1 are checked, if the identification strip 2 at the upper end of the core plate 1 is positioned on the left side of the identification strip 2 at the lower end in each core plate 1, the core plates 1 are not laminated, otherwise, the core plates 1 are laminated;
checking any adjacent upper and lower layers of core boards 1, if the identification strips 2 of the upper layer of core boards 1 are positioned at the right sides of the identification strips 2 of the lower layer of core boards 1, sequentially overlapping the core boards 1, otherwise, sequentially and incorrectly overlapping the core boards 1;
in the two steps, when the core boards 1 are not overlapped and the core boards 1 are sequentially overlapped, the core boards 1 in the inner layer are overlapped, otherwise, the core boards 1 in the inner layer are overlapped in a wrong way.
EXAMPLE III
This embodiment is substantially the same as the first embodiment, except that:
referring to fig. 5, in each core board 1, the identification strip 2 at the upper end of the core board 1 is positioned at the right side of the identification strip 2 at the lower end; in any adjacent upper and lower layers of core boards 1, the identification strip 2 of the upper layer of core board 1 is positioned on the left side of the identification strip 2 of the lower layer of core board 1.
In the monitoring method of the PCB with the inner core plates for preventing the wrong lamination, the identification strips 2 on the side surfaces of the core plates 1 are checked, if the identification strip 2 at the upper end of the core plate 1 is positioned at the right side of the identification strip 2 at the lower end in each core plate 1, the core plates 1 are not laminated, otherwise, the core plates 1 are laminated;
checking any adjacent upper and lower layers of core boards 1, if the identification strips 2 of the upper layer of core boards 1 are positioned at the left sides of the identification strips 2 of the lower layer of core boards 1, sequentially overlapping the core boards 1, otherwise, sequentially and incorrectly overlapping the core boards 1;
in the two steps, when the core boards 1 are not overlapped and the core boards 1 are sequentially overlapped, the core boards 1 in the inner layer are overlapped, otherwise, the core boards 1 in the inner layer are overlapped in a wrong way.
Example four
This embodiment is substantially the same as the first embodiment, except that:
referring to fig. 2, in each core board 1, the identification strip 2 at the upper end of the core board 1 is positioned at the right side of the identification strip 2 at the lower end; in any adjacent upper and lower layers of core boards 1, the identification strip 2 of the upper layer of core board 1 is positioned at the right side of the identification strip 2 of the lower layer of core board 1.
In the monitoring method of the PCB with the inner core board for preventing the wrong lamination, the identification strips 2 on the side surfaces of the core boards 1 are checked, if the identification strip 2 at the upper end of each core board 1 is positioned at the right side of the identification strip 2 at the lower end of the core board 1 in each core board 1, the core boards 1 are not laminated, otherwise, the core boards 1 are laminated, and refer to the attached figure 7;
checking any adjacent upper and lower layers of core boards 1, if the identification strips 2 of the upper layer of core boards 1 are positioned at the right sides of the identification strips 2 of the lower layer of core boards 1, sequentially overlapping the core boards 1, otherwise, sequentially and wrongly overlapping the core boards 1, and referring to the attached figure 6;
in the two steps, when the core boards 1 are not overlapped and the core boards 1 are sequentially overlapped, the core boards 1 in the inner layer are overlapped, otherwise, the core boards 1 in the inner layer are overlapped in a wrong way.
In the invention, the identification strips 2 are arranged at the two ends of the core plate 1, after the core plates 1 are overlapped, whether the core plates 1 are overlapped or not is checked by checking whether the identification strip 2 at the upper end of each core plate 1 is positioned at the right side or the left side of the identification strip 2 at the lower end, then whether the core plates 1 are overlapped or not in sequence is checked by checking whether the identification strip 2 of each lower core plate 1 is positioned at the left side or the right side of the identification strip 2 of the upper core plate 1, only when the core plates 1 are not overlapped and the core plates 1 are overlapped in sequence, the inner core plates 1 are overlapped, otherwise, the inner core plates 1 are overlapped. This inner core board 1 structural design is simple, and the inspection is fast, and can effectively inspect out whether inner core board 1 is folded up, and the inspection is effectual, can effectively avoid the defective products to flow in the customer end.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (6)
1. The PCB with the inner core plates capable of preventing the wrong lamination is characterized by comprising a plurality of layers of core plates, wherein the upper end and the lower end of each core plate are respectively provided with a mark strip; or in each core plate, the identification strip at the upper end of the core plate is positioned at the right side of the identification strip at the lower end; in any adjacent upper and lower layers of the core boards, the identification strip of the upper layer core board is positioned on the left side of the identification strip of the lower layer core board; or in any two adjacent upper and lower layers of the core boards, the identification strip of the upper layer core board is positioned on the right side of the identification strip of the lower layer core board.
2. The PCB of claim 1, wherein all of the identification strips are arranged in a diagonal line along the side of the core.
3. The inner core anti-stacking PCB of claim 2, wherein the identification strip is a copper strip.
4. A method for monitoring a PCB having an inner core board for preventing a lamination error as claimed in any one of claims 1 to 3, comprising the steps of:
checking the identification strips on the side surfaces of the core boards, and if in each core board, the identification strip on the upper end of the core board is positioned on the left side of the identification strip on the lower end; or in each core plate, the identification strip at the upper end of the core plate is positioned at the right side of the identification strip at the lower end; the core plates are not overlapped; otherwise, the core plate is reversely stacked;
checking any adjacent upper and lower layers of the core boards, if the identification strip of the upper layer of the core board is positioned on the left side of the identification strip of the lower layer of the core board; or the identification strip of the upper core plate is positioned on the right side of the identification strip of the lower core plate; the core plates are sequentially overlapped, otherwise, the core plates are sequentially overlapped;
in the two steps, the core plates are not overlapped and the core plates are sequentially overlapped, the core plates of the inner layer are overlapped, otherwise, the core plates of the inner layer are overlapped in a wrong way.
5. The method for monitoring the PCB of the inner core board with the anti-stacking function of claim 4, wherein when the inner core boards are stacked, the identification strips on the side surfaces of the core boards are distributed in a diagonal line.
6. The method for monitoring the PCB of the inner core board with the anti-stacking function of claim 5, wherein the identification strip is a copper strip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011227506.8A CN112601388A (en) | 2020-11-05 | 2020-11-05 | Inner core board anti-stacking PCB and monitoring method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011227506.8A CN112601388A (en) | 2020-11-05 | 2020-11-05 | Inner core board anti-stacking PCB and monitoring method |
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| Publication Number | Publication Date |
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| CN112601388A true CN112601388A (en) | 2021-04-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202011227506.8A Pending CN112601388A (en) | 2020-11-05 | 2020-11-05 | Inner core board anti-stacking PCB and monitoring method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116234151A (en) * | 2022-12-21 | 2023-06-06 | 镁佳(武汉)科技有限公司 | Printed circuit board |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5266380A (en) * | 1992-09-08 | 1993-11-30 | Motorola, Inc. | Method and apparatus for visual verification of proper assembly and alignment of layers in a multi-layer printed circuit board |
| JPH10163631A (en) * | 1996-11-30 | 1998-06-19 | Samsung Electro Mech Co Ltd | Multi-layer printed circuit board and its manufacturing method |
| CN204217205U (en) * | 2014-11-14 | 2015-03-18 | 广州兴森快捷电路科技有限公司 | Printed circuit board and the anti-antistructure of lamination thereof |
| CN109600941A (en) * | 2019-01-28 | 2019-04-09 | 鹤山市世安电子科技有限公司 | A kind of PCB multilayer circuit board interlayer change in size measurement method |
-
2020
- 2020-11-05 CN CN202011227506.8A patent/CN112601388A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5266380A (en) * | 1992-09-08 | 1993-11-30 | Motorola, Inc. | Method and apparatus for visual verification of proper assembly and alignment of layers in a multi-layer printed circuit board |
| JPH10163631A (en) * | 1996-11-30 | 1998-06-19 | Samsung Electro Mech Co Ltd | Multi-layer printed circuit board and its manufacturing method |
| CN204217205U (en) * | 2014-11-14 | 2015-03-18 | 广州兴森快捷电路科技有限公司 | Printed circuit board and the anti-antistructure of lamination thereof |
| CN109600941A (en) * | 2019-01-28 | 2019-04-09 | 鹤山市世安电子科技有限公司 | A kind of PCB multilayer circuit board interlayer change in size measurement method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116234151A (en) * | 2022-12-21 | 2023-06-06 | 镁佳(武汉)科技有限公司 | Printed circuit board |
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Application publication date: 20210402 |