CN112600566A - Digital circuit for decoding run length - Google Patents
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Abstract
The invention provides a run length decoding digital circuit, which comprises a state machine unit, wherein the state machine unit switches an operation state according to classification information of compressed data, and the run length decoding digital circuit determines the reading time of the next compressed data according to the operation state. The configuration is adopted, decoding is carried out in a hardware mode, and real-time performance is achieved; meanwhile, by reasonably setting the running state and the state conversion logic of the state machine unit, the coupling relation between the decoding process of the run-length coded data and the waiting process required for smoothly splicing the decoded data is decoupled, the design difficulty of the run-length decoding circuit is reduced, the interruption and delay of the picture stream data output by the common hardware decoding circuit are avoided, and the requirement of an OSD function on the picture stream data to be superposed is met.
Description
Technical Field
The invention relates to the field of digital circuit design, in particular to a run length decoding digital circuit.
Background
Run-length encoding is a common compression algorithm, and the basic idea is to describe repeated and multiple continuous characters in a { continuous occurrence number, a certain character } format, and in the run-length encoding process, two kinds of data are included, one is original data (which may also be called data to be compressed or encoded), and the other is compressed data (which may also be called encoded data). In this specification, picture stream data, decoded data, uncoded data, data in a general format, and the like all refer to original data; run-length coded format data, compressed data, and the like, all refer to compressed data; the process of obtaining compressed data from the original data is called run-length coding; the process of deriving the original data from the compressed data is called run-length decoding. The invention provides a run length decoding digital circuit, which is a circuit for decoding compressed data into original picture stream data.
The run-length coding and decoding is a solution for loading overlay graphs or characters for realizing OSD (picture-in-picture) function, and the realization of the OSD function comprises the following five steps: 1. acquiring overlay data in a run-length coding format; 2. obtaining data of a graph to be folded in a common format; 3. decoding the overlay data in the run-length coding format to obtain decoded overlay data; 4. overlaying the overlay data in the common format on the data to be overlaid in the common format to obtain combined picture stream data; 5. and outputting the combined picture stream data.
In the prior art, the above process is implemented by an MCU (micro controller Unit or Microcontroller). The specific implementation is that the overlay coding information and the data of the overlay to be stored in the external memory or the internal buffer memory are accessed by the MCU ( i.e. steps 1 and 2 above), then the overlay coding information is decoded by software, and the decoded overlay data and the data of the overlay are combined, so as to complete the OSD overlay function (i.e. steps 3 and 4 above) and then write the overlay result back to the data memory (i.e. step 5 above).
Decoding by MCU has the following problems: because the reading, decoding and superimposing processes of the data are completely finished based on the MCU, the reading coding and decoding speed is limited by the performance of the MCU, and the condition that the OSD superimposition frame rate is low may exist on the MCU with lower performance. FIG. 1 is a schematic diagram of MCU decoding resulting in overlay error. Fig. 1 shows that a plurality of error data appear in the picture stream data in YUV format which is finally generated by picture stream data output by a common decoding circuit, which affects the final picture folding effect.
In summary, in the prior art, a circuit for implementing an OSD function by software has a high requirement on MCU performance, and is prone to have problems of low frame rate, inability to output picture stream data in real time, and delay, breakpoint or error when outputting picture stream data in real time.
Disclosure of Invention
The invention aims to provide a run-length decoding digital circuit, which aims to solve the problems that in the prior art, a circuit for realizing an OSD function in a software mode has high requirements on MCU performance, is easy to have low frame rate, cannot output picture stream data in real time and is easy to have delay, break points or errors when the picture stream data is output in real time.
In order to solve the above technical problem, the present invention provides a run length decoding digital circuit, which includes a state machine unit, wherein the state machine unit switches an operation state according to classification information of compressed data, and the run length decoding digital circuit determines a reading time of next compressed data based on the operation state; the compressed data is picture stream data in a run-length compression format.
Optionally, the run-length decoding digital circuit includes a decoding unit, where the decoding unit is configured to obtain the classification information of the compressed data, and send the classification information to the state machine unit; the decoding unit is further configured to decode the compressed data.
Optionally, the classification information includes a compression type of the compressed data, a length of the compressed data itself, and a length of the decoded data.
Optionally, the running state includes a preparation state and a working state, the working state includes a core state, and when the compression type of the compressed data is uncompressed, the length of the compressed data is 1 byte, and the length of the decoded data is 1 byte, the running state is switched to the core state.
Optionally, after the current decoding process of the compressed data is finished, if it is determined that the run-length decoding digital circuit needs to continue to operate, the state machine unit switches the operating state to the core state.
Optionally, the working states further include a first state group, and the first state group includes at least one of the working states; and when the compression type of the compressed data is uncompressed and the length of the compressed data is at least 2 bytes, the running state is switched to one or more working states in the first state group according to first state switching logic.
Optionally, the first state switching logic includes that, when the length of the compressed data is 2 bytes and the length of the decoded data is 2 bytes, the operating state is switched to one of the working states in the first state group; and when the length of the compressed data is 2 bytes and the length of the decoded data is 3 bytes, switching the running state to one working state in the first state group.
Optionally, the first state switching logic includes that, when the length of the compressed data is at least 3 bytes and the length of the decoded data is an odd number of bytes in 4 to 1023 bytes, the running state is switched to one of the working states in the first state group; and when the length of the compressed data is at least 3 bytes and the length of the decoded data is an even number of bytes in 4-1023, switching the running state to one working state in the first state group.
Optionally, the working states further include a second state group, where the second state group includes at least one of the working states; and when the compression type of the compressed data is compression, the operating state is switched to one or more working states in the second state group according to second state switching logic.
Optionally, the second state switching logic includes switching the operating state to one of the operating states in the second state group when the length of the compressed data is 2 bytes and the length of the decoded data is between 3 to 1023 bytes.
Optionally, the second state switching logic includes switching the operating state to one of the operating states in the second state group when the length of the compressed data is 3 bytes and the length of the decoded data is between 1024 ^26-1 bytes.
Optionally, the preparation state includes a waiting state and an open state; when the state machine unit does not start working, the running state is switched to the waiting state; when the running state is a waiting state, the state machine unit receives an end signal of a previous frame and receives an enable signal, and the running state is switched to the starting state; and when the running state is the starting state, waiting for a preset number of clock cycles, and switching the running state to the core state.
Optionally, the run-length decoding digital circuit includes at least one of the following elements or units: a memory for storing the compressed data to be decoded, the compressed data utilized by the state machine unit being read from the memory; the reading control unit is used for reading the compressed data according to the running state and sending the compressed data to a subsequent circuit; and a picture stream data memory for buffering the decoded picture stream data and outputting the decoded picture stream data to an external circuit.
Compared with the prior art, the run length decoding digital circuit provided by the invention comprises a state machine unit, wherein the state machine unit switches the operation state according to the classification information of the compressed data, and the run length decoding digital circuit determines the reading time of the next compressed data according to the operation state. Decoding is carried out in a hardware mode, real-time performance is achieved, the decoding speed is completely consistent with an input clock, the image folding operation can be completed under the condition that the frame rate of the output image stream is ensured, and the problems that a circuit which realizes an OSD function in a software mode has high requirements on MCU performance, the frame rate is low, the image stream data cannot be output in real time, and delay, breakpoints or errors are prone to occur when the image stream data is output in real time are solved.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention. Wherein:
FIG. 1 is a diagram illustrating an error in overlay due to an OSD function implemented by an MCU;
FIG. 2 is a schematic diagram of a digital circuit for run-length decoding according to an embodiment of the present invention;
FIG. 3 is a data type diagram of a portion of compressed data according to an embodiment of the invention;
FIG. 4 is a diagram illustrating the operation states and state transition logic of a state machine unit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of correct overlay data obtained by the OSD circuit according to an embodiment of the present invention.
In the drawings:
1-a state machine unit; 2-a decoding unit; 3-a memory; 4-a read control unit; 5-picture stream data storage.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, features defined as "first", "second", "third" may explicitly or implicitly include one or at least two of such features, the term "proximal" is typically the end near the operator, the term "distal" is typically the end near the patient, "end" with "another end" and "proximal" with "distal" are typically the corresponding two parts, which include not only end points, the terms "mounted", "connected" and "connected" are to be understood broadly, e.g., they may be fixedly connected, detachably connected, or integrated; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. Furthermore, as used in the present invention, the disposition of an element with another element generally only means that there is a connection, coupling, fit or driving relationship between the two elements, and the connection, coupling, fit or driving relationship between the two elements may be direct or indirect through intermediate elements, and cannot be understood as indicating or implying any spatial positional relationship between the two elements, i.e., an element may be in any orientation inside, outside, above, below or to one side of another element, unless the content clearly indicates otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The core idea of the invention is to provide a run decoding digital circuit to solve the problems that in the prior art, a circuit for realizing an OSD function in a software mode has high requirements on MCU performance, is easy to have low frame rate, cannot output picture stream data in real time, and is easy to have delay, break points or errors when outputting the picture stream data in real time.
In the background section, the drawbacks of implementing OSD functions by an MCU have been analyzed in detail. Further, the inventor found that, because the run-length encoded data includes a plurality of data types, and the lengths of the run-length encoded data of different data types are different, the delays to be waited before and after reading, during decoding, and after decoding of the run-length encoded data of different data types are different, and the run-length encoded data of different data types cannot be processed by a simple logic, otherwise, errors or losses of data during decoding are easily caused, and erroneous data or breakpoints occur in finally spliced picture stream data. Therefore, the common hardware decoding circuit has difficulty in splicing the picture stream data after decoding the run-length coded data of different continuous data types. In order to realize the OSD function, a decoding circuit is needed to output the picture stream to be superimposed, and the picture stream output by the decoding circuit and the input data of the picture stream of the other path need to be strictly superimposed according to the requirements of user configuration, size of the superimposed area, and the like, so that signal interruption and delay of the picture stream data cannot occur in the middle. The hardware decoding circuit with simple arrangement cannot meet the above requirements. Thus, the inventors further conceived that the above-described difficulty can be solved by the run length decoding digital circuit in the present embodiment.
The following description refers to the accompanying drawings.
Referring to fig. 2 to 5, fig. 2 is a schematic structural diagram of a run-length decoding digital circuit according to an embodiment of the present invention; FIG. 3 is a data type diagram of a portion of compressed data according to an embodiment of the invention; FIG. 4 is a diagram illustrating the operation states and state transition logic of a state machine unit according to an embodiment of the present invention; fig. 5 is a schematic diagram of correct overlay data obtained by the OSD circuit according to an embodiment of the present invention.
As shown in fig. 2, this embodiment provides a run-length decoding digital circuit, where the run-length decoding digital circuit includes a state machine unit 1, the state machine unit 1 switches an operation state according to classification information of compressed data, and the run-length decoding digital circuit determines a reading timing of next compressed data according to the operation state; the compressed data is picture stream data in a run-length compression format.
According to the configuration, on one hand, decoding is carried out in a hardware mode, real-time performance is achieved, the decoding speed is completely consistent with that of an input clock, the image folding operation can be completed under the condition that the frame rate of an output image stream is ensured, and the problems that a circuit for realizing an OSD function in a software mode has high requirements on MCU performance, the frame rate is low, image stream data cannot be output in real time, and delay, breakpoints or errors are prone to occur when the image stream data is output in real time are solved. On the other hand, by reasonably setting the running state and the state conversion logic of the state machine unit 1, the run-length decoding digital circuit can respectively play its own roles in terms of decoding related units and reading related units of the compressed data to be decoded, and the final decoded data can be ensured to be correctly spliced without mutual cooperation. That is to say, the state machine unit 1 is configured to decouple the coupling relationship between the decoding process of the run-length encoded data and the delay time setting of the read-band decoded data, reduce the design difficulty of the run-length decoding circuit, and solve the problem that the common hardware decoding circuit is difficult to adapt to the run-length encoded data of different data types in the decoding process, so that the spliced picture stream data has errors, delays or breakpoints, and the requirement for the picture stream data to be superimposed in the OSD function cannot be met.
With continued reference to fig. 2, in an exemplary embodiment, the run-length decoding digital circuit includes a decoding unit 2, a memory 3, a read control unit 4, and a picture stream data memory 5.
The decoding unit 2 is configured to obtain the classification information of the compressed data, and send the classification information to the state machine unit 1; the decoding unit 2 is also used to decode the compressed data. The function of acquiring the classification information is arranged in the decoding unit 2, so that decoding circuits in the decoding unit can be multiplexed better, and the scale and the size of the whole circuit are reduced.
The memory 3 is used to store the compressed data to be decoded, and the compressed data utilized by the state machine unit 1 is read from the memory 3. So configured, the decoding unit 2 can obtain the compressed data more conveniently. Preferably, the Memory 3 is a Static Random-Access Memory (sram). In other embodiments, other forms of Memory, such as a ROM (Read-Only Memory), may be selected as long as the compressed data can be continuously Read.
The reading control unit 4 is configured to read the compressed data according to the operating state and send the compressed data to a subsequent circuit. The single reading control unit 4 is used for controlling the time of reading data, so that the division of labor among modules of the circuit is more definite, and the design difficulty of the circuit is also reduced.
The picture stream data memory 5 is configured to buffer the decoded picture stream data and output the decoded picture stream data to an external circuit. The picture stream data storage 5 is arranged to further buffer data, so as to further ensure the accuracy of the output overlay information. The picture stream data storage 5 may also process data in a first-in first-out manner, and may suspend buffering data when the available storage space is less than or equal to a preset ratio, and when the picture stream data storage 5 suspends buffering data, other parts of the run-length decoding digital circuit may also change the current operating state accordingly, and the specific change rule and logic may be configured according to common knowledge in the art, and will not be described in detail herein, and the preset ratio may be 1/4, 1/2 or other suitable ratios.
It is to be understood that in other embodiments, the memory 3, the read control unit 4, and the picture stream data memory 5 can be selectively configured, and such a scheme can still accommodate run-length encoded data of different data types, but the scheme of configuring the above elements or units at the same time is a preferred scheme.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating data types of a portion of compressed data according to an embodiment of the invention. As can be seen from fig. 3, the data types of the compressed data are various, and therefore, a detailed classification rule needs to be set to classify the compressed data so as to better perform the subsequent state transition.
Preferably, the classification information includes a compression type of the compressed data, a length of the compressed data itself, and a length of the decoded data. The compression type of the compressed data determines the data decoding speed, the length of the compressed data determines the data reading time, the length of the decoded data determines the data output time, and the three determine the time which is required from the beginning of reading a new piece of the compressed data to the end of outputting the decoded data (hereinafter, the time is replaced by the decoding time length, but please note the slight difference between the decoding time length and the time). And the following problem analysis can be performed according to the time: to output decoded data of a second piece of the compressed data that can be just next to the decoded data of the first piece of the compressed data, how many clock cycles the read time of the second piece of the compressed data should be from the read time of the first piece of the compressed data? The result of the above problem can be obtained through calculation or experiments in advance, and the run length decoding digital circuit is guided to work by the calculation result, so that the problem of difficult splicing among data in the prior art is solved. Therefore, the three indexes are selected as the classification information of the compressed data, so that the decoding time lengths of the final data in the same classification are close or equal, and the subsequent logic planning is facilitated. It should be noted that, according to the existing run-length coding standard, the compressed data must include a 2-bit flag bit and a plurality of bit length indicating bits, and the above-mentioned indexes can be obtained by the flag bit and the length indicating bits of the compressed data. But for ease of understanding, and to accommodate possible future modifications of the run-length coding standard, the remainder of the description is described in detail in the context of the three indicators described above, without reference to the notion of flag bits and length indicator bits.
According to the classification information, various classifications can be designed and corresponding operation states can be designed, and the following description introduces specific details of the operation states in a manner of alternately explaining a design idea in combination with an embodiment, which refers to fig. 4.
Firstly, the running state comprises a preparation state and a working state, and the configuration is beneficial to the state machine unit 1 to better switch between a standby state and a working state, wherein the preparation state comprises a waiting state and an opening state; when the state machine unit 1 does not start working, the running state is switched to the waiting state; when the running state is a waiting state, the state machine unit 1 receives an end signal of a previous frame and receives an enable signal, and the running state is switched to the open state; and when the running state is the starting state, waiting for three clock cycles, and switching the running state to the core state. The physical inputs of the end signal and the enable signal, and the corresponding processing logic, may be arranged according to common general knowledge in the art and will not be described in detail here. The corresponding states in this embodiment are also named as a waiting state and an open state, and please refer to fig. 4 for understanding. It should be understood that, in this embodiment, the transition between the on state and the core state needs to wait for three clock cycles, and in other embodiments, the transition may be set to wait for a preset number of clock cycles according to actual needs and operating parameters of other modules of the circuit, where the preset number may be any natural number.
Secondly, when the compression type of the compressed data is uncompressed, the length of the compressed data is 1 byte, and the length of the decoded data is 1 byte (hereinafter referred to as a first classification condition), the decoding time length of the data is short, and if the connection relationship with the previous data and the connection relationship with the next data are not processed within the decoding time length, the final output data is likely to have errors, so that the data meeting the first classification condition needs to be particularly processed in an important manner, and therefore, the working state needs to be designed to include a core state, and when the compressed data meets the first classification condition, the operating state is switched to the core state. In this embodiment, PT1 corresponds to the core state.
In order to further solve the problem that errors are easily caused in the processing of data meeting the first classification condition, after the current decoding process of the compressed data is finished, if it is determined that the run-length decoding digital circuit needs to continue to work, the state machine unit 1 switches the operating state to the core state. The above design concept can be regarded as a logic in a "pre-judging" form, although at this time, the state machine unit does not know which classification the next piece of compressed data belongs to specifically, and pre-judging it as a better strategy is the classification condition. If the next piece of compressed data does meet the first classification condition, the run-length decoding digital circuit can immediately start working, and if the next piece of compressed data does not meet the first classification condition, switching is performed again, and although the switching consumes a certain clock period, the consumption does not influence the final result because the decoding duration of other classified compressed data is longer. Referring to fig. 4, in fig. 4, the states PT2, PT3, CPT1, CPT2, PTEVEN and PTODD all have arrows pointing to PT1, that is, the above working states are all switched to PT1 after the completion. It should be understood that the operating state is switched to the core state only when the state machine unit 1 determines that the run-length decoding digital circuit needs to continue to operate, and otherwise, the operating state may be switched to the standby state. The specific condition for switching to the standby state may be set according to actual requirements, for example, a signal at the enable end disappears or other transition conditions, and this logic is not a matter of emphasis in this specification and will not be expanded herein. It should be understood that in some other embodiments, the state transition path for switching to the standby state may not be provided for some of the operating states.
The inventors performed systematic analyses for the remaining possible data types. The method is exhaustive by a classification idea, and the exhaustive result is shown in table 1.
TABLE 1 results of classification of data types
It should be understood that the classification in table 1 is an exhaustive list of possible classifications, and not just one such classification concept. The classification conditions in table 1 are divided into nine categories according to space relationships, and the purpose is to illustrate the classification concept. In fact, some conditions can be further subdivided according to the same idea, for example, the classification condition six can be further specifically subdivided into two sub-classes, namely an odd number in 1024 ^ 2^26-1 and an odd number ≧ 2^26, and the sub-class of the odd number ≧ 2^26 can be further subdivided, so as to avoid the redundant verbuttle, no further development is performed here.
For discussion on the basis of the classification conditions shown in table 1, (other classification methods should be understood in the same way), first, in the classification conditions listed in table 1, the compressed data of adjacent conditions often have similar logic but are different in processing; secondly, the number of the operating states is considered, too few of the operating states cannot exert the advantages of the state machine, and too many of the operating states increase the design and manufacturing costs. Based on the comprehensive consideration of the two design ideas, the following design ideas are obtained:
the operating states further comprise a first state set comprising at least one of the operating states; and when the compression type of the compressed data is uncompressed and the length of the compressed data is at least 2 bytes, the running state is switched to one or more working states in the first state group according to first state switching logic. For example, one of the operating states may be set for all cases that satisfy the second to seventh classification conditions, one of the operating states may be set for each case that satisfies the second to seventh classification conditions, or one of the operating states may be set for cases that satisfies the second to third classification conditions, while another of the operating states may be set for cases that satisfies the fourth to seventh classification conditions.
The operating states further comprise a second state set comprising at least one of the operating states; and when the compression type of the compressed data is compression, the operating state is switched to one or more working states in the second state group according to second state switching logic. The specific arrangement concept of the second state set can be understood by referring to the description of the first state set in the specification.
Preferably, the first state switching logic includes that, when the length of the compressed data is 2 bytes and the length of the decoded data is 2 bytes, the operating state is switched to one of the operating states in the first state group; when the length of the compressed data is 2 bytes and the length of the decoded data is 3 bytes, switching the running state to one working state in the first state group; when the length of the compressed data is at least 3 bytes and the length of the decoded data is an odd number of bytes in 4-1023, switching the running state to one working state in the first state group; and when the length of the compressed data is at least 3 bytes and the length of the decoded data is an even number of bytes in 4-1023, switching the running state to one working state in the first state group.
The second state switching logic comprises that when the length of the compressed data is 2 bytes and the length of the decoded data is between 3 and 1023 bytes, the operation state is switched to one working state in the second state group; and when the length of the compressed data is 3 bytes and the length of the decoded data is between 1024 and (2^26-1) bytes, switching the running state to one working state in the second state group.
It should be understood that, in the above design concept, the concept of "one of the operating states" should be understood that "one of the operating states" corresponding to different classification conditions in the same state group may actually be the same operating state, may also be different operating states, or some of the operating states may be the same operating state and other operating states may be other operating states. The specific arrangement scheme can be balanced according to actual needs and the design and manufacturing cost of the circuit.
For the classification situation not mentioned in the above design idea, one other working state may be separately designed for the remaining situation according to actual needs (for the same state group, the working states of different state groups are not proposed to be combined), or the remaining situation may be classified into one existing working state or subdivided, and a plurality of different working states are used to correspond to the subdivided remaining situation one to one.
In an exemplary embodiment, referring to fig. 4, when the compressed data meets the second classification condition, the operating state is switched to PT2, when the compressed data meets the third classification condition, the operating state is switched to PT3, when the compressed data meets the fourth classification condition or the sixth classification condition, the operating state is switched to PTODD, when the compressed data meets the fifth classification condition or the seventh classification condition, the operating state is switched to PTEVEN, when the compressed data meets the eighth classification condition, the operating state is switched to CPT1, and when the compressed data meets the ninth classification condition or the tenth classification condition, the operating state is switched to CPT 2.
It should be understood that, based on the detailed explanation of the above design idea in this specification and assisted by table 1 to determine the processing logic similarity degree between the classification conditions, those skilled in the art can easily split or combine the above two classification conditions to decimal classification conditions, and design corresponding working states, so as to obtain other better setting schemes for the working states of the state machine unit 1.
In addition, although a scheme such as setting an independent state for the two plus ten sorting conditions has a negative effect on the design and manufacture of the run-length decoding digital circuit, such a scheme can still solve the problem of decoding with software in the prior art, and should be regarded as a simple modification of the present embodiment.
It should be understood that, after the operating states are determined, the reading timing of the next piece of compressed data corresponding to each operating state may be configured according to specific situations, for example, after other parameters of the circuit are determined, a better reading timing is obtained according to a calculation or experimental manner, and then the reading timing is configured in the run length decoding digital circuit.
As described in the background art, the implementation of the OSD function includes five steps, and the run-length decoding digital circuit disclosed in this embodiment optimizes step 3 of the five steps, and implements the functions of step 1 and step 3.
The embodiment also provides an OSD circuit for implementing a complete OSD function, where the OSD circuit includes the above run-length decoding digital circuit and a superimposition module, and the superimposition module is configured to receive the decoded first picture stream data sent by the run-length decoding digital circuit, receive the second picture stream data, and superimpose the first picture stream data and the second picture stream data according to a superimposition logic to obtain the superimposed picture stream data. Other modules of the OSD circuit, the specific implementation manner inside the overlay module, and the connection relationship among the modules of the OSD circuit may be set by a person skilled in the art according to common knowledge, and are not specifically described here. Referring to fig. 5, in an embodiment, the video data in YUV format output by the OSD circuit is as shown in fig. 5, and thus, the OSD circuit overcomes the problem of difficulty in splicing different types of data by a common decoding circuit.
In summary, the digital circuit for run length decoding provided by the present invention includes a state machine unit 1, where the state machine unit 1 switches an operation state according to classification information of compressed data, and the digital circuit for run length decoding determines a reading timing of next compressed data according to the operation state. Decoding is carried out in a hardware mode, and real-time performance is achieved; meanwhile, the problem that the common decoding circuit is difficult to splice different types of data is solved by reasonably setting the running state and the state conversion logic of the state machine unit 1.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.
Claims (13)
1. A digital circuit of decoding of the run, characterized by that, the said digital circuit of decoding of the run includes the unit of the state machine, the said state machine unit switches over the running state according to the classification information of the compressed data, the said digital circuit of decoding of the run regards said running state as the reading opportunity of the next said compressed data of decision; the compressed data is picture stream data in a run-length compression format.
2. The run length decoding digital circuit according to claim 1, comprising a decoding unit for obtaining said classification information of said compressed data and sending said classification information to said state machine unit; the decoding unit is further configured to decode the compressed data.
3. The run length decoding digital circuit according to claim 1, wherein the classification information includes a compression type of the compressed data, a length of the compressed data itself, and a length of the decoded data.
4. The run-length decoding digital circuit according to claim 3, wherein the operating states include a ready state and an operating state, the operating state includes a core state, and the operating state is switched to the core state when the compression type of the compressed data is uncompressed, the length of the compressed data is 1 byte, and the length of the decoded data is 1 byte.
5. The run-length decoding digital circuit according to claim 4, wherein the state machine unit switches the operating state to the core state if it is determined that the run-length decoding digital circuit needs to continue to operate after the current decoding process of the compressed data is completed.
6. The run length decoding digital circuit of claim 4 wherein said operating states further comprise a first set of states, said first set of states comprising at least one of said operating states;
and when the compression type of the compressed data is uncompressed and the length of the compressed data is at least 2 bytes, the running state is switched to one or more working states in the first state group according to first state switching logic.
7. The run decoding digital circuit of claim 6 wherein the first state switching logic comprises,
when the length of the compressed data is 2 bytes and the length of the decoded data is 2 bytes, switching the running state to one working state in the first state group; and
and when the length of the compressed data is 2 bytes and the length of the decoded data is 3 bytes, switching the running state to one working state in the first state group.
8. The run decoding digital circuit of claim 7 wherein the first state switching logic comprises,
when the length of the compressed data is at least 3 bytes and the length of the decoded data is an odd number of bytes in 4-1023, switching the running state to one working state in the first state group; and
and when the length of the compressed data is at least 3 bytes and the length of the decoded data is an even number of bytes in 4-1023, switching the running state to one working state in the first state group.
9. The run length decoding digital circuit of claim 4 wherein said operating states further comprise a second set of states, said second set of states comprising at least one of said operating states;
and when the compression type of the compressed data is compression, the operating state is switched to one or more working states in the second state group according to second state switching logic.
10. The run decoding digital circuit of claim 9 wherein the second state switching logic comprises,
when the length of the compressed data is 2 bytes and the length of the decoded data is between 3 and 1023 bytes, the operation state is switched to one of the working states in the second state group.
11. The run decoding digital circuit of claim 10 wherein the second state switching logic comprises,
when the length of the compressed data is 3 bytes and the length of the decoded data is between 1024 ^26-1 bytes, the operation state is switched to one working state in the second state group.
12. The run length decoding digital circuit of claim 4 wherein the ready state comprises a wait state and an on state;
when the state machine unit does not start working, the running state is switched to the waiting state;
when the running state is a waiting state, the state machine unit receives an end signal of a previous frame and receives an enable signal, and the running state is switched to the starting state; and
and when the running state is the starting state, waiting for a preset number of clock cycles, and switching the running state to the core state.
13. A run length decoding digital circuit according to claim 1, comprising at least one of the following elements or units:
a memory for storing the compressed data to be decoded, the compressed data utilized by the state machine unit being read from the memory;
the reading control unit is used for reading the compressed data according to the running state and sending the compressed data to a subsequent circuit; and
a picture stream data memory for buffering decoded picture stream data and outputting the decoded picture stream data to an external circuit.
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