CN112600565A - Digital circuit for decoding run length - Google Patents
Digital circuit for decoding run length Download PDFInfo
- Publication number
- CN112600565A CN112600565A CN202011506128.7A CN202011506128A CN112600565A CN 112600565 A CN112600565 A CN 112600565A CN 202011506128 A CN202011506128 A CN 202011506128A CN 112600565 A CN112600565 A CN 112600565A
- Authority
- CN
- China
- Prior art keywords
- data
- picture stream
- stream data
- digital circuit
- run
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000013500 data storage Methods 0.000 claims description 17
- 238000012545 processing Methods 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000003631 expected effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/46—Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
The invention provides a run decoding digital circuit, which comprises a decoding control module and two decoders, wherein the decoding control module is used for acquiring compressed data of different data types and sending the acquired compressed data to the decoders according to a first preset logic, and the decoders are used for decoding the acquired compressed data into picture stream data in a preset format and outputting the picture stream data according to a second preset logic. The configuration is adopted, decoding is carried out in a hardware mode, and real-time performance is achieved; meanwhile, the two decoders buffer each other and have enough time to decode the received compressed data, so that interruption and delay of picture stream data output by a common hardware decoding circuit, which are easy to occur, are avoided, and the requirements of an OSD function on the picture stream data to be superimposed are met.
Description
Technical Field
The invention relates to the field of digital circuit design, in particular to a run length decoding digital circuit.
Background
Run-length encoding is a common compression algorithm, and the basic idea is to describe repeated and multiple continuous characters in a { continuous occurrence number, a certain character } format, and in the run-length encoding process, two kinds of data are included, one is original data (which may also be called data to be compressed or encoded), and the other is compressed data (which may also be called encoded data). In this specification, picture stream data, decoded data, uncoded data, data in a general format, and the like all refer to original data; run-length coded format data, compressed data, and the like, all refer to compressed data; the process of obtaining compressed data from the original data is called run-length coding; the process of deriving the original data from the compressed data is called run-length decoding. The invention provides a run length decoding digital circuit, which is a circuit for decoding compressed data into original picture stream data.
Run-length coding is a solution for loading overlay or characters to realize OSD (picture-in-picture) function, which includes the following five steps: 1. acquiring overlay data in a run-length coding format; 2. obtaining data of a graph to be folded in a common format; 3. decoding the overlay data in the run-length coding format to obtain decoded overlay data; 4. overlaying the overlay data in the common format on the data to be overlaid in the common format to obtain combined picture stream data; 5. and outputting the combined picture stream data.
In the prior art, the above process is implemented by an MCU (micro controller Unit or Microcontroller). The specific implementation is that the overlay coding information and the data of the overlay to be stored in the external memory or the internal buffer memory are accessed by the MCU ( i.e. steps 1 and 2 above), then the overlay coding information is decoded by software, and the decoded overlay data and the data of the overlay are combined, so as to complete the OSD overlay function ( i.e. steps 3 and 4 above) and then write the overlay result back to the data memory (i.e. step 5 above).
Decoding by MCU has the following problems: because the reading, decoding and superimposing processes of the data are completely finished based on the MCU, the reading coding and decoding speed is limited by the performance of the MCU, and the condition that the OSD superimposition frame rate is low may exist on the MCU with lower performance. FIG. 1 is a schematic diagram of MCU decoding resulting in overlay error. Fig. 1 shows that a plurality of error data appear in the picture stream data in YUV format which is finally generated by picture stream data output by a common decoding circuit, which affects the final picture folding effect.
In summary, in the prior art, a circuit for implementing an OSD function by software has a high requirement on MCU performance, and is prone to have problems of low frame rate, inability to output picture stream data in real time, and delay, breakpoint or error when outputting picture stream data in real time.
Disclosure of Invention
The invention aims to provide a run-length decoding digital circuit, which aims to solve the problems that in the prior art, a circuit for realizing an OSD function in a software mode has high requirements on MCU performance, is easy to have low frame rate, cannot output picture stream data in real time and is easy to have delay, break points or errors when the picture stream data is output in real time.
In order to solve the above technical problem, the present invention provides a run decoding digital circuit, which includes a decoding control module and two decoders, wherein the decoding control module is configured to obtain compressed data of different data types, and send the obtained compressed data to the decoders according to a first preset logic, and the decoders are configured to decode the obtained compressed data into picture stream data of a preset format and output the picture stream data according to a second preset logic; the compressed data is picture stream data in a run-length coding format.
Optionally, the first preset logic includes sending the compressed data to two decoders alternately, and sending the compressed data to only one decoder at a time.
Optionally, the first preset logic further includes sending only the compressed data of the same data type before switching the sending object.
Optionally, the second preset logic includes that the two decoders output the picture stream data alternately and uninterruptedly, and only one decoder outputs the data at the same time.
Optionally, the run-length decoding digital circuit further includes a storage control module and a picture stream data storage, where the storage control module is configured to directly splice the picture stream data output by the decoder according to the sequence of the receiving time, and write the combined picture stream data into the picture stream data storage.
Optionally, the data processing mode of the picture stream data storage is first-in first-out.
Optionally, the storage control module is further configured to read picture stream data stored in the picture stream data storage and output the picture stream data to an external circuit.
Optionally, when the available storage space of the picture stream data storage is smaller than or equal to a preset ratio, the storage control module suspends writing data into the picture stream data storage.
Optionally, the preset ratio is 1/2.
Optionally, the run-length decoding digital circuit further includes a memory, the memory is used for storing the compressed data to be decoded, and the decoding control module obtains the compressed data from the memory.
Compared with the prior art, the run-length decoding digital circuit provided by the invention comprises a decoding control module and two decoders, wherein the decoding control module is used for acquiring compressed data of different data types and sending the acquired compressed data to the decoders according to a first preset logic, and the decoders are used for decoding the acquired compressed data into picture stream data in a preset format and outputting the picture stream data according to a second preset logic. The configuration is adopted, decoding is carried out in a hardware mode, real-time performance is achieved, the decoding speed is completely consistent with that of an input clock, the image folding operation can be finished under the condition that the frame rate of the output image stream is ensured, and the problems that a circuit for realizing an OSD function in a software mode has high requirements on the performance of an MCU, the frame rate is low, the image stream data cannot be output in real time, and delay, breakpoints or errors are prone to occur when the image stream data is output in real time are solved.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention. Wherein:
FIG. 1 is a diagram illustrating an error in overlay due to an OSD function implemented by an MCU;
FIG. 2 is a schematic diagram of a digital circuit for run-length decoding according to an embodiment of the present invention;
FIG. 3 is a data type diagram of a portion of compressed data according to an embodiment of the invention;
fig. 4 is a schematic diagram of correct overlay data obtained by the OSD circuit according to an embodiment of the present invention.
In the drawings:
1-a decoding control module; 2-a decoder; 3-storing the control module; 4-picture stream data storage; 5-a memory; 6-memory control module.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, features defined as "first", "second", "third" may explicitly or implicitly include one or at least two of such features, the term "proximal" is typically the end near the operator, the term "distal" is typically the end near the patient, "end" with "another end" and "proximal" with "distal" are typically the corresponding two parts, which include not only end points, the terms "mounted", "connected" and "connected" are to be understood broadly, e.g., they may be fixedly connected, detachably connected, or integrated; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. Furthermore, as used in the present invention, the disposition of an element with another element generally only means that there is a connection, coupling, fit or driving relationship between the two elements, and the connection, coupling, fit or driving relationship between the two elements may be direct or indirect through intermediate elements, and cannot be understood as indicating or implying any spatial positional relationship between the two elements, i.e., an element may be in any orientation inside, outside, above, below or to one side of another element, unless the content clearly indicates otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The core idea of the invention is to provide a run decoding digital circuit to solve the problems that in the prior art, a circuit for realizing an OSD function in a software mode has high requirements on MCU performance, is easy to have low frame rate, cannot output picture stream data in real time, and is easy to have delay, break points or errors when outputting the picture stream data in real time.
In the background section, the drawbacks of implementing OSD functions by an MCU have been analyzed in detail. Further, the inventor found that since the run-length encoded data includes a plurality of data types, and the lengths of the run-length encoded data of different data types are different, it may take a plurality of digital clocks to obtain the complete and accurate pixel information included in the run-length encoded data during the decoding process. In order to realize the OSD function, a decoding circuit is needed to output the picture stream to be superimposed, and the picture stream output by the decoding circuit and the input data of the picture stream of the other path need to be strictly superimposed according to the requirements of user configuration, size of the superimposed area, and the like, so that signal interruption and delay of the picture stream data cannot occur in the middle. The hardware decoding circuit with simple arrangement cannot meet the above requirements. Thus, the inventors further conceived that the above-described difficulty can be solved by the run length decoding digital circuit in the present embodiment.
The following description refers to the accompanying drawings.
Referring to fig. 2 to 4, fig. 2 is a schematic structural diagram of a run-length decoding digital circuit according to an embodiment of the present invention; FIG. 3 is a data type diagram of a portion of compressed data according to an embodiment of the invention; fig. 4 is a schematic diagram of correct overlay data obtained by the OSD circuit according to an embodiment of the present invention.
As shown in fig. 2, this embodiment provides a run-length decoding digital circuit, where the run-length decoding digital circuit includes a decoding control module 1 and two decoders 2, where the decoding control module 1 is configured to obtain compressed data of different data types and send the obtained compressed data to the decoder 2 according to a first preset logic, and the decoder 2 is configured to decode the obtained compressed data into picture stream data in a preset format and output the picture stream data according to a second preset logic; the compressed data is picture stream data in a run-length coding format.
According to the configuration, on one hand, decoding is carried out in a hardware mode, real-time performance is achieved, the decoding speed is completely consistent with that of an input clock, the image folding operation can be completed under the condition that the frame rate of an output image stream is ensured, and the problems that a circuit for realizing an OSD function in a software mode has high requirements on MCU performance, the frame rate is low, image stream data cannot be output in real time, and delay, breakpoints or errors are prone to occur when the image stream data is output in real time are solved. On the other hand, in combination with the first preset logic and the second preset logic, the effect of the two decoders 2 working alternately can be achieved, when one of the decoders 2 does not complete the decoding task, the other decoder 2 can output the picture stream data which is already decoded as a buffer, thereby eliminating the problem of interruption and delay of the picture stream data when the decoded picture stream is output by a single decoder 2, and meeting the problem of the requirement of the OSD function for the picture stream data to be superimposed.
It should be understood that the preset format may be any data format convenient for implementing the subsequent overlay, and those skilled in the art may set the preset format according to the common general knowledge, and will not be described in detail herein.
It should be understood that the first preset logic may be any logic that enables the above-mentioned effects to be achieved, for example, the data may be sent to one of the decoders 2 first, and when the sending process is not finished, another data is sent to the other decoder 2, and from the time scale, the time proportion for sending data to both the decoders 2 at the same time is 10%, the time proportion for sending data to one of the decoders 2 alone is 80%, and the time proportion for not sending data is 10%, and the above-mentioned effects can also be achieved. Preferably, however, said first preset logic comprises sending said compressed data alternately to two of said decoders 2, sending compressed data to only one of said decoders 2 at a time. So configured, it is beneficial to design and implement the decoding control module 1. On the other hand, since the decoded picture stream data is finally subjected to the superimposition operation with the other path of picture stream data to output the final image, the run-length decoding digital circuit does not need to output the picture stream data at a higher speed (compared with the other path of picture stream data), and it is not necessary to design to transmit data to both of the decoders 2 at the same time for a part of the time. Of course, under other conditions, the expected effect can be achieved by other forms of the first preset logic.
Preferably, the first preset logic further comprises sending only the compressed data of the same data type before switching sending objects. That is, only the same type of compressed data is output each time the compressed data is transmitted continuously. Referring to fig. 3, fig. 3 is a schematic diagram illustrating data types of a portion of compressed data according to an embodiment of the invention. As can be seen from fig. 3, the data types of the compressed data are various, and the total length of the compressed data of each data type is not equal. If the time length or the data length is used as the logic for switching the transmission target, the workload of each decoder 2 is increased, and on the other hand, if the compressed data of the same data type is switched without being completely transmitted, another decoder 2 receives the subsequent data without including the data header, which is not beneficial to the realization of decoding the data.
It should be understood that the second preset logic may also be various, for example, each of the decoders 2 decodes immediately upon receiving the compressed data, and outputs the decoded picture stream data at the first time when decoding is completed, so as to achieve the above-mentioned effects. However, such a scheme brings inconvenience to subsequent circuit module processing. In a preferred embodiment, the second predetermined logic comprises two decoders 2 outputting picture stream data alternatively and uninterruptedly, and only one decoder 2 outputting data at a time. It should be understood that how each of the decoders 2 determines whether another decoder 2 has completed outputting the data of this time may be implemented by various schemes, for example, two decoders 2 communicate with each other, or a module is provided to send a message to each of the decoders 2 that the data of another decoder 2 has been sent, or other implementations. The above-described embodiments are not limited in this specification, and those skilled in the art can design and implement the embodiments according to actual needs and common general knowledge.
In an embodiment, the run-length decoding digital circuit further comprises a storage control module 3 and a picture stream data storage 4, wherein the storage control module 3 is configured to directly splice the picture stream data output by the decoder in the order of receiving time, and write the combined picture stream data into the picture stream data storage 4. With such a configuration, firstly, the picture stream data which needs to be output finally can be formed through the splicing process, no further processing is required by other circuits, and secondly, a buffer link is added through the setting of the picture stream data storage 4, so that the picture stream data which needs to be output finally is smoother, and the possibility of interruption or delay is further reduced. It is to be understood that "direct concatenation" herein is to be understood as a simple concatenation process, such as directly combining two data, or deleting some data at the end of the first data and/or deleting some data at the head of the second data, and then directly combining the processed two data. All concatenation procedures that require at least one of decoding, reordering, and data conversion are not to be understood as "direct concatenation".
Further, the data processing mode of the picture stream data storage 4 is first-in first-out. So configured, the picture stream data storage 4 can match the timing of the run length decoding digital circuit outputting data to the external circuit at the end when storing and deleting data, and no additional conversion is needed.
In an embodiment, the storage control module 3 is further configured to read the picture stream data stored in the picture stream data storage 4 and output the picture stream data to an external circuit. The whole function of the run-length decoding digital circuit is completely realized by the configuration.
In a preferred embodiment, when the available storage space of the picture stream data storage 4 is smaller than or equal to a preset ratio, the storage control module 3 suspends writing data into the picture stream data storage 4. So configured, it is prevented that in a special case, after the picture stream data storage 4 is filled, the redundant picture stream data is lost, thereby causing an error in the whole run length decoding digital circuit. The preset proportion can be set according to actual conditions, and preferably is 1/2. With the configuration, both the safety and the utilization rate of the storage space can be considered. It should be understood that when the storage control module 3 suspends writing data, the operating logic of other modules may be set according to the actual situation, for example, data is suspended on the storage control module 3, or the decoder 2 suspends outputting data synchronously, or the decoding control module suspends outputting compressed data, etc. The communication and trigger logic between the modules may also be configured according to actual situations, and will not be described in detail here.
In an embodiment, the run-length decoding digital circuit further comprises a memory 5, the memory 5 is used for storing the compressed data to be decoded, and the decoding control module 1 acquires the compressed data from the memory 5. The decoding control module 1 can be connected to the memory 5 via a memory control module 6 in order to better read the data inside the memory 5. The control logic of the memory control module 6 can be configured according to actual needs and common knowledge by those skilled in the art, and will not be described in detail herein. Preferably, the Memory 5 is a Static Random-Access Memory (SRAM), and the Memory control module 6 is an SRAM control module. In other embodiments, other forms of Memory and Memory control module, such as a ROM (Read-Only Memory) and its control module, may be selected as long as the compressed data can be continuously Read.
As described in the background art, the implementation of the OSD function includes five steps, and the run-length decoding digital circuit disclosed in this embodiment optimizes step 3 of the five steps, and implements the functions of step 1 and step 3.
The embodiment also provides an OSD circuit for implementing a complete OSD function, where the OSD circuit includes the above run length decoding digital circuit and a superimposition module, and the superimposition module is configured to receive first picture stream data in a preset format sent by the run length decoding digital circuit, receive second picture stream data in the preset format, and superimpose the first picture stream data and the second picture stream data according to a superimposition logic to obtain superimposed picture stream data. Other modules of the OSD circuit, the specific implementation manner inside the overlay module, and the connection relationship among the modules of the OSD circuit may be set by a person skilled in the art according to common knowledge, and are not specifically described here. Referring to fig. 4, in an embodiment, the video data in YUV format output by the OSD circuit is as shown in fig. 4, and as can be seen, the OSD circuit overcomes the problem of interruption and delay which are easily occurred in a conventional decoding circuit.
In summary, the run-length decoding digital circuit provided by the present invention includes a decoding control module 1 and two decoders 2, where the decoding control module 1 is configured to obtain compressed data of different data types, and send the obtained compressed data to the decoders 2 according to a first preset logic, and the decoders 2 are configured to decode the obtained compressed data into picture stream data in a preset format and output the picture stream data according to a second preset logic. The configuration is adopted, decoding is carried out in a hardware mode, and real-time performance is achieved; meanwhile, the two decoders 2 buffer each other and have enough time to decode the received compressed data, so that interruption and delay of picture stream data output by a common hardware decoding circuit, which are easy to occur, are avoided, and the requirements of an OSD function on the picture stream data to be superimposed are met.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.
Claims (10)
1. A digital circuit for run decoding is characterized in that the digital circuit for run decoding comprises a decoding control module and two decoders, wherein the decoding control module is used for acquiring compressed data of different data types and sending the acquired compressed data to the decoders according to a first preset logic, and the decoders are used for decoding the acquired compressed data into picture stream data in a preset format and outputting the picture stream data according to a second preset logic; the compressed data is picture stream data in a run-length coding format.
2. The run length decoding digital circuit of claim 1 wherein the first preset logic comprises alternately sending the compressed data to two of the decoders and sending compressed data to only one of the decoders at a time.
3. The run length decoding digital circuit of claim 2 wherein the first preset logic further comprises transmitting only the compressed data of the same data type before switching the transmission target.
4. A run length decoding digital circuit according to claim 1 wherein said second preset logic comprises two of said decoders alternately outputting picture stream data uninterruptedly, only one of said decoders outputting data at a time.
5. The run-length decoding digital circuit according to claim 4, further comprising a storage control module and a picture stream data memory, wherein the storage control module is configured to directly splice the picture stream data outputted from the decoder in order of reception time and write the combined picture stream data into the picture stream data memory.
6. The run length decoding digital circuit according to claim 5, wherein the data processing mode of the picture stream data memory is first-in first-out.
7. The run-length decoding digital circuit of claim 5, wherein the storage control module is further configured to read the picture stream data stored in the picture stream data storage and output the picture stream data to an external circuit.
8. The run-length decoding digital circuit according to claim 5, wherein the memory control module suspends writing data into the picture stream data memory when the available storage space of the picture stream data memory is less than or equal to a preset ratio.
9. The run length decoding digital circuit of claim 8 wherein the predetermined ratio is 1/2.
10. The run length decoding digital circuit of claim 1 further comprising a memory for storing the compressed data to be decoded, the decode control module retrieving the compressed data from the memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011506128.7A CN112600565A (en) | 2020-12-18 | 2020-12-18 | Digital circuit for decoding run length |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011506128.7A CN112600565A (en) | 2020-12-18 | 2020-12-18 | Digital circuit for decoding run length |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112600565A true CN112600565A (en) | 2021-04-02 |
Family
ID=75199446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011506128.7A Pending CN112600565A (en) | 2020-12-18 | 2020-12-18 | Digital circuit for decoding run length |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112600565A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022127913A1 (en) * | 2020-12-18 | 2022-06-23 | 上海集成电路研发中心有限公司 | Run-length decoding circuit, control method, electronic device, and readable storage medium |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1241871A (en) * | 1998-07-07 | 2000-01-19 | C-立方微系统股份有限公司 | MPEG start code compatible overlay graphics encoding |
| CN1246019A (en) * | 1998-07-14 | 2000-03-01 | 汤姆森消费电子有限公司 | System for producing decode low-resolution video signal from code high-resolution video signal |
| CN1279859A (en) * | 1997-11-27 | 2001-01-10 | 德国汤姆森-布兰特有限公司 | Apparatus for generating a digital video picture |
| US6721455B1 (en) * | 1998-05-08 | 2004-04-13 | Apple Computer, Inc. | Method and apparatus for icon compression and decompression |
| US20050212969A1 (en) * | 2004-03-23 | 2005-09-29 | Via Technologies Inc. | Apparatus and method of image display with real-time compression |
| CN1755797A (en) * | 2004-09-30 | 2006-04-05 | 松下电器产业株式会社 | Audio decoding apparatus |
| CN1805517A (en) * | 2005-01-14 | 2006-07-19 | 三星电子株式会社 | System and method of decoding dual video signals |
| CN101378447A (en) * | 2007-08-31 | 2009-03-04 | 佳能株式会社 | Image decoding apparatus and method, and printing apparatus |
| JP2011151572A (en) * | 2010-01-21 | 2011-08-04 | Renesas Electronics Corp | Image data processor and operating method thereof |
| CN102547280A (en) * | 2010-12-24 | 2012-07-04 | 微软公司 | Image and video decoding implementations |
| US20130162679A1 (en) * | 2011-12-27 | 2013-06-27 | Samsung Electro-Mechanics Co., Ltd. | Apparatus and method for embodying overlay images using mrlc |
| CN103988518A (en) * | 2011-11-25 | 2014-08-13 | 日立麦克赛尔株式会社 | Image transmission device, image transmission method, image reception device, and image reception method |
-
2020
- 2020-12-18 CN CN202011506128.7A patent/CN112600565A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1279859A (en) * | 1997-11-27 | 2001-01-10 | 德国汤姆森-布兰特有限公司 | Apparatus for generating a digital video picture |
| US6721455B1 (en) * | 1998-05-08 | 2004-04-13 | Apple Computer, Inc. | Method and apparatus for icon compression and decompression |
| CN1241871A (en) * | 1998-07-07 | 2000-01-19 | C-立方微系统股份有限公司 | MPEG start code compatible overlay graphics encoding |
| CN1246019A (en) * | 1998-07-14 | 2000-03-01 | 汤姆森消费电子有限公司 | System for producing decode low-resolution video signal from code high-resolution video signal |
| US20050212969A1 (en) * | 2004-03-23 | 2005-09-29 | Via Technologies Inc. | Apparatus and method of image display with real-time compression |
| CN1755797A (en) * | 2004-09-30 | 2006-04-05 | 松下电器产业株式会社 | Audio decoding apparatus |
| CN1805517A (en) * | 2005-01-14 | 2006-07-19 | 三星电子株式会社 | System and method of decoding dual video signals |
| CN101378447A (en) * | 2007-08-31 | 2009-03-04 | 佳能株式会社 | Image decoding apparatus and method, and printing apparatus |
| JP2011151572A (en) * | 2010-01-21 | 2011-08-04 | Renesas Electronics Corp | Image data processor and operating method thereof |
| CN102547280A (en) * | 2010-12-24 | 2012-07-04 | 微软公司 | Image and video decoding implementations |
| CN103988518A (en) * | 2011-11-25 | 2014-08-13 | 日立麦克赛尔株式会社 | Image transmission device, image transmission method, image reception device, and image reception method |
| US20130162679A1 (en) * | 2011-12-27 | 2013-06-27 | Samsung Electro-Mechanics Co., Ltd. | Apparatus and method for embodying overlay images using mrlc |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022127913A1 (en) * | 2020-12-18 | 2022-06-23 | 上海集成电路研发中心有限公司 | Run-length decoding circuit, control method, electronic device, and readable storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2134092B1 (en) | Information processing apparatus and method, and program | |
| US5790179A (en) | Multi-point motion picture encoding and decoding apparatus | |
| EP2061255A1 (en) | Information processing device and method | |
| US11500804B2 (en) | Method for transmitting control instruction, transmitting device, and receiving device | |
| EP2648411A1 (en) | Image encoding device, and image encoding method | |
| CN110113610A (en) | Data transmission method and device | |
| CN112600565A (en) | Digital circuit for decoding run length | |
| WO2023024421A1 (en) | Method and system for splicing multiple channels of images, and readable storage medium and unmanned vehicle | |
| US20150103895A1 (en) | Electronic devices for signaling multiple initial buffering parameters | |
| US10349073B2 (en) | Decoding device, image transmission system, and decoding method | |
| US9066111B2 (en) | Image encoder and method for encoding images | |
| JPS589470A (en) | Transmitting method of facsimile data | |
| US11516503B2 (en) | Encoding apparatus, decoding apparatus, encoding method, decoding method, and storage medium | |
| KR20020015219A (en) | Apparatus and method for video transmission in video conferencing system | |
| JP2004007066A (en) | Picture transmission device | |
| JP3595563B2 (en) | Moving image processing method and apparatus | |
| CN218041574U (en) | High-definition video signal transmission system | |
| JP2988686B2 (en) | Radiation receiving system | |
| CN112600566A (en) | Digital circuit for decoding run length | |
| CN212850675U (en) | Zynq FPGA-based low-illumination handheld terminal | |
| JP2817818B2 (en) | Image transmission device | |
| KR20020052220A (en) | The method of compression and decompression of high resolution image using mpeg | |
| JPH11136683A (en) | Video signal coder | |
| WO2021102992A1 (en) | Data transmissio method, device and system as well as storage medium | |
| US6741654B1 (en) | MPEG decoding circuit displaying images and incrusted images |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |