CN112599181A - Flash memory chip analysis method and device, electronic equipment and storage medium - Google Patents
Flash memory chip analysis method and device, electronic equipment and storage medium Download PDFInfo
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- CN112599181A CN112599181A CN202011446240.6A CN202011446240A CN112599181A CN 112599181 A CN112599181 A CN 112599181A CN 202011446240 A CN202011446240 A CN 202011446240A CN 112599181 A CN112599181 A CN 112599181A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
Abstract
The invention is suitable for the technical field of computers, and provides a flash memory chip analysis method, a flash memory chip analysis device, electronic equipment and a storage medium, wherein the method comprises the following steps: carrying out data retention capability test on the flash memory chip through the BCH code; baking the memory chips in different states, and testing the data retention capacity of the physical memory blocks with different erasing times in the flash memory chips through the BCH codes; and recording and analyzing the test results of the flash memory chip at a plurality of time points to obtain the characteristics of the flash memory chip. The method provided by the invention solves the problems that the existing flash memory core is unstable to use in different test scenes and platforms and has short service life.
Description
Technical Field
The invention belongs to the technical field of computers, and particularly relates to a flash memory chip analysis method and device, electronic equipment and a storage medium.
Background
For the data error correction in flash memory chips, two mainstream error correction codes at present are BCH codes and LDPC codes. An LDPC Code (Low Density Parity Check Code, LDPC) is a linear block Code having a sparse Check matrix, and has a Low decoding complexity and a flexible structure. The BCH code (abbreviation of Bose, Ray-Chaudhuri, Hocquenghem) is a cyclic code capable of correcting multiple random errors, has a strict algebraic structure and strong error correction capability, and is one of linear block codes, wherein the error correction performance of the BCH code is close to a theoretical value particularly under short and medium code lengths.
Flash wafers produced by different manufacturers on the market have different processes and qualities, and different Flash memory chips produced by the same manufacturer are different in expression when being applied to storage products taking BCH codes as error correction engines, and even different batches of Flash memory chips of the same model have different qualities; the use of such flash memory chips in different test scenes and platforms is unstable, and the unique characteristics of the flash memory chips easily cause product defects.
Disclosure of Invention
The embodiment of the invention aims to provide a flash memory chip analysis method, and aims to solve the problems that the existing flash memory chip is unstable to use in different test scenes and platforms and has short service life.
The embodiment of the invention is realized in such a way that a flash memory chip analysis method comprises the following steps:
carrying out data retention capability test on the flash memory chip through the BCH code;
baking the memory chips in different states, and testing the data retention capacity of the physical memory blocks with different erasing times in the flash memory chips through the BCH codes;
and recording and analyzing the test results of the flash memory chip at a plurality of time points to obtain the characteristics of the flash memory chip.
Further, before the step of testing the data retention capability of the physical memory blocks with different erase times in the flash memory chip, the method further comprises the steps of:
burning a firmware program into the flash memory chip;
and writing test item data into the flash memory chip.
Furthermore, the method for baking the memory chips in different states comprises the following steps:
and baking the memory chip at 120 ℃.
Further, after the step of burning the firmware program into the flash memory chip, the method further comprises the steps of:
and testing the memory chip in a first state, wherein the first state is that the memory pages of a plurality of physical memory blocks in the flash memory chip are in an unfilled state.
Further, after the step of burning the firmware program into the flash memory chip, the method further comprises the steps of:
and testing the memory chip in a second state, wherein the flash memory chip is in an SLC mode in the second state.
Further, after the step of burning the firmware program into the flash memory chip, the method further comprises the steps of:
and testing the memory chip in a third state, wherein the flash memory chip is in an MLC (multi-level cell) or TLC (thin-layer chromatography) mode in the third state.
Another embodiment of the present invention further provides a flash memory chip analysis apparatus, including:
the BCH code is used for testing the data retention capability of the flash memory chip and testing the data retention capability of the physical memory blocks with different erasing times in the flash memory chip;
the constant temperature and humidity box is used for baking the storage chips in different states;
and the record analysis module is used for recording and analyzing the test results of the flash memory chip at a plurality of time points so as to obtain the characteristics of the flash memory chip.
Still further, the apparatus further comprises:
the burning module is used for burning a firmware program into the flash memory chip;
and the data writing module is used for writing the test item data into the flash memory chip.
Another embodiment of the present invention is also directed to an electronic device, including: a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps in the flash memory chip analysis method as described in any one of the above when executing the computer program.
Another embodiment of the present invention further provides a computer-readable storage medium, having a computer program stored thereon, where the computer program, when executed by a processor, implements the steps in the method for analyzing a flash memory chip as described in any one of the above.
The invention has the beneficial effects that: carrying out data retention capability test on the flash memory chip through the BCH code; baking the memory chips in different states, and testing the data retention capacity of the physical memory blocks with different erasing times in the flash memory chips through the BCH codes; recording and analyzing the test results of the flash memory chip at a plurality of time points to obtain the characteristics of the flash memory chip; by simulating the daily use environment of the flash memory chip and the limit condition, and taking BCH code and other characteristic analysis software and firmware as the basis, the test scheme is set to obtain a large amount of needed ECC data, the critical trip point of the ECC changing along with the external temperature environment is found out, and data support is provided for the firmware development of the flash memory chip, so that the flash memory chip stores the data on a physical storage block with better holding capacity, and the service life and the stability of a product are improved.
Drawings
FIG. 1 is a flow chart of a method for analyzing a flash memory chip according to an embodiment of the present invention;
FIG. 2 is a flowchart of a method for analyzing a flash memory chip according to an embodiment of the present invention;
FIG. 3 is a flowchart of a method for analyzing a flash memory chip according to an embodiment of the present invention;
FIG. 4 illustrates a portion of ECC or other indicator data for a physical memory block in a flash memory chip analysis method test item;
FIG. 5 illustrates another portion of ECC or other indicator data for a physical memory block in a flash memory chip analysis method test item;
FIG. 6 is a block diagram of an apparatus for analyzing a flash memory chip according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The BCH code is provided to acquire a large amount of needed ECC data, so that data support is provided for firmware development of the flash memory chip, and the service life and the stability of a product are improved; the storage chips in different states are baked, the daily use environment and the use environment under the limit condition of the flash memory chip are simulated, and the holding capacity of the flash memory chip in different operation states in different time periods is obtained.
Specific implementations of the present invention are described in detail below with reference to specific examples.
Example one
Referring to fig. 1, the method for analyzing a flash memory chip according to a first embodiment of the present invention includes steps S01 to S03:
step S01, the flash memory chip is tested for data retention capability through BCH code.
Step S02, baking the memory chips in different states, and testing the data retention capability of the physical memory blocks with different erasing times in the flash memory chips through the BCH code.
Step S03, recording and analyzing the test results of the flash memory chip at multiple time points to obtain the characteristics of the flash memory chip.
Specifically, in the present embodiment, the data retention (i.e., data retention) of the flash memory chip with low erase count is tested, wherein the flash memory chip with low erase count is the flash memory chip just after production and processing is completed, and the erase count is low because the use count is small. During testing, the temperature is controlled to be kept at 120 ℃ by means of constant temperature and humidity box constant temperature control equipment, full disk data are copied to a tested sample in a normal temperature state, standing and baking are carried out for 168 hours in total, multiple sampling points are set according to different baking time, and ECC data are read. Simulating a platform installation burning system and configuring a user App by using the process, and restarting the machine after placing for different periods of time; and then, sorting, counting and analyzing the data acquired by each sampling point, and analyzing to obtain the rule that the ECC changes along with time on the premise of low erasing times, namely the retention capacity of all data in each physical storage block of the flash memory chip in different time periods is strong and weak. Therefore, important data in the flash memory chip can be stored in the area with strong holding capacity, and data which is frequently erased and written is stored in the physical storage block with weak holding capacity, so that the service life and the stability of the flash memory chip are improved.
It should be noted that, in a physical memory block (flash memory structure of nand flash, minimum unit of erase operation) with different erase times, the data retention capability is tested along with the temperature variation; setting the temperature of the constant temperature and humidity chamber to be constant at 120 ℃, using character analysis software such as BCH codes and the like to burn firmware programs into the flash memory chips and carrying out erasing and writing test of private commands, so that the erasing times of the designated physical memory blocks reach a required value, reading ECC original data, then putting the ECC original data into the constant temperature and humidity chamber, and standing and baking the ECC original data to simulate that the data is placed for one year, two years or more in practical use.
The invention has the beneficial effects that: carrying out data retention capability test on the flash memory chip through the BCH code; baking the memory chips in different states, and testing the data retention capacity of the physical memory blocks with different erasing times in the flash memory chips through the BCH codes; recording and analyzing the test results of the flash memory chip at a plurality of time points to obtain the characteristics of the flash memory chip; by simulating the daily use environment of the flash memory chip and the use environment of the limit condition, and taking BCH code and other characteristic analysis software and firmware as the basis, a test scheme is set to obtain a large amount of needed ECC data, the critical trip point of the ECC changing along with the external temperature environment is found out, data support is provided for the firmware development of the flash memory chip, and the service life and the stability of a product are improved.
Example two
In an embodiment of the invention, referring to fig. 2, before the step S02, the method further includes steps S04 to S05:
in step S04, a firmware program is burned into the flash memory chip.
Step S05, writing test item data into the flash memory chip.
Specifically, a firmware program is burned into the flash memory chip through characteristic analysis software, erasing and reading tests of private commands are carried out, the erasing times of the specified physical memory block reach a required value, ECC original data are read and then put into a constant temperature and humidity box, and data are placed for one year, two years or many years in the actual use of standing and baking simulation.
EXAMPLE III
In another embodiment of the present invention, after the step of burning the firmware program into the flash memory chip, the method further includes the steps of:
step S06, testing the memory chip in a first state, where the first state is an unfilled state of the memory pages of the physical memory blocks in the flash memory chip.
Specifically, when each storage page of the physical storage block is filled with data, the physical storage block is in a closed state; when some blank storage pages exist in the physical storage block, the physical storage block is in an open state;
by the mode, when the platform is used, if the written data exceed the storage capacity of one or more physical storage blocks, after the platform is processed by firmware, part of physical check of the flash memory is in a closed state, and some physical storage blocks are in an open state because the data are not full, so that the normal use state of the flash memory chip is simulated.
Step S07, the memory chip in the second state is tested, please refer to fig. 3, where the second state is that the flash memory chip is in SLC mode.
Specifically, during the operation of the flash memory chip, there is an SLC (Single Level Cell Single layer Cell) mode, that is, an SLC physical memory block, a lower page of a word line written in the physical memory block each time, a lower/upper page of each word line of an MLC (multi-layer Cell) flash memory, and a lower/middle/upper page of each word line of a TLC (three-layer Cell) flash memory. The data written in the SLC mode is stable, the ECC has small amplitude along with the temperature change, and the ECC is usually used for storing key table items and system data required by firmware.
Step S08, the memory chip in the third state is tested, where the third state is that the flash memory chip is in the MLC or TLC mode.
Specifically, when the flash memory chip uses Normal mode, i.e. MLC/TLC mode, all the memory pages of each word line in the physical memory block need to be written to full.
Normal mode physical memory blocks are generally used for storing user data or platform system data, and ECC of these physical memory blocks is greatly influenced by temperature, humidity and PE (erasure) times.
Specifically, the characteristics of a certain flash memory chip are counted and obtained by sorting, combining and analyzing ECC data. ECC or other index data of the physical storage blocks in each test item are processed by using an Excel table, so that the characteristics of some storage pages in the flash memory blocks can be clearly presented. As shown in FIG. 4 and FIG. 5, ECC statistics of pages 1766-1789 of TLC blocks 64-96 after 168h baking are shown. As can be seen from the longitudinal comparison of the word lines, each word line in this interval exhibits a lower page ECC value significantly smaller than that of the middle/upper page, which is relatively stable.
Example four
Another embodiment of the present invention further provides a flash memory chip analysis apparatus, referring to fig. 6, the apparatus including:
the BCH code 10 is used for testing the data retention capability of the flash memory chip and testing the data retention capability of the physical memory blocks with different erasing times in the flash memory chip;
the constant temperature and humidity box 20 is used for baking the memory chips in different states;
the record analysis module 30 records and analyzes the test results of the flash memory chip at a plurality of time points to obtain the characteristics of the flash memory chip.
The flash memory chip analysis device tests the data retention capacity of the flash memory chip through the BCH code 10; baking the memory chips in different states through a constant temperature and humidity box 20, and testing the data retention capacity of the physical memory blocks with different erasing times in the flash memory chips through the BCH code 10; recording and analyzing the test results of the flash memory chip at a plurality of time points through a recording and analyzing module 30 to obtain the characteristics of the flash memory chip; by simulating the daily use environment of the flash memory chip and the use environment of the limit condition, and taking BCH code and other characteristic analysis software and firmware as the basis, a test scheme is set to obtain a large amount of needed ECC data, the critical trip point of the ECC changing along with the external temperature environment is found out, data support is provided for the firmware development of the flash memory chip, and the service life and the stability of a product are improved.
EXAMPLE five
Another embodiment of the present invention further provides a flash memory chip analysis apparatus, please refer to fig. 6, where the apparatus further includes:
a burning module 40, configured to burn a firmware program into the flash memory chip;
and a data writing module 50 for writing the test item data into the flash memory chip.
Specifically, a firmware program is burned into the flash memory chip through the burning module 40 in the characteristic analysis software, and the erasing and writing test of the private command is performed through the data writing module 50, so that the erasing times of the specified physical memory block reach a required value, the ECC original data is read and then put into a constant temperature and humidity box, and the data is placed for one year, two years or many years in the static baking simulation practical use.
EXAMPLE six
In order to solve the foregoing technical problem, an embodiment of the present application further provides an electronic device for a flash memory chip analysis method. Referring to fig. 7 in detail, fig. 7 is a block diagram of a basic structure of the electronic device of the present embodiment, as shown in fig. 7.
The electronic device 14 comprises a memory 1401, a processor 1402, a network interface 1403 communicatively connected to each other via a system bus. It is noted that only electronic device 14 having components 1401 and 1403 is shown, but it is understood that not all of the shown components need be implemented, and that more or fewer components can be implemented instead. As will be understood by those skilled in the art, the electronic device is a device capable of automatically performing numerical calculation and/or information processing according to a preset or stored instruction, and the hardware includes, but is not limited to, a microprocessor, an Application Specific Integrated Circuit (ASIC), a Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), an embedded device, and the like.
The electronic device may be a desktop computer, a notebook, a palm computer, a cloud server, or other computing device. The electronic equipment can be in man-machine interaction with a user through a keyboard, a mouse, a remote controller, a touch panel or voice control equipment and the like.
The memory 1401 includes at least one type of readable storage medium including a flash memory, a hard disk, a multimedia card, a card type memory (e.g., SD or DX memory, etc.), a Random Access Memory (RAM), a Static Random Access Memory (SRAM), a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a Programmable Read Only Memory (PROM), a magnetic memory, a magnetic disk, an optical disk, etc. In some embodiments, the storage 1401 may be an internal storage unit of the electronic device 14, such as a hard disk or a memory of the electronic device 14. In other embodiments, the memory 1401 may also be an external storage device of the electronic device 14, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the electronic device 14. Of course, the memory 1401 may also include both internal and external memory units of the electronic device 14. In this embodiment, the memory 1401 is generally configured to store an operating system installed in the electronic device 14 and various types of application software, such as program codes of a flash chip analysis method. The memory 1401 may also be used to temporarily store various types of data that have been output or are to be output.
The processor 1402 may be, in some embodiments, a Central Processing Unit (CPU), a controller, a microcontroller, a microprocessor, or other data Processing chip. The processor 1402 is generally configured to control the overall operation of the electronic device 14. In this embodiment, the processor 1402 is configured to run the program code stored in the memory 1401 or process data, for example, the program code of the flash memory chip analysis method.
The network interface 1403 may include a wireless network interface or a wired network interface, and the network interface 1403 is generally used for establishing a communication connection between the electronic device 14 and other electronic devices.
EXAMPLE seven
The present application further provides another embodiment, which is to provide a computer-readable storage medium storing a flash memory chip analysis method program, where the flash memory chip analysis method program is executable by at least one processor to cause the at least one processor to perform the steps of the flash memory chip analysis method.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present application.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A flash memory chip analysis method is characterized by comprising the following steps:
carrying out data retention capability test on the flash memory chip through the BCH code;
baking the memory chips in different states, and testing the data retention capacity of the physical memory blocks with different erasing times in the flash memory chips through the BCH codes;
and recording and analyzing the test results of the flash memory chip at a plurality of time points to obtain the characteristics of the flash memory chip.
2. The flash memory chip analysis method of claim 1, wherein prior to the step of testing the data retention capability of the physical memory blocks of different erase counts within the flash memory chip, the method further comprises the steps of:
burning a firmware program into the flash memory chip;
and writing test item data into the flash memory chip.
3. The method of claim 1, wherein the step of baking the memory chips in different states comprises the steps of:
and baking the memory chip at 120 ℃.
4. The method of claim 2, wherein after the step of burning the firmware program into the flash memory chip, the method further comprises the steps of:
and testing the memory chip in a first state, wherein the first state is that the memory pages of a plurality of physical memory blocks in the flash memory chip are in an unfilled state.
5. The method of claim 2, wherein after the step of burning the firmware program into the flash memory chip, the method further comprises the steps of:
and testing the memory chip in a second state, wherein the flash memory chip is in an SLC mode in the second state.
6. The method of claim 2, wherein after the step of burning the firmware program into the flash memory chip, the method further comprises the steps of:
and testing the memory chip in a third state, wherein the flash memory chip is in an MLC (multi-level cell) or TLC (thin-layer chromatography) mode in the third state.
7. An apparatus for analyzing a flash memory chip, the apparatus comprising:
the BCH code is used for testing the data retention capability of the flash memory chip and testing the data retention capability of the physical memory blocks with different erasing times in the flash memory chip;
the constant temperature and humidity box is used for baking the storage chips in different states;
and the record analysis module is used for recording and analyzing the test results of the flash memory chip at a plurality of time points so as to obtain the characteristics of the flash memory chip.
8. The flash memory chip analysis apparatus of claim 7, wherein the apparatus further comprises:
the burning module is used for burning a firmware program into the flash memory chip;
and the data writing module is used for writing the test item data into the flash memory chip.
9. An electronic device, comprising: memory, processor and computer program stored on the memory and executable on the processor, the processor implementing the steps in the flash memory chip analysis method according to any one of claims 1 to 6 when executing the computer program.
10. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, implements the steps in the flash memory chip analysis method of any one of claims 1 to 6.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117809724A (en) * | 2024-03-01 | 2024-04-02 | 四川云海芯科微电子科技有限公司 | NAND Flash wear balancing method based on life test |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5287313A (en) * | 1991-08-07 | 1994-02-15 | Rohm Co., Ltd. | Method of testing data-holding capability of a semiconductor memory device |
| US6813752B1 (en) * | 2002-11-26 | 2004-11-02 | Advanced Micro Devices, Inc. | Method of determining charge loss activation energy of a memory array |
| CN107025941A (en) * | 2016-01-29 | 2017-08-08 | 瑞昱半导体股份有限公司 | Solid state hard disc controls circuit |
| CN108231108A (en) * | 2016-12-14 | 2018-06-29 | 爱思开海力士有限公司 | Memory device and its operating method |
| CN108647111A (en) * | 2018-05-14 | 2018-10-12 | 联芸科技（杭州）有限公司 | Read control device, reading and control method thereof and Memory Controller for memory |
| CN110517718A (en) * | 2019-08-22 | 2019-11-29 | 深圳忆联信息系统有限公司 | A kind of Effective selection particle increases the method and its system of bad block newly |
-
2020
- 2020-12-11 CN CN202011446240.6A patent/CN112599181A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5287313A (en) * | 1991-08-07 | 1994-02-15 | Rohm Co., Ltd. | Method of testing data-holding capability of a semiconductor memory device |
| US6813752B1 (en) * | 2002-11-26 | 2004-11-02 | Advanced Micro Devices, Inc. | Method of determining charge loss activation energy of a memory array |
| CN107025941A (en) * | 2016-01-29 | 2017-08-08 | 瑞昱半导体股份有限公司 | Solid state hard disc controls circuit |
| CN108231108A (en) * | 2016-12-14 | 2018-06-29 | 爱思开海力士有限公司 | Memory device and its operating method |
| CN108647111A (en) * | 2018-05-14 | 2018-10-12 | 联芸科技（杭州）有限公司 | Read control device, reading and control method thereof and Memory Controller for memory |
| CN110517718A (en) * | 2019-08-22 | 2019-11-29 | 深圳忆联信息系统有限公司 | A kind of Effective selection particle increases the method and its system of bad block newly |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117809724A (en) * | 2024-03-01 | 2024-04-02 | 四川云海芯科微电子科技有限公司 | NAND Flash wear balancing method based on life test |
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