CN117809724A - NAND Flash wear balancing method based on life test - Google Patents
NAND Flash wear balancing method based on life test Download PDFInfo
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- CN117809724A CN117809724A CN202410233584.0A CN202410233584A CN117809724A CN 117809724 A CN117809724 A CN 117809724A CN 202410233584 A CN202410233584 A CN 202410233584A CN 117809724 A CN117809724 A CN 117809724A
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- 238000012360 testing method Methods 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000005299 abrasion Methods 0.000 claims description 21
- 235000012431 wafers Nutrition 0.000 claims description 14
- 230000015654 memory Effects 0.000 claims description 13
- 230000006870 function Effects 0.000 claims description 10
- 230000000694 effects Effects 0.000 claims description 8
- 230000001419 dependent effect Effects 0.000 claims description 4
- 238000011990 functional testing Methods 0.000 description 3
- 238000004590 computer program Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
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Abstract
The invention discloses a NAND Flash wear balancing method based on life test, which belongs to the technical field of storage and comprises the following steps: and testing the service life of each block on the grain DIE, using the test result as a reference of the maximum service life of the block, and using the ratio of the current wear times to the maximum erasable times in the wear balance design as a reference standard of the wear balance design, so that the wear ratio of all blocks is kept average, and the purpose of using the service life of the block to the maximum is achieved. The invention can prolong the service life of the hard disk.
Description
Technical Field
The invention relates to the technical field of storage, in particular to a NAND Flash wear balancing method based on life test.
Background
As can be seen from the physical characteristics of NAND FLASH, flash memories are not perfect storage media, and both traditional 2D flash memories and currently mainstream 3D flash memories have certain reliability problems.
First, after writing data into the flash memory, the data is stored in the transistor with the floating gate surrounded by the insulator up and down. However, as time goes by, electrons stored in the floating gate can "escape" through the insulating layer under the action of the intrinsic electric field, when the number of the "escape" electrons reaches a certain amount, the "0" bit is turned to "1", and when the number of the "0" bit is turned to exceed the error correction capability of the controller, the situation of user data loss occurs. Second, when we read a flash page each time, to ensure that the other floating gate transistors turn on, an on voltage needs to be applied on the other word lines, which can cause these transistors to suffer from slight "programming", as flash blocks are read more and more times, more electrons enter the floating gate transistors, which can eventually lead to bit flipping. Finally, the flash memory cannot directly perform the overwriting operation, and new data can be written into the block again after the block is erased. As the number of erasing increases, the isolation effect of the tunnel oxide layer for isolating electrons from the floating gate becomes worse, and as a result, electrons get in and out of the floating gate easily, and finally, the number of electrons stored in the floating gate may change unexpectedly, so that the data is changed from "0" to "1" or from "1" to "0". As shown in fig. 1, when a read operation is performed on WL1 (word line 1), the control electrode of the unselected flash page in the flash block is applied with a positive voltage to ensure that the unselected MOS transistor is turned on. But this brings about some slight "programming" which eventually may lead to bit flipping as the flash block is read more and more times.
Because of the above list, for blocks that have been written with data and have not been garbage-reclaimed for a long time, there is a risk of data loss; secondly, the block is too low in use rate in the SSD disk, so that the wear of the block is uneven, and some blocks are damaged in the service life. Flash memories are limited in the number of erasures, and if the number of erasures exceeds a certain value, the block becomes unreliable and even a bad block. Therefore, the firmware in the SSD needs to be subjected to wear leveling in the design of the firmware, so that all flash memory blocks are used together to bear the writing of user data, and more user data writing can be carried out, and the writing can not be continuously carried out for a certain number of blocks, so that the SSD is hung up before the warranty period.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a NAND Flash wear balancing method based on a life test, which can prolong the service life of a hard disk.
The invention aims at realizing the following scheme:
a NAND Flash wear balancing method based on life test comprises the following steps:
and testing the service life of each block on the grain DIE, using the test result as a reference of the maximum service life of the block, and using the ratio of the current wear times to the maximum erasable times in the wear balance design as a reference standard of the wear balance design, so that the wear ratio of all blocks is kept average, and the purpose of using the service life of the block to the maximum is achieved.
Further, the service life of each block on the DIE is tested, the test result is used as a reference of the maximum service life of the block, in the wear balance design, the ratio of the current wear times to the maximum erasable times is used as a reference standard of the wear balance design, so that the wear ratio of all blocks is kept average, and the purpose of maximally utilizing the service life of the block is achieved, and the method specifically comprises the following sub-steps:
s1, predicting the service life of a NAND Flash memory block;
s2, based on different maximum erasable frequency values obtained in life prediction, the maximum erasable frequency values are used as dependent data and stored in a hard disk;
s3, after each pair of blocks of the hard disk is subjected to one-time erasing operation, recording the current erasing times;
s4, recording the ratio of the current wear times to the maximum erasable times as a wear ratio value;
s5, selecting a block with the minimum abrasion proportion value as an abrasion balance selecting block;
s6, moving the data of the blocks with the abrasion proportion smaller than the first set value to the blocks with the abrasion proportion higher than the second set value, so as to achieve the effect of abrasion balance; the first set value and the second set value are empirically chosen values, and the first set value is smaller than the second set value.
Further, in step S1, the life prediction of the NAND Flash block specifically includes the following sub-steps:
s11, selecting a plurality of wafers as test samples;
s12, testing the DIE DIE, wherein the test needs to be covered on each position of the wafer;
s13, taking blocks with the same block serial numbers on all the grains DIE as a group for abrasion;
s14, carrying out corresponding function test after the set values are worn every time;
s15, judging that the block fails if any test in the step S14 fails, and recording the erased number of times of the last successful test of the block as the maximum erasable number of times;
s16, counting the maximum erasable frequency values of all the blocks, and taking the minimum value as a new maximum erasable frequency value of the hard disk in actual use.
Further, in step S11, the plurality of wafers includes at least 3 wafers.
Further, in step S14, the set value number of times includes 1000 times.
Further, in step S14, the performing the corresponding functional test specifically includes the following sub-steps: after being placed at the first set temperature for a set time, the data can be successfully read by performing a read operation on the data; the first set temperature is an empirically set temperature.
Further, in step S14, the performing the corresponding functional test specifically includes the following sub-steps: and performing analog reading on all pages in the block, performing data reading on the pages, and testing whether the data can be successfully read.
Further, in step S14, the performing the corresponding functional test specifically includes the following sub-steps: writing the first set temperature into the second set temperature for reading, writing the second set temperature into the first set temperature for reading, and testing whether the reading and writing can be successfully performed; the first set temperature and the second set temperature are experience set temperatures, and the first set temperature is higher than the second set temperature.
Further, the set time includes 5 hours.
Further, the set time includes 6 hours.
The beneficial effects of the invention include:
according to the invention, the service life of each block on the grain DIE is tested, the test result is used as the reference of the maximum service life of the block, and in the wear balance design, the proportion of the current wear times to the maximum erasable times is used as the reference standard of the wear balance design, so that the wear proportion of all blocks is kept average, and the effect of maximally utilizing the service life of the block is achieved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a schematic diagram of a flash block with possible bit flipping; wherein Vcc is the supply voltage of the circuit, vpass is the pass voltage, V READ BL0 is bit line 0, BL1 is bit line 1, BL2 is bit line 2, BL3 is bit line 3, SSL is drain select transistor, WL0 is word line 0, WL1 is word line 1, WL2 is word line 2, GSL is source select transistor;
FIG. 2 is a flowchart illustrating steps of a method according to an embodiment of the present invention.
Detailed Description
All of the features disclosed in all of the embodiments of this specification, or all of the steps in any method or process disclosed implicitly, except for the mutually exclusive features and/or steps, may be combined and/or expanded and substituted in any way.
The inventor of the present invention found the following new technical problems:
each flash memory has specific erasing times limitation, the erasing times limitation for the flash memory blocks is directly provided by a manufacturer, and the provided erasing times limitation value is the worst erasable times value, so that all the blocks can be at least erased for the numerical value times.
Most existing wear leveling algorithms are designed according to manufacturer-supplied erasure count values, so that all blocks are smaller than this value during the service life of the entire SSD disk.
However, the life of different blocks on the same DIE (DIE) is also somewhat different, so that if wear leveling is performed solely according to the erasable values provided by the manufacturer, the ability to have longer life blocks is not demonstrated.
Therefore, the inventor of the invention considers that for SSD, the block capacity can be expected first, which blocks have strong capacities can be judged, and the blocks with weak capacities can be erased for a plurality of times, and relatively less erasing can be carried out for the blocks with weak capacities, so that the service life of the hard disk can be greatly prolonged.
Under the above conception, life test can be performed on all blocks on a DIE (DIE), the life condition of each block is recorded, and then wear balancing operation is performed according to the life condition of each block, so that the effect of prolonging the life of the SSD is finally achieved. In a further embodiment, as shown in fig. 2, the method for balancing NAND Flash wear based on life test provided by the invention comprises the following steps: 1) Testing the block life condition of all DIEs (DIE); 2) And carrying out wear balancing operation according to the service life condition of the block. Specifically, the method comprises the following steps:
and S1, carrying out service life prediction on the flash memory block.
1) At least 3 wafers were selected as test samples
2) Testing DIE substantially covers various locations of a wafer
3) The blocks with the same block number on all DIE (grains) are worn as a group
4) The corresponding function test is carried out every 1 thousand times, and the method specifically comprises the following substeps:
(1) after 5 and 6 hours of standing at the first set temperature (high temperature), the data can be read successfully.
(2) And performing analog reading on all pages in the block, and then performing data reading on the pages to see whether the data can be successfully read.
(3) And writing the first set temperature (high temperature) into the second set temperature (low temperature) for reading all the blocks, and writing the second set temperature (low temperature) into the first set temperature (high temperature) for reading and writing whether the blocks can be successfully read or written.
5) If any one of the previous tests fails, judging that the block fails, and recording the erased number of the last successful pass test of the block as the maximum erasable number.
6) And counting the maximum erasable frequency values of all the blocks, and taking the minimum value as a new maximum erasable frequency value of the hard disk in actual use.
Step S2, different maximum erasable frequency values obtained based on the test are stored in the hard disk as dependent data.
Step S3, after the SSD performs erasing operation on each block, recording the current erasing times.
And S4, recording the ratio of the current wear times to the maximum erasable times as a wear ratio value.
And S5, selecting the block with the smallest wear proportion value as a wear balance selecting block.
And S6, moving the data (cold data) of the blocks with smaller abrasion proportion to the blocks with higher abrasion proportion, so as to achieve the effect of abrasion balance.
It should be noted that, within the scope of protection defined in the claims of the present invention, the following embodiments may be combined and/or expanded, and replaced in any manner that is logical from the above specific embodiments, such as the disclosed technical principles, the disclosed technical features or the implicitly disclosed technical features, etc.
Example 1
A NAND Flash wear balancing method based on life test comprises the following steps:
and testing the service life of each block on the grain DIE, using the test result as a reference of the maximum service life of the block, and using the ratio of the current wear times to the maximum erasable times in the wear balance design as a reference standard of the wear balance design, so that the wear ratio of all blocks is kept average, and the purpose of using the service life of the block to the maximum is achieved.
Example 2
Based on the embodiment 1, the service life of each block on the DIE is tested, the test result is used as the reference of the maximum service life, in the wear balance design, the ratio of the current wear times to the maximum erasable times is used as the reference standard of the wear balance design, so that the wear ratio of all blocks is kept average, and the purpose of using the service life of the blocks is achieved, specifically comprising the following sub-steps:
s1, predicting the service life of a NAND Flash memory block;
s2, based on different maximum erasable frequency values obtained in life prediction, the maximum erasable frequency values are used as dependent data and stored in a hard disk;
s3, after each pair of blocks of the hard disk is subjected to one-time erasing operation, recording the current erasing times;
s4, recording the ratio of the current wear times to the maximum erasable times as a wear ratio value;
s5, selecting a block with the minimum abrasion proportion value as an abrasion balance selecting block;
s6, moving the data of the blocks with the abrasion proportion smaller than the first set value to the blocks with the abrasion proportion higher than the second set value, so as to achieve the effect of abrasion balance; the first set value and the second set value are empirically chosen values, and the first set value is smaller than the second set value. Specifically, the data of the block with the smaller wear ratio can be moved to the block with the higher wear ratio, thereby achieving the effect of wear balance. In a specific implementation, for example, assuming that one block can wear 10000 times in total, the data of the block worn 3000 times may be moved into the block 7000 times.
Example 3
On the basis of embodiment 2, in step S1, the life prediction of the NAND Flash block specifically includes the following sub-steps:
s11, selecting a plurality of wafers as test samples;
s12, testing the DIE DIE, wherein the test needs to be covered on each position of the wafer;
s13, taking blocks with the same block serial numbers on all the grains DIE as a group for abrasion;
s14, carrying out corresponding function test after the set values are worn every time;
s15, judging that the block fails if any test in the step S14 fails, and recording the erased number of times of the last successful test of the block as the maximum erasable number of times;
s16, counting the maximum erasable frequency values of all the blocks, and taking the minimum value as a new maximum erasable frequency value of the hard disk in actual use.
Example 4
On the basis of embodiment 3, in step S11, the plurality of wafers includes at least 3 wafers.
Example 5
On the basis of embodiment 3, in step S14, the set value number of times includes 1000 times.
Example 6
On the basis of embodiment 3, in step S14, the performing the corresponding function test specifically includes the sub-steps of: after being placed at the first set temperature for a set time, the data can be successfully read by performing a read operation on the data, and the first set temperature is an experience set temperature.
Example 7
On the basis of embodiment 3, in step S14, the performing the corresponding function test specifically includes the sub-steps of: and performing analog reading on all pages in the block, performing data reading on the pages, and testing whether the data can be successfully read.
Example 8
On the basis of embodiment 3, in step S14, the performing the corresponding function test specifically includes the sub-steps of: writing the first set temperature into the second set temperature for reading, writing the second set temperature into the first set temperature for reading, and testing whether the reading and writing can be successfully performed; the first set temperature and the second set temperature are experience set temperatures, and the first set temperature is higher than the second set temperature.
Example 9
On the basis of embodiment 6, the set time includes 5 hours.
Example 10
On the basis of embodiment 6, the set time includes 6 hours.
The units involved in the embodiments of the present invention may be implemented by software, or may be implemented by hardware, and the described units may also be provided in a processor. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.
According to an aspect of embodiments of the present invention, there is provided a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The computer instructions are read from the computer-readable storage medium by a processor of a computer device, and executed by the processor, cause the computer device to perform the methods provided in the various alternative implementations described above.
As another aspect, the embodiment of the present invention also provides a computer-readable medium that may be contained in the electronic device described in the above embodiment; or may exist alone without being incorporated into the electronic device. The computer-readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to implement the methods described in the above embodiments.
Claims (10)
1. The NAND Flash wear balancing method based on the life test is characterized by comprising the following steps of:
and testing the service life of each block on the grain DIE, using the test result as a reference of the maximum service life of the block, and using the ratio of the current wear times to the maximum erasable times in the wear balance design as a reference standard of the wear balance design, so that the wear ratio of all blocks is kept average, and the purpose of using the service life of the block to the maximum is achieved.
2. The method for balancing wear of NAND Flash based on life test according to claim 1, wherein the life of each block on the test DIE is used as a reference for the maximum life of each block, and in the wear balancing design, the ratio of the current number of wear times to the maximum erasable number of wear times is used as a reference standard for the wear balancing design, so that the wear ratio of all blocks is kept average to achieve the purpose of maximizing the life of each block, and the method specifically comprises the following sub-steps:
s1, predicting the service life of a NAND Flash memory block;
s2, based on different maximum erasable frequency values obtained in life prediction, the maximum erasable frequency values are used as dependent data and stored in a hard disk;
s3, after each pair of blocks of the hard disk is subjected to one-time erasing operation, recording the current erasing times;
s4, recording the ratio of the current wear times to the maximum erasable times as a wear ratio value;
s5, selecting a block with the minimum abrasion proportion value as an abrasion balance selecting block;
s6, moving the data of the blocks with the abrasion proportion smaller than the first set value to the blocks with the abrasion proportion higher than the second set value, so as to achieve the effect of abrasion balance; the first set value and the second set value are empirically chosen values, and the first set value is smaller than the second set value.
3. The method for balancing NAND Flash wear based on life test according to claim 2, wherein in step S1, the life prediction of the NAND Flash block specifically comprises the following sub-steps:
s11, selecting a plurality of wafers as test samples;
s12, testing the DIE DIE, wherein the test needs to be covered on each position of the wafer;
s13, taking blocks with the same block serial numbers on all the grains DIE as a group for abrasion;
s14, carrying out corresponding function test after the set values are worn every time;
s15, judging that the block fails if any test in the step S14 fails, and recording the erased number of times of the last successful test of the block as the maximum erasable number of times;
s16, counting the maximum erasable frequency values of all the blocks, and taking the minimum value as a new maximum erasable frequency value of the hard disk in actual use.
4. The life test-based NAND Flash wear leveling method as claimed in claim 3, wherein in step S11, the plurality of wafers includes at least 3 wafers.
5. The method for NAND Flash wear leveling based on life test as claimed in claim 3, wherein the set number of times includes 1000 times in step S14.
6. The method for balancing NAND Flash wear based on life test according to claim 3, wherein in step S14, the performing the corresponding function test specifically comprises the sub-steps of: after being placed at the first set temperature for a set time, the data can be successfully read by performing a read operation on the data, and the first set temperature is an experience set temperature.
7. The method for balancing NAND Flash wear based on life test according to claim 3, wherein in step S14, the performing the corresponding function test specifically comprises the sub-steps of: and performing analog reading on all pages in the block, performing data reading on the pages, and testing whether the data can be successfully read.
8. The method for balancing NAND Flash wear based on life test according to claim 3, wherein in step S14, the performing the corresponding function test specifically comprises the sub-steps of: writing the first set temperature into the second set temperature for reading, writing the second set temperature into the first set temperature for reading, and testing whether the reading and writing can be successfully performed; the first set temperature and the second set temperature are experience set temperatures, and the first set temperature is higher than the second set temperature.
9. The life test-based NAND Flash wear leveling method of claim 6, wherein the set time comprises 5 hours.
10. The life test-based NAND Flash wear leveling method of claim 6, wherein the set time comprises 6 hours.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364437A (en) * | 2007-08-07 | 2009-02-11 | 芯邦科技（深圳）有限公司 | Method capable of loss equalization of flash memory and application thereof |
| US20110173484A1 (en) * | 2010-01-08 | 2011-07-14 | Ocz Technology Group, Inc. | Solid-state mass storage device and method for failure anticipation |
| JP2011186554A (en) * | 2010-03-04 | 2011-09-22 | Toshiba Corp | Memory management device and method |
| US20110271030A1 (en) * | 2008-12-30 | 2011-11-03 | Massimo Iaculo | Wear Leveling For Erasable Memories |
| CN106504794A (en) * | 2015-09-04 | 2017-03-15 | Hgst荷兰公司 | Operating parameter for flash memory device |
| CN112599181A (en) * | 2020-12-11 | 2021-04-02 | 深圳市时创意电子有限公司 | Flash memory chip analysis method and device, electronic equipment and storage medium |
-
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- 2024-03-01 CN CN202410233584.0A patent/CN117809724A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364437A (en) * | 2007-08-07 | 2009-02-11 | 芯邦科技（深圳）有限公司 | Method capable of loss equalization of flash memory and application thereof |
| US20110271030A1 (en) * | 2008-12-30 | 2011-11-03 | Massimo Iaculo | Wear Leveling For Erasable Memories |
| US20110173484A1 (en) * | 2010-01-08 | 2011-07-14 | Ocz Technology Group, Inc. | Solid-state mass storage device and method for failure anticipation |
| JP2011186554A (en) * | 2010-03-04 | 2011-09-22 | Toshiba Corp | Memory management device and method |
| CN106504794A (en) * | 2015-09-04 | 2017-03-15 | Hgst荷兰公司 | Operating parameter for flash memory device |
| CN112599181A (en) * | 2020-12-11 | 2021-04-02 | 深圳市时创意电子有限公司 | Flash memory chip analysis method and device, electronic equipment and storage medium |
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