CN112599106B - Display panel, driving method thereof and display device - Google Patents
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- 238000000034 method Methods 0.000 title abstract description 10
- 239000004973 liquid crystal related substance Substances 0.000 description 31
- 239000000758 substrate Substances 0.000 description 21
- 238000010586 diagram Methods 0.000 description 9
- 239000010408 film Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 230000010287 polarization Effects 0.000 description 3
- 241001270131 Agaricus moelleri Species 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
Abstract
The application discloses a display panel, a driving method thereof and a display device; the display panel includes: the pixel structure comprises a plurality of columns of data lines, a plurality of rows of scanning lines, a pixel electrode, a plurality of reset circuits and a common electrode; the plurality of reset circuits are arranged in one-to-one correspondence with the plurality of pixel regions, and the reset circuits are connected with the pixel electrodes; wherein, the difference value between the voltage value of the reset data signal and the voltage value of the common voltage signal is a reset data signal offset value; the difference value between the voltage value of the data signal and the voltage value of the common voltage signal is a data signal offset value; if the data signal deviation value is in an interval from zero to a positive value; the reset data signal offset value is an interval from zero to a negative value; if the data signal deviation value is in an interval from zero to a negative value; the reset data signal offset value is an interval from zero to a positive value; the problem that image sticking is easily caused by positive and negative changes of the voltage on the data line is solved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device.
Background
The thin film transistor liquid crystal display (TFT-LCD) is increasingly widely used, and people have increasingly high requirements for the performance of the liquid crystal display and at the same time have increasingly strict requirements for the picture quality. The wide viewing angle, high contrast, low power consumption and fast response are the main directions for improving the performance of the display, and the liquid crystal panel generally comprises an array substrate and a color film substrate which are arranged in a box-to-box manner, and liquid crystal molecules are filled between the array substrate and the color film substrate; the array substrate comprises a substrate base plate, and a grid line and a data line which are formed on the substrate base plate, wherein the grid line and the data line are pixel units.
In general, in a liquid crystal display, since the polarity of a voltage signal applied across a liquid crystal capacitor (Clc) and a storage capacitor (Cst) must be inverted every predetermined time to prevent a liquid crystal material from being polarized and permanently damaged, it is necessary to perform polarity inversion driving on a pixel cell on an array substrate. The polarity inversion driving needs to change the positive and negative of the voltage on the data line; but the positive and negative changes in the voltage on the data lines tend to cause image sticking problems.
Disclosure of Invention
The application aims to provide a display panel, a driving method thereof and a display device, so as to solve the problem that image sticking is easily caused by positive and negative changes of voltage on a data line.
The application discloses display panel, display panel includes: the pixel structure comprises a plurality of columns of data lines, a plurality of rows of scanning lines, a pixel electrode, a plurality of reset circuits and a common electrode; the data line provides a data signal; the scanning lines provide scanning signals, and the common electrode provides a common voltage signal for the display panel; the data lines and the scanning lines are crossed to form a plurality of pixel regions; the pixel region is provided with corresponding pixel electrodes, a plurality of reset circuits are arranged in one-to-one correspondence with the pixel regions and connected with the pixel electrodes, the reset circuits provide reset data signals for the pixel electrodes, and the reset circuits are controlled to be started by reset control signals;
wherein, the difference value between the voltage value of the reset data signal and the voltage value of the common voltage signal is a reset data signal offset value; the difference value between the voltage value of the data signal and the voltage value of the common voltage signal is a data signal offset value; if the data signal deviation value is an interval from zero to a positive value; the reset data signal offset value is an interval from zero to a negative value; if the data signal deviation value is in an interval from zero to a negative value; the reset data signal offset value is in the interval from zero to a positive value.
Optionally, the display panel further includes a plurality of pixel active switches, and the pixel active switches are arranged in one-to-one correspondence with the plurality of pixel regions, gates of the plurality of pixel active switches in a current row are connected to the corresponding scan lines, and sources of the plurality of pixel active switches in a current column are connected to the corresponding data lines; the reset circuit comprises a reset active switch, the source electrode of the reset active switch is connected to the pixel electrode, the reset data signal is provided to the drain electrode of the reset active switch, and the grid electrode of the reset active switch is connected to a reset control signal; the reset control signal is a scanning signal.
Optionally, in each pixel region corresponding to the current row of scanning lines, the gate of the corresponding reset active switch is connected to the previous row of scanning lines; the grid electrode of the pixel active switch is connected to the current row scanning line; the reset control signal is a scanning signal of a previous scanning line.
Optionally, the current row of scanning line is an nth row of scanning line, in an n row of pixel region, a gate of the corresponding reset active switch is connected to the nth-2 row of scanning line, and a gate of the pixel active switch is connected to the nth row of scanning line; the reset control signal is a scanning signal of an n-2 th row of scanning lines, and n is an integer larger than 2.
Optionally, the source of the reset active switch is connected to the common electrode, and the reset data signal is a common voltage signal of the common electrode.
Optionally, the display panel further includes a plurality of reset data signal lines, the data signal lines are parallel to the data lines, and the reset data signal lines are externally connected to a timing controller.
The application also discloses a driving method of the display panel, which comprises the following steps:
providing a common voltage signal to a common electrode of the display panel;
providing a reset data signal to the pixel electrode at a time t1 before the scanning signal of the current row of scanning lines is turned on; and closing the reset data signal at time t2 before the scan signal of the scan line is turned on;
starting at t3 moment when the scanning signal of the current row of scanning line is started, and transmitting the data signal to the pixel electrode for displaying;
wherein t1 is more than t2 and is more than or equal to t 3; the difference value between the voltage value of the reset data signal and the voltage value of the common voltage signal is a reset data signal offset value; the difference value between the voltage value of the data signal and the voltage value of the common voltage signal is a data signal offset value; if the data signal deviation value is an interval from zero to a positive value; the reset data signal offset value is an interval from zero to a negative value; if the data signal deviation value is in an interval from zero to a negative value; the reset data signal offset value is in the interval from zero to a positive value.
Optionally, the difference between t2 and t1 is equal to the row on time of the scanning signal of the current row scanning line; t3= t 2.
Optionally, the difference between t2 and t1 is equal to twice the row on time of the scan signal of the current row scan line; the values of t3-t2 are equal to the row on time of the scan signal of the current row scan line.
The application also discloses a display device, including foretell display panel and for display panel provides the backlight unit of light source.
Compared with the technical scheme of the exemplary dot inversion, the display panel of the application is provided with the reset circuit which can be independently controlled relative to the active switch of the pixel for displaying in the display panel, so that the reset data signal can be provided to the pixel electrode before the scanning line of the current row of each frame is turned on, and the voltage difference between the pixel electrode and the common electrode is the offset value of the reset data signal at the current time t 2; at the moment t3, when the scan line is opened, a data signal is input to the pixel electrode, that is, under the condition of normal display, the voltage difference between the pixel electrode and the common electrode is a data signal offset value, and the common electrode and the pixel electrode drive liquid crystal molecules to deflect together; and the polarity of the reset data signal offset value is opposite to that of the data signal offset value, namely after the reset circuit of each frame is started, the reset data signal is assigned to the pixel electrode, so that the polarity of the voltage between the pixel electrode and the common electrode is reversed, the deviation of the corresponding liquid crystal molecules is reversed, and one-time polarity reversal is realized. Compared with the technical scheme of dot inversion, the voltage of the data signal is inverted from positive to negative or from negative to positive, the data signal can be constantly positive or constantly negative, and the positive and negative data signals are not required to be input when different scanning lines are started, so that the power consumption is saved, and the problem of image sticking caused by positive and negative changes of the data signal is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic view of a display device according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a display panel according to an embodiment of the present application;
FIG. 3 is a schematic view of a display panel according to an embodiment of the present application;
FIG. 4 is a schematic diagram of pixel active switching and reset circuitry within a pixel area according to one embodiment of the present application;
FIG. 5 is a schematic diagram of pixel active switches and reset active switches within a pixel area of another embodiment of the present application;
FIG. 6 is a timing diagram of a reset control signal, a data signal and a scan line according to an embodiment of the present application;
FIG. 7 is a diagram illustrating timing of a reset control signal, a data signal, and a scan line according to another embodiment of the present application;
FIG. 8 is a schematic view of a display panel according to another embodiment of the present application;
FIG. 9 is an enlarged schematic view of a pixel region of FIG. 7 of the present application;
fig. 10 is a schematic view of a display panel according to another embodiment of the present application;
fig. 11 is a schematic diagram of a driving method of a display panel according to an embodiment of the present application.
10, a display panel; 100. an array substrate; 110. a scan driving circuit; 111. scanning a line; 120. a data driving circuit; 121. a data line; 130. a pixel active switch; 140. a pixel region; 150. a pixel electrode; 160. a reset circuit; 161. resetting the active switch; 170. a reset control drive circuit; 171. a reset control signal line; 180. a reset data driving circuit; 182. resetting the data signal; 190. a common line; 200. a color film substrate; 210. a common electrode; 300. and (3) liquid crystals.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
Common polarity reversals include: frame inversion, column inversion, row inversion, and dot inversion. If the polarities of the voltages stored in the pixel units in the entire frame are the same and the polarities of the voltages are all positive or all negative before the writing of the next frame is finished in the previous frame, the frame inversion is called; if the polarities of the voltages stored in the pixel units on the same row are the same and the polarities of the voltages stored in the pixel units on the left and right adjacent rows are opposite, the inversion is called row inversion; if the polarities of the voltages stored in the pixel units on the same row are the same and the polarities of the voltages stored in the pixel units on the upper and lower adjacent rows are opposite, the inversion is called row inversion; if the polarity of the voltage stored in each pixel unit is opposite to the polarity of the voltage stored in the pixel units adjacent to the pixel units, it is called dot inversion. In order to improve the quality of the whole display screen, the dot inversion driving method of the pixel unit has become the mainstream display driving method at present. However, the present application provides a new polarity inversion implementation, which requires positive and negative changes in the voltage on the data line 121, and the positive and negative changes in the voltage on the data line 121 are likely to cause image sticking.
The present application is described in detail below with reference to the figures and alternative embodiments.
As shown in fig. 1 to 3, as an embodiment of the present application, a display device is disclosed, which includes a display panel 10 and a backlight module providing a light source for the display panel 10. Wherein the display panel 10 includes: the liquid crystal display panel comprises an array substrate 100 and a color film substrate 200, wherein a liquid crystal 300 is arranged between the array substrate 100 and the color film substrate 200, and the array substrate 100 is provided with a plurality of rows of data lines 121, a plurality of rows of scanning lines 111, a plurality of pixel active switches 130, a pixel electrode 150 and a plurality of reset circuits 160; a common electrode 210 is arranged on the color film substrate 200; the common electrode 210 and the pixel electrode 150 drive the liquid crystal 300 molecules to deflect together.
Fig. 4 shows a schematic diagram of the pixel active switch 130 and the reset circuit 160 in one pixel region 140; the data line 121 supplies a data signal; the scan lines 111 provide scan signals, and the common electrode 210 provides common voltage signals for the display panel 10; the data lines 121 and the scanning lines 111 intersect to form the plurality of pixel regions 140; the pixel active switches 130 and the pixel regions 140 are arranged in a one-to-one correspondence, a gate of the pixel active switch 130 is connected to the scan line 111 of the current row, and a source of the pixel active switch 130 is connected to the data line 121 of the current column; the pixel electrode 150 is disposed in the pixel region 140 and connected to the drain of the corresponding pixel active switch 130; a plurality of reset circuits 160 are disposed in one-to-one correspondence with the plurality of pixel regions 140, and are connected to the pixel electrodes 150, and the reset circuits provide a reset data signal to the pixel electrodes;
wherein, the difference value between the voltage value of the reset data signal and the voltage value of the common voltage signal is a reset data signal offset value; the difference value of the voltage value of the data signal and the voltage value of the public voltage signal is a data signal offset value; if the data signal deviation value is an interval from zero to a positive value; the reset data signal offset value is an interval from zero to a negative value; if the data signal deviation value is in an interval from zero to a negative value; the reset data signal offset value is in the interval from zero to a positive value.
Compared with the technical scheme of the exemplary dot inversion, the display panel of the application is provided with the reset circuit which can be independently controlled relative to the active switch of the pixel for displaying in the display panel, the reset circuit 160 is turned on at the time t1 before the scanning signal of the current row scanning line 111 is turned on to provide the reset data signal for the pixel electrode 150, the reset circuit 160 is turned off at the time t2 before the scanning signal of the current row scanning line 111 is turned on, the scanning signal of the current row scanning line 111 is turned on at the time t3, and t1 < t2 is less than or equal to t 3; so that the reset data signal can be supplied to the pixel electrode 150 before the scan line 111 of the current row of each frame is turned on, so that the voltage difference between the pixel electrode 150 and the common electrode 210 at the current time t2 is the reset data signal offset value; at the time t3, when the scan line 111 is turned on, a data signal is input to the pixel electrode 150, that is, under the normal display condition, the voltage difference between the pixel electrode 150 and the common electrode 210 is a data signal offset value, and the common electrode 210 and the pixel electrode 150 drive the liquid crystal 300 molecules to deflect together; the polarity of the reset data signal offset value is opposite to that of the data signal offset value, that is, after the reset circuit 160 of each frame is turned on, the reset data signal is assigned to the pixel electrode, so that the polarity of the voltage between the pixel electrode 150 and the common electrode 210 is inverted, and the bias of the corresponding liquid crystal 300 molecule is inverted, thereby implementing one polarity inversion. Compared with the exemplary dot inversion technical scheme, the voltage of the data signal is inverted from positive to negative or from negative to positive, the data signal can be constantly positive or constantly negative, and the positive and negative data signals are not required to be input when the scanning lines 111 on different rows are opened, so that the power consumption is saved, and the problem of image retention caused by positive and negative changes of the data signal is solved.
As shown in fig. 5, which illustrates a schematic diagram of the pixel active switch 130 and the reset active switch 161 of the present application, the reset circuit 160 of the present application includes a reset active switch 161, a source of the reset active switch 161 is connected to the pixel electrode 150, the reset data signal is provided to a drain of the reset active switch 161, and a gate of the reset active switch 161 is connected to a reset control signal; the reset control signal controls the reset active switch 161 to be turned on at the time t1 and turned off at the time t 2; the present application provides a reset active switch 161 corresponding to each pixel region 140, and the reset active switch 161 provides a reset data signal to the pixel electrode 150 when turned on. The reset control signal controls the reset active switch 161 to be turned on at time t1 and turned off at time t2, and time t1 and time t2 of the present application can be selected according to actual situations, and the following are respectively deployed:
in one embodiment, the time T1 to the time T2 is a row on time before the current row of scan lines 111 is turned on, and T2= T3, where the row on time T is a time when the row of scan lines 111 is turned on, i.e., is earlier than the row on time, the reset active switch 161 is turned on, and the reset data signal is transmitted to the pixel electrode 150; after the current scan line 111 is turned on, the pixel active switch 130 is turned on to transmit the data signal to the pixel electrode 150; the gate of the corresponding reset active switch 161 is connected to the previous scan line 111, and the previous scan line 111 is earlier than the current scan line 111 by one row on time. That is, the reset active switch 161 in the newly added reset circuit 160 is controlled by the previous scanning line 111, and the basic scanning line 111 architecture in the display panel 10 is directly utilized to implement the function of resetting the data signal without providing a new control circuit; in addition, the reset data signal in this embodiment is provided only during a row turn-on time before the current row scanning line 111 is turned on, that is, during a frame time, after the pixel electrode 150 corresponding to the current row scanning line 111 is charged, before the next frame scanning is turned on, before each row scanning line 111 is scanned line by line, the pixel electrode 150 corresponding to each row scanning line 111 is connected to the reset data signal line by line, and is reset, that is, the polarity of the liquid crystal 300 is reversed; the corresponding timing sequence is shown in fig. 6, where inversion is a reset control signal, and n is the nth row pixel region 140, the nth row pixel active switch 130, or the nth row reset active switch 161; the same row of scanning lines 111, after the scanning of the previous frame is finished, the display panel 10 displays according to the data signal, and at the line turn-on time before the scanning of the next frame is started, the display panel 10 reverses the polarity of the voltage between the pixel electrode and the common electrode according to the reset data signal, so that the corresponding liquid crystal 300 is reversely deflected.
In another embodiment, the time t1 to the time t2 is a row on time before the current row scanning line 111 is turned on, and the time t2 to the time t3 is also a row on time, that is, before the current row scanning line 111 is turned on, two row on times are advanced, the reset active switch 161 is turned on, and the reset data signal is transmitted to the pixel electrode 150; after the current scan line 111 is turned on, the pixel active switch 130 is turned on to transmit the data signal to the pixel electrode 150; taking the current row scanning line 111 as the nth row scanning line 111, in the n rows of pixel regions 140, the gate of the corresponding reset active switch 161 is connected to the nth-2 row scanning line 111, and the gate of the pixel active switch 130 is connected to the nth row scanning line 111; the reset control signal is a scanning signal of the scanning line 111 of the (n-2) th row. The gate of the corresponding reset active switch 161 is connected to the upper scan line 111, and the upper scan line 111 is two lines of turn-on time earlier than the turn-on time of the current scan line 111; the corresponding timing is shown in fig. 7. Compared with the previous embodiment, in the present embodiment, the on time of the reset active switch 161 corresponding to the reset data signal is advanced by two line on times, so that the current line scan line 111 is turned on after the reset active switch 161 is turned off, thereby preventing signal delay, and before the reset active switch 161 is not turned off, the pixel active switch 130 is already turned on, which causes insufficient charging of the pixel electrode 150, and causes problems such as color difference.
In both embodiments, the gate of the reset active switch 161 is connected to the corresponding scan line 111, and correspondingly, the gate of the reset active switch 161 corresponding to the first row of pixel regions 140 may be connected to the last row of scan line 111, or the scan signal of the last row of scan line 111 may be transmitted to another twin scan line 111, the twin scan line 111 is disposed on the side of the first row of scan line 111 away from the second row of scan line 111, and the gate of the first row of reset active switch 161 may be connected to the twin scan line 111.
In addition, the present embodiment provides another timing for resetting the active switch 161 to be turned on, which is as follows: the reset control signal lines 171 are lines corresponding to the scan lines 111 one by one, and can provide reset control signals similar to the scan signals to the reset active switches 161 to realize the line-by-line opening of the reset active switches 161, so that only the liquid crystal 300 molecules corresponding to one row of the pixel regions 140 are refreshed in each line of the opening time, thereby realizing the line-by-line refreshing.
Specifically, fig. 8 to 9 show schematic diagrams of a scan driving circuit 110 and a reset control driving circuit 170; the display panel 10 includes: a scan driving circuit 110, wherein the scan driving circuit 110 is connected to the scan line 111 and provides a scan signal for the scan line 111; a reset control driving circuit 170, wherein the reset control driving circuit 170 is connected to the reset control signal line 171, and provides a reset control signal for the reset control signal line 171; the scan driving circuit 110 and the reset control driving circuit 170 are disposed at different sides of the display panel 10. Correspondingly, the scan driving circuit 110 outputs the scan signal to the corresponding pixel active switch 130 from the left side, the reset control driving circuit 170 outputs the reset control signal to the corresponding reset active switch 161 from the right side, the scan driving circuit 110 and the reset driving circuit do not interfere with each other, for the small-sized high-refresh liquid crystal 300 display panel 10, when no more wiring space can be loaded on one side of the display panel 10, the scan driving circuit 110 and the reset control driving circuit 170 are arranged on different sides of the display panel 10, and the reset control is realized without affecting the normal scan driving circuit 110 of the display panel 10, and the display effect of high refresh is not affected. The relationship between the turn-on time t1, t2 of each row of the reset control driving circuit 170 and the turn-on time t3 of each row of the scan driving circuit 110 is not affected by the turn-on time of each row of the scan signal, i.e. the row turn-on time; i.e. t2-t1, the on time of the reset control signal of each row may be equal to half of the row on time, or may be equal to one row on time, and may be specifically selected according to actual situations.
As shown in fig. 10, the scan driving circuit 110 and the reset control driving circuit 170 according to another embodiment of the present application, the display panel 10 includes: two scan driving circuits 110 and two reset control driving circuits 170; the two scan driving circuits 110 are respectively disposed at two sides of the display panel 10, and the two scan driving circuits 110 are respectively connected to two ends of the scan line 111 and provide scan signals for the scan line 111; the two reset control driving circuits 170 are respectively disposed at two sides of the display panel 10, and the two reset control driving circuits 170 are respectively connected to two ends of the reset control signal line 171 and simultaneously provide a reset control signal for the reset control signal line 171. For a large-sized display panel 10, the wiring space is large, and the scan driving circuit 110 and the reset control driving circuit 170 may be simultaneously disposed on both sides of the display panel 10, which is suitable for different display panels 10.
The reset control signal lines 171 of the reset control driving circuit 170 and the scanning lines 111 of the scanning driving circuit 110 may be stacked or may be provided in the same layer. Specifically, the reset control signal line 171 and the scan line 111 are formed in the same layer, and the reset control signal line 171 and the scan line 111 are disposed at an interval. The reset control signal lines 171 are arranged one by one at intervals of the scanning lines 111, and in this way, the reset control signal lines 171 arranged at intervals on the same layer as the scanning lines 111 can be etched when the metal layer of the scanning lines 111 is etched only by changing the original mask. And the reset active switch 161 and the pixel active switch 130 are also formed in the same layer, and only the mask needs to be changed without increasing the manufacturing process, and the manufacturing process of other structures in the display panel 10 is not affected.
However, the arrangement in the same layer has a certain influence on the aperture ratio, and in order to seek a high aperture ratio, the reset control signal line 171 and the scanning line 111 are stacked, specifically, they may be completely overlapped or partially overlapped, the complete overlapping increases the aperture ratio of the display panel 10 to a certain extent, and the partial overlapping reduces the load between the scanning line 111 and the reset control signal line 171. The selection can be made by those skilled in the art according to the actual situation.
In light of the above, the manner of providing the reset data signal in the present application is specifically developed as follows:
in one embodiment, the reset data signal is a common voltage signal, and the drain of the reset active switch 161 is connected to the common electrode 210. The drain of the reset active switch 161 may be connected to the common electrode 210 through a connection line between the array substrate 100 and the color filter substrate 200, in another embodiment, in each pixel region 140, the drain of the corresponding reset active switch 161 is directly connected to the common line of the array substrate 100, and generally, the common line of the array substrate 100 and the common electrode 210 of the color filter substrate 200 are connected together, so in this embodiment, the drain of the reset active switch 161 may be directly connected to the common line, during the on time of the reset active switch 161, the common electrode 210 provides a common voltage signal to the pixel electrode 150, so that the voltage difference between the pixel electrode 150 and the common electrode 210 is zero, that is, the capacitance between the current pixel electrode 150 and the common line is released, so that the pixel unit discharge is completed, and the molecules of the liquid crystal 300 recover to the natural state under the condition of the zero voltage difference, after the next frame is charged, the liquid crystal 300 molecules are deflected again, preventing the polarization effect of the liquid crystal 300 molecules under a certain voltage difference for a long time.
Different from the previous embodiment, the present application may further provide reset data signal lines similar to the data lines 121 in direction and arrangement, the display panel 10 further includes a plurality of reset data signal lines, the data signal lines are parallel to the data lines 121, and a timing controller is connected to the reset data signal lines. A reset data signal is provided by the timing controller, where the reset data signal may be a fixed value or a variable value. The fixed value is that before the next frame is charged, the molecules of the liquid crystal 300 are deflected to the fixed differential pressure position, and the fixed differential pressure position can cause the situation that the absolute value of the data voltage deviant in the display time period is unequal to the absolute value of the reset data signal deviant in the refresh time period, and the situation that the gray scale in the refresh time period is different from the gray scale in the display time period, although the time is extremely short, the display panel 10 which has low requirements for some low-brush applications has almost no influence, and a better display effect is sought, and the changed reset data signal can be selected.
In the following embodiments, the reset data signal offset value is a fixed value, and a specific value is selected according to the data signal offset value, and the following is a specific embodiment of the present application:
in an embodiment, the reset data signal offset value is equal to the absolute value of the maximum value of the data signal offset values. The maximum value of the data signal offset value is the maximum voltage difference between the pixel electrode 150 and the common electrode 210, that is, the maximum deflection angle of the liquid crystal 300 molecules, and after the display period in each frame is completed, the liquid crystal 300 molecules are applied with the reverse maximum voltage, so that the liquid crystal 300 molecules are deflected to the reverse maximum gray scale value no matter how many gray scale values the display period is, for example, when the current pixel region 140 is 160 gray scales in the display period, the current pixel region is-255 gray scales in the reset period, and the reverse deflection is performed, so that the liquid crystal 300 molecules can be refreshed in each frame, and polarization is prevented; according to the principle that the scanning lines 111 are opened line by line, the reset data signals are also opened and reset line by line through the reset control signals, therefore, in each frame, the whole frame is refreshed line by line from top to bottom, and not at the same time point, the pixel areas 140 in each line are reset and refreshed, so that strong human eye reaction is caused, the pixel areas 140 in the scheme are refreshed line by line, and the effect on the displayed image is lower. It should be noted that: the display time interval is the input of the scanning signal of the current frame, before the reset control signal of the current frame is input, the reset time interval is the input of the reset control signal before the scanning signal of the next frame is input; the time t3 corresponding to the scanning line of the first row of the current frame to the time t3 of the next frame is one frame, and the polarity of the voltage difference between the pixel electrode and the common electrode in the display period is opposite to the polarity of the voltage difference between the pixel electrode and the common electrode in the reset period.
Specifically, when the data signal is in a voltage value range of 0-7V, the voltage value Vcom of the common voltage signal is in a range of [0V, 1V ]; the range of the reset data signal offset value is any value of [0V, 7V ], and the range of the data signal offset value is [ -7V, 0V ]; or the reset data signal offset value ranges from any one of [ -7V, 0V ], and the data signal offset value ranges from [0V, 7V ]. For example, the voltage value of the common voltage signal is 0V, the reset data signal is 7V, and the data signal is-7V-0V, wherein the offset value of the reset data signal is 7, and the maximum value of the offset value of the data signal is 7; the voltage of the common voltage signal in this embodiment is low, and the voltage values of the data signal and the reset data signal are also low, which has the effect of low power consumption. Conversely, the voltage value of the common voltage signal is 0V, the reset data signal is-7V, and the data signal is 0V-7V, wherein the offset value of the reset data signal is 7, and the maximum value of the offset value of the data signal is 7; suitable for a display panel 10 with a low refresh rate and low power consumption.
Of course, it is also possible that the reset data signal offset value ranges from any value of [0V, 7V ] such that the absolute value of the reset data signal offset value is not equal to the maximum value of the data signal offset values, for example: the voltage value of the public voltage signal is 0V, the reset data signal is 0V, the data signal is 0V-7V, wherein the offset value of the reset data signal is 0, and the offset value of the data signal is 7; at this time, the offset value of the reset data signal is 0, that is, in the reset period, the molecules of the liquid crystal 300 are restored to the natural state, and the natural state can also avoid the occurrence of polarization; before the next frame is charged, the residual capacity of the previous frame of the pixel electrode 150 is completely released, so that the pixel capacitor is ensured not to have the residual capacity of the previous frame, the next frame is charged more accurately, and the charging capacity of the current frame cannot be influenced by the residual capacity of the previous frame.
In another embodiment, when the data signal takes on a value within a voltage range of 7-14V, such as a high refresh display panel 10, a higher data signal voltage is required; specifically, the voltage value Vcom of the common voltage signal is in a range of [6V, 8V ] or [ -8V, -6V ]; the range of the reset data signal offset value is any value of [0V, 7V ], and the range of the data signal offset value is [ -7V, 0V ]; or the range of the offset value of the reset data signal is any value of [ -7V, 0V ], the range of the offset value of the data signal is [0V, 7V ], wherein the reset data signal can select 0V or 14V. For example, the voltage value Vcom of the common voltage signal is 7V, the voltage value range of the data signal is [7V, 14V ], and the voltage value of the reset data signal is 0V. Power consumption is lower when the voltage value of the reset data signal takes 0V, compared to when the voltage value of the reset data signal takes 14V.
As shown in fig. 11, a driving method of a display panel includes the steps of:
s1: providing a common voltage signal to a common electrode of the display panel;
s2: providing a reset data signal to the pixel electrode at a time t1 before the scanning signal of the current row of scanning lines is turned on; and closing the reset data signal at time t2 before the scan signal of the scan line is turned on;
s3: starting at a scanning signal of a current row of scanning lines at a time t3, and transmitting a data signal to a pixel electrode for displaying;
wherein t1 is more than t2 and is more than or equal to t 3; the difference value between the voltage value of the reset data signal and the voltage value of the common voltage signal is a reset data signal offset value; the difference value between the voltage value of the data signal and the voltage value of the common voltage signal is a data signal offset value; if the data signal deviation value is an interval from zero to a positive value; the reset data signal offset value is an interval from zero to a negative value; if the data signal deviation value is in an interval from zero to a negative value; the reset data signal offset value is in the interval from zero to a positive value.
Before the scanning line of the current row of each frame is started, a reset data signal is supplied to the pixel electrode, so that the voltage difference between the pixel electrode and the common electrode is a reset data signal offset value at the current time t 2; at the moment t3, when the scan line is opened, a data signal is input to the pixel electrode, that is, under the condition of normal display, the voltage difference between the pixel electrode and the common electrode is a data signal offset value, and the common electrode and the pixel electrode drive liquid crystal molecules to deflect together; and the polarity of the reset data signal offset value is opposite to that of the data signal offset value, namely after the reset circuit of each frame is started, the reset data signal is assigned to the pixel electrode, so that the polarity of the voltage between the pixel electrode and the common electrode is reversed, the deviation of the corresponding liquid crystal molecules is reversed, and one-time polarity reversal is realized. Compared with the technical scheme of the exemplary dot inversion, the voltage of the data signal is inverted from positive to negative or from negative to positive, the data signal can be constantly positive or constantly negative, and the positive and negative data signals are not required to be input when the scanning lines of different rows are started, so that the power consumption is saved, and the problem of image retention caused by positive and negative changes of the data signal is solved.
Specifically, the value of t2-t1 is equal to the row on time of the scanning signal of the current row scanning line; t3= t 2. The reset active switch is turned on and the reset data signal is transmitted to the pixel electrode one row opening time in advance; after the current scanning line is started, a pixel active switch is turned on, and a data signal is transmitted to a pixel electrode; the grid electrode of the corresponding reset active switch is connected to the last row of scanning lines, and the last row of scanning lines is earlier than the starting time of the current row of scanning lines by one row starting time. The reset active switch in the newly added reset circuit is controlled by the scanning line in the previous line, a new control line is not needed, and the function of resetting the data signal is realized by directly utilizing the framework of the basic scanning line in the display panel; in this embodiment, the reset data signal is provided only during a row on time before the current row scan line is turned on, that is, during a frame time, after the pixel electrode corresponding to the current row scan line is charged, before the next frame scan is turned on, and before each row scan line is scanned line by line, the pixel electrode corresponding to each row scan line is connected to the reset data signal line by line, and the reset data signal is reset, that is, the liquid crystal is subjected to polarity inversion
In another embodiment, the value of t2-t1 is equal to twice the row on time of the scan signal of the current row scan line; the values of t3-t2 are equal to the row on time of the scan signal of the current row scan line. Compared with the previous embodiment, the embodiment advances the turn-on time of the reset active switch corresponding to the reset data signal by two line turn-on times, so that the current line scan line is turned on after the reset active switch is turned off by one line turn-on time, thereby preventing signal delay.
It should be noted that, the limitations of each step in the present disclosure are not considered to limit the order of the steps without affecting the implementation of the specific embodiments, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all the steps should be considered as belonging to the protection scope of the present application.
The technical solution of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panel, and the above solution can be applied thereto.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (7)
1. A display panel, comprising:
a plurality of rows of data lines for providing data signals;
the scanning line, provide the scanning signal, the said data link crosses and forms a plurality of pixel areas with the scanning line;
the pixel active switches are arranged in one-to-one correspondence with the pixel regions, the grid electrodes of the pixel active switches are connected to the scanning lines of the current row, and the source electrodes of the pixel active switches are connected to the data lines of the current column;
the pixel area is provided with a corresponding pixel electrode, and the pixel electrode is connected with the drain electrode of the pixel active switch;
the reset circuits are arranged in one-to-one correspondence with the pixel regions, are connected with the pixel electrodes, and provide a reset data signal for the pixel electrodes; and
a common electrode for providing a common voltage signal to the display panel;
wherein, the difference value between the voltage value of the reset data signal and the voltage value of the common voltage signal is a reset data signal offset value;
the difference value between the voltage value of the data signal and the voltage value of the common voltage signal is a data signal offset value;
if the data signal deviation value is in an interval from zero to a positive value; the offset value of the reset data signal is any fixed value in a range from zero to a negative value;
if the data signal deviation value is in an interval from zero to a negative value; the offset value of the reset data signal is any fixed value in the interval from zero to a positive value;
wherein the data signal offset value is constantly a positive value or constantly a negative value;
the reset circuit comprises a reset active switch, the source electrode of the reset active switch is connected to the pixel electrode, and the grid electrode of the reset active switch is connected to a reset control signal; the reset control signal controls the reset active switch to be turned on at the time t1 before the scanning line scanning signal of the current row is turned on, and to be turned off at the time t2 before the scanning line scanning signal of the current row is turned on, the scanning signal of the scanning line of the current row is turned on at the time t3, and t1 is more than t2 and is less than or equal to t 3;
the reset data signal is a common voltage signal, the drain electrode of the reset active switch is connected to the common electrode, and when the reset active switch is turned on, the reset data signal is provided for the pixel electrode.
2. A display panel as claimed in claim 1 characterized in that the reset data signal offset value is equal to the absolute value of the maximum value of the data signal offset values.
3. The display panel according to claim 1, wherein the voltage value Vcom of the common voltage signal is in a range of [0V, 1V ];
the range of the reset data signal offset value is any value of [0V, 7V ], and the range of the data signal offset value is [ -7V, 0V ]; or the reset data signal offset value ranges from any one of [ -7V, 0V ], and the data signal offset value ranges from [0V, 7V ].
4. A display panel as claimed in claim 1, characterized in that the voltage value Vcom of the common voltage signal is in the range of [6V, 8V ] or [ -8V, -6V ];
the range of the reset data signal offset value is any value of [0V, 7V ], and the range of the data signal offset value is [ -7V, 0V ]; or the reset data signal offset value ranges from any one of [ -7V, 0V ], and the data signal offset value ranges from [0V, 7V ].
5. A display panel according to claim 4, wherein the voltage value Vcom of the common voltage signal is 7V, the voltage value of the data signal is in a range of [7V, 14V ], and the voltage value of the reset data signal is 0V.
6. The display panel according to claim 1, wherein in each pixel region corresponding to a scan line of a current row, a gate of the corresponding reset active switch is connected to the scan line of a previous row; the grid electrode of the pixel active switch is connected to the scanning line of the current row; the reset control signal is a scanning signal of the scanning line in the previous row.
7. A display device comprising the display panel according to any one of claims 1 to 6 and a backlight module for providing a light source to the display panel.
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| CA2302230C (en) * | 1997-09-04 | 2004-11-16 | Silicon Image, Inc. | Power saving circuit and method for driving an active matrix display |
| JP3713922B2 (en) * | 1997-10-30 | 2005-11-09 | セイコーエプソン株式会社 | Driving device for liquid crystal display device, liquid crystal display device, electronic apparatus, and driving method for liquid crystal display device |
| SG119173A1 (en) * | 1999-07-08 | 2006-02-28 | Nichia Corp | Image display apparatus and its method of operation |
| JP3750722B2 (en) * | 2000-06-06 | 2006-03-01 | セイコーエプソン株式会社 | Liquid crystal device, driving device and driving method thereof, and electronic apparatus |
| JP4103425B2 (en) * | 2002-03-28 | 2008-06-18 | セイコーエプソン株式会社 | Electro-optical device, electronic apparatus, and projection display device |
| JP3799307B2 (en) * | 2002-07-25 | 2006-07-19 | Ｎｅｃ液晶テクノロジー株式会社 | Liquid crystal display device and driving method thereof |
| KR101166824B1 (en) * | 2004-09-30 | 2012-07-19 | 엘지디스플레이 주식회사 | A electro-Luminescence display device and a method for driving the same |
| JP2007093660A (en) * | 2005-09-27 | 2007-04-12 | Hitachi Displays Ltd | Display device |
| KR101245944B1 (en) * | 2006-05-10 | 2013-03-21 | 엘지디스플레이 주식회사 | Liquid crystal display device and driving method thereof |
| CN102608818B (en) * | 2012-04-01 | 2014-07-30 | 友达光电（苏州）有限公司 | Liquid crystal display panel and display drive method |
| WO2014041965A1 (en) * | 2012-09-11 | 2014-03-20 | シャープ株式会社 | Display device, and driving circuit and driving method therefor |
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