WO2014041965A1

WO2014041965A1 - Display device, and driving circuit and driving method therefor

Info

Publication number: WO2014041965A1
Application number: PCT/JP2013/072175
Authority: WO
Inventors: 田中　学
Original assignee: シャープ株式会社
Priority date: 2012-09-11
Filing date: 2013-08-20
Publication date: 2014-03-20

Abstract

Provided are an active matrix type display device and so forth capable of performing a correct AC drive even when a scanning direction corresponding to the selection order for gate lines changes. In a display device wherein gate lines (GL0 to GLN) are driven such that the activated periods in mutually adjoining gate lines (GLi-1, GLi) are partially overlapped with each other, the values of a first counter voltage (VcomA) for forward scanning and a second counter voltage (VcomB) for backward scanning are set taking into consideration the difference in the magnitude of pull-in voltage in a pixel voltage (Vp) in accordance with the scanning direction (selection order for the gate lines). A common electrode driving circuit (500) switches the counter voltage applied to a common electrode (COM) of a liquid crystal panel (100) between the first counter voltage (VcomA) and the second counter voltage (VcomB) in accordance with the scanning direction on the basis of a direction designation signal (Cud) for designating the scanning direction.

Description

Display device, driving circuit and driving method thereof

The present invention relates to a display device such as an active matrix type liquid crystal display device having a plurality of scanning signal lines and a plurality of data signal lines crossing the scanning signal lines. More specifically, the selection order of the plurality of scanning signal lines, that is, the scanning direction. The present invention relates to an active matrix display device capable of switching between the two, a driving circuit and a driving method thereof.

An active matrix liquid crystal display device is arranged in a matrix corresponding to a plurality of data signal lines, a plurality of scanning signal lines intersecting with the data signal lines, the plurality of data signal lines and the plurality of scanning signal lines. A plurality of pixel formation portions are provided, and each pixel formation portion includes a pixel capacitor and a switching element. Here, as the switching element, a thin film transistor (hereinafter referred to as “TFT”) is usually used. The pixel capacitance in each pixel formation portion is formed by a pixel electrode and a common electrode (also referred to as “counter electrode”) opposite to the pixel electrode with the liquid crystal in between, and the pixel electrode serves as the switching element. The corresponding data signal line is connected through the TFT, and the corresponding scanning signal line is connected to the gate terminal of the TFT.

In the liquid crystal display device, AC driving is performed to prevent deterioration of the liquid crystal. That is, in order to make the voltage applied to the liquid crystal alternating, a positive voltage and a negative voltage are alternately applied to the pixel electrode with reference to the voltage applied to the common electrode. These positive voltage and negative voltage constitute a data signal to be applied to each data signal line. Therefore, a voltage corresponding to the center value of the data signal may be applied to the common electrode.

However, when the TFT as a switching element in each pixel formation portion transitions from the ON state to the OFF state, the voltage change of the corresponding scanning signal line (change from the gate voltage Von for turning on the TFT to the voltage Voff for turning off the TFT) ) Affects the voltage of the pixel electrode through the parasitic capacitance. That is, for example, when the TFT as the switching element is an N-channel type, the voltage applied to the pixel electrode when the TFT is in the ON state decreases by ΔVp when the TFT transitions from the ON state to the OFF state. . This voltage ΔVp (> 0) is called “push-down voltage”, “pull-in voltage”, “field-through voltage” or the like. In the liquid crystal display device, a voltage to be applied to the common electrode (hereinafter referred to as “opposite voltage”, hereinafter referred to as “opposite DC voltage” since it is assumed to be a DC voltage) is to change the voltage applied to the liquid crystal to AC, It is determined in consideration of such a pull-in voltage ΔVp.

As an invention related to the problem that the voltage change of other signal lines affects the voltage of the pixel electrode due to the parasitic capacitance, Japanese Patent Application Laid-Open No. 2009-58595 is a case where there is an inter-pixel parasitic capacitance. However, an invention of an active matrix display device that can improve image quality is described. In the present invention, the driving of the scanning signal line is devised so that the influence of the inter-pixel parasitic capacitance is suppressed.

Japanese Patent Laid-Open No. 2009-25667 also outputs to the data bus line according to the detection result of the panel temperature by the temperature detecting means for the purpose of setting the counter voltage to an optimum value even if the panel temperature fluctuates. A liquid crystal display device having a voltage level median value setting means for setting a median value of a range of voltage levels of a data signal is disclosed.

Japanese Unexamined Patent Publication No. 2009-58595 Japanese Unexamined Patent Publication No. 2009-25667

In an active matrix display device, the scanning signal line scanning direction (scanning) is used for the purpose of, for example, displaying an image with the correct orientation to the viewer even when the screen is arranged upside down. The signal line selection order may be changed. However, in this configuration, depending on the scanning direction of the scanning signal line, the voltage applied to the liquid crystal may not be properly converted into an alternating current and a direct current component may be applied. In this case, flicker occurs in the display image in the liquid crystal display device, and there is a possibility that an image sticking or afterimage may occur due to deterioration of the liquid crystal.

Therefore, an object of the present invention is to provide an active matrix display device that can perform AC drive correctly even if the scanning direction corresponding to the selection order of the scanning signal lines is changed, and a driving circuit and driving method thereof.

A first aspect of the present invention is a matrix corresponding to a plurality of data signal lines, a plurality of scanning signal lines intersecting with the plurality of data signal lines, and the plurality of data signal lines and the plurality of scanning signal lines. A plurality of pixel electrodes arranged in a shape, a common electrode arranged so as to face the plurality of pixel electrodes, and a pixel electrode provided for each pixel electrode to connect each pixel electrode to a corresponding data signal line A drive circuit for an alternating current drive type display device including a switching element having a control terminal connected to a scanning signal line,
A data signal line driver that applies a plurality of data signals representing an image to be displayed to the plurality of data signal lines;
A scanning signal that sequentially activates the plurality of scanning signal lines and can switch a scanning direction corresponding to the activation order of the plurality of scanning signal lines between a first direction and a second direction that are opposite to each other. A line driver;
A counter voltage supply unit that outputs a counter voltage to be applied to the common electrode;
Select one of the first direction and the second direction as the scanning direction, and set the scanning signal line driver to activate the plurality of scanning signals in the order corresponding to the selected scanning direction. The counter voltage corresponding to the selected scanning direction is output from two different counter voltages including the first counter voltage for the first direction and the second counter voltage for the second direction. And a control unit for controlling the counter voltage supply unit.

According to a second aspect of the present invention, in the first aspect of the present invention,
The scanning signal line driving unit drives the plurality of scanning signal lines such that periods in which adjacent scanning signal lines are activated partially overlap each other.

According to a third aspect of the present invention, in the second aspect of the present invention,
The scanning signal line driving unit includes:
When the first direction is selected as the scanning direction, the first scanning signal connected to the control terminal of the switching element corresponding to the pixel electrode among the two scanning signal lines adjacent to each pixel electrode. Before activating the line, activate the second scanning signal line that is not connected to the control terminal of the switching element among the two scanning signal lines,
When the second direction is selected as the scanning direction, the second scanning signal line is activated after activating the first scanning signal line;
The first counter voltage includes a voltage change amount in the first scanning signal line when the first scanning signal line changes from an activated state to an inactivated state, and the first scanning signal line and the first scanning signal line. It is a voltage obtained by increasing or decreasing the center voltage of the data signal according to the parasitic capacitance between the pixel electrode,
The second counter voltage includes a voltage change amount in the second scanning signal line when the second scanning signal line changes from an activated state to an inactivated state, and the second scanning signal line and the second scanning signal line. The voltage is obtained by increasing or decreasing the first counter voltage according to the parasitic capacitance between the pixel electrode and the pixel electrode.

According to a fourth aspect of the present invention, in the second or third aspect of the present invention,
The scanning signal line drive unit displays the scanning signal line connected to the control terminal of the switching element corresponding to each pixel electrode, and the data signal indicating the pixel corresponding to the pixel electrode in the image to be displayed. In a period consisting of a main charging period to be applied to the electrode and a pre-charging period that is a predetermined period immediately before the main charging period, it is continuously activated.
The data signal line driver generates the plurality of data signals so that the polarities of the plurality of data signals do not change within the same frame period.

According to a fifth aspect of the present invention, in any one of the first to fourth aspects of the present invention,
The counter voltage supply unit includes:
A voltage generator for generating the first and second counter voltages;
And a selector that selects one of the first and second counter voltages as a counter voltage to be applied to the common electrode based on a control signal from the control unit.

According to a sixth aspect of the present invention, in any one of the first to fourth aspects of the present invention,
At least one of the first and second counter voltages is input from the outside,
The counter voltage supply unit includes a selector that selects one of the first and second counter voltages as a counter voltage to be applied to the common electrode based on a control signal from the control unit. .

A seventh aspect of the present invention is a display device, and includes a drive circuit according to any one of the first to fourth aspects of the present invention.

According to an eighth aspect of the present invention, in the seventh aspect of the present invention,
The switching element is a thin film transistor including a channel layer formed of an oxide semiconductor.

According to a ninth aspect of the present invention, a plurality of data signal lines, a plurality of scanning signal lines intersecting with the plurality of data signal lines, a matrix corresponding to the plurality of data signal lines and the plurality of scanning signal lines are provided. A plurality of pixel electrodes arranged in a shape, a common electrode arranged so as to face the plurality of pixel electrodes, and a pixel electrode provided for each pixel electrode to connect each pixel electrode to a corresponding data signal line A driving method of an AC driving type display device including a switching element having a control terminal connected to a scanning signal line,
A data signal line driving step of applying a plurality of data signals representing an image to be displayed to the plurality of data signal lines;
A scanning signal line driving step for sequentially activating the plurality of scanning signal lines;
A counter voltage supply step of outputting a counter voltage to be applied to the common electrode;
A scanning direction selection step of selecting one of a first direction and a second direction that are opposite to each other as a scanning direction corresponding to the activation order of the plurality of scanning signal lines;
In the scanning signal line driving step, the plurality of scanning signals are activated in the order corresponding to the scanning direction selected in the scanning direction selection step,
In the counter voltage supply step, the scanning direction selected in the scanning direction selection step is selected from two different counter voltages including the first counter voltage for the first direction and the second counter voltage for the second direction. A counter voltage corresponding to the output is output.

Since other aspects of the present invention will be apparent from the description of the above aspect of the present invention and the following embodiments, description thereof will be omitted.

According to the first aspect of the present invention, the first counter voltage is applied to the common electrode when scanning is performed in the first direction, and the second counter voltage is applied when scanning is performed in the second direction. Is applied. That is, the counter voltage applied to the common electrode is switched according to the scanning direction corresponding to the activation order of the scanning signal lines. As a result, even when scanning is performed in any one of the first and second directions, the display device is appropriately AC driven, and the DC component in the voltage applied between each pixel electrode and the common electrode is suppressed. Is done. As a result, occurrence of flicker in the display image can be suppressed, and deterioration of the liquid crystal can be prevented when the present invention is applied to a liquid crystal display device.

According to the second aspect of the present invention, two periods in which two adjacent scanning signal lines are activated partially overlap each other, and therefore, due to a voltage change in the scanning signal line adjacent to each pixel electrode. The influence on the voltage of each pixel electrode (the voltage held in the capacitor formed by each pixel electrode and the common electrode) differs depending on the activation order (scanning direction) of the scanning signal lines. That is, there is a parasitic capacitance between each pixel electrode and two adjacent scanning signal lines, and one of the two scanning signal lines is connected to the control terminal of the switching element corresponding to the pixel electrode. However, the other is not connected to the control terminal, and the influence of the voltage change in the other scanning signal line on the voltage of the pixel electrode is which of the two scanning signal lines is activated first. Depends on (see FIG. 5). For this reason, the voltage to be applied to the common electrode for correct AC driving varies depending on the scanning direction. On the other hand, in the second aspect of the present invention, the first and second counter voltages are set to values in consideration of such differences depending on the scanning direction, so that any of the first and second directions is set. Even when scanning is performed, the display device is appropriately AC driven, and the DC component in the voltage applied between each pixel electrode and the common electrode is suppressed.

According to the third aspect of the present invention, the first counter voltage applied to the common electrode when scanning in the first direction changes from the activated state to the deactivated state of the first scanning signal line. A voltage obtained by increasing or decreasing the center voltage of the data signal in accordance with the amount of voltage change in the first scanning signal line and the parasitic capacitance between the first scanning signal line and the pixel electrode, The second counter voltage applied to the common electrode when scanning in the second direction is the voltage on the second scanning signal line when the second scanning signal line changes from the activated state to the inactivated state. This is a voltage obtained by increasing or decreasing the first counter voltage according to the amount of change and the parasitic capacitance between the second scanning signal line and the pixel electrode. As a result, even when scanning is performed in any one of the first and second directions, the display device is appropriately AC driven, and the DC component in the voltage applied between each pixel electrode and the common electrode is suppressed. Is done.

According to the fourth aspect of the present invention, the scanning signal line connected to the control terminal of the switching element corresponding to each pixel electrode receives the data signal indicating the pixel corresponding to the pixel electrode in the image to be displayed. In addition to being activated in the main charging period to be applied to the pixel electrode (that is, the period for charging the capacitor formed by the pixel electrode and the common electrode with the voltage of the data signal), the preliminary period immediately before that is activated. Each data signal is generated so that the polarity of each data signal does not change within the same frame period. For this reason, the polarity of the voltage applied to each pixel electrode from the corresponding data signal line via the corresponding switching element during the preliminary charging period is determined from the data signal line via the switching element during the main charging period immediately thereafter. This coincides with the polarity of a voltage applied to the pixel electrode (a voltage indicating a pixel corresponding to the pixel electrode). Thereby, the charging rate in the main charging period of the capacitance formed by each pixel electrode and the common electrode can be improved, and insufficient charging can be prevented even if the display screen is increased in size or resolution. In addition, the fourth aspect of the present invention has the same configuration as the second or third aspect of the present invention, so that the display device has the effect of improving the charging rate by driving as described above. There is also an effect that the direct current component in the voltage applied between each pixel electrode and the common electrode is suppressed appropriately and the direct current component is suppressed.

According to the fifth aspect of the present invention, the first and second counter voltages are generated in the counter voltage supply unit, and scanning is performed in the first direction based on the control signal from the control unit. When the counter voltage is selected and scanning is performed in the second direction, the second counter voltage is selected. When the counter voltage selected in this way is applied to the common electrode, the display device is appropriately AC driven, and the DC component in the applied voltage between each pixel electrode and the common electrode is suppressed.

According to the sixth aspect of the present invention, at least one of the first and second counter voltages is input from the outside, and one of the first and second counter voltages is selected based on a control signal from the control unit. The When the counter voltage selected in this way is applied to the common electrode, the display device is appropriately AC driven, and the DC component in the applied voltage between each pixel electrode and the common electrode is suppressed.

According to the seventh aspect of the present invention, there is provided a display device having the same effects as any one of the first to fourth aspects of the present invention.

According to the eighth aspect of the present invention, the switching element provided for each pixel electrode is a thin film transistor including a channel layer formed of an oxide semiconductor, and since the off-leakage current is small, each switching element is interposed via the switching element. The voltage applied to the pixel electrode can be reliably held in the capacitor formed by the pixel electrode and the common electrode.

According to the ninth aspect of the present invention, the same effects as in the first aspect of the present invention are achieved.

Since the effects of other aspects of the present invention are clear from the effects of the above aspects of the present invention and the description of the following embodiments, the description thereof will be omitted.

1 is a block diagram illustrating a configuration of a liquid crystal display device according to a first embodiment of the present invention. 4 is a timing chart for explaining an operation during forward scanning of the liquid crystal display device according to the first embodiment. 6 is a timing chart for explaining an operation during backward scanning of the liquid crystal display device according to the first embodiment. It is a figure which shows typically the structure of the pixel circuit of the TFT substrate in the said 1st Embodiment. FIG. 6 is a signal waveform diagram (A to D) for explaining the relationship between the scanning direction and the counter DC voltage in the liquid crystal display device according to the first embodiment. It is a block diagram which shows the structure of the liquid crystal display device which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the liquid crystal display device which concerns on the 3rd Embodiment of this invention.

<1. First Embodiment>
<1.1 Overall configuration and operation overview>
FIG. 1 is a block diagram showing the configuration of the liquid crystal display device according to the first embodiment of the present invention. As shown in FIG. 1, the liquid crystal display device includes a liquid crystal panel 100 as a display panel, a source driver 300 as a data signal line driver, a gate driver 400 as a scanning signal line driver, and a counter voltage supply unit. As a common electrode driving circuit 500 and a display control circuit 200. Further, in order to display an image on the liquid crystal panel 100, a backlight for irradiating light on the back surface is necessary, and this liquid crystal display device also includes such a backlight (not shown). The source driver 300, the gate driver 400, the common electrode driving circuit 500, and the display control circuit 200 constitute a driving circuit for the liquid crystal display device according to the present embodiment.

The liquid crystal panel 100 includes an insulating first substrate called a TFT substrate, an insulating second substrate called a CF substrate, and a liquid crystal layer sandwiched between the first and second substrates. The TFT substrate and the CF substrate are typically glass substrates. The TFT substrate intersects the source lines SL1 to SLM as a plurality (M) of data signal lines and the plurality (M) of source lines Ls. Gate lines GL0 to GLN as a plurality of (N + 1) scanning signal lines, and a plurality (N × M) arranged in a matrix along the plurality of source lines SL1 to SLM and the plurality of gate lines GL1 to GLN Pixel circuits are formed. Here, each pixel circuit corresponds to one of the plurality of source lines SL1 to SLM and also corresponds to one of the plurality of gate lines GL1 to GLN, and corresponds to the corresponding source line SLj and corresponding gate line GLi. It is connected to the. Each pixel circuit 110 includes a pixel electrode Ep (see FIG. 4 described later), and the pixel electrodes Ep of the N × M pixel circuits 110 in the liquid crystal panel 100 correspond to the pixels constituting the image to be displayed, respectively. It corresponds. The gate line GL0 is provided so that the influence of the parasitic capacitance on the voltage of the pixel electrode does not vary depending on the pixel circuit (details will be described later).

On the other hand, a common electrode COM is formed on the CF substrate, and color filters corresponding to primary colors for color display (for example, red, green, and blue color filters that are three primary colors) and various optical compensation films (polarized light). A plate or the like).

The pixel forming portion Px for forming each pixel of an image to be displayed on the liquid crystal panel 100 includes a pixel circuit formed on the TFT substrate, the liquid crystal layer, the common electrode COM, and the color. It consists of color filters for display. However, the liquid crystal layer and the common electrode COM are provided in common to the plurality (N × M) of pixel forming portions Px. The N × M pixel forming portions Px are pixel circuits included in the N × M pixel forming portions Px in correspondence with the N gate lines GL1 to GLN and the M data signal lines SL1 to SLM, respectively. The same applies to the pixel electrode Ep included in each of the N × M pixel circuits 110.

FIG. 4 schematically shows the configuration of the pixel circuit 110 formed on the TFT substrate. As shown in FIG. 4, the pixel circuit 110 includes an N-channel TFT 10 as a switching element and a pixel electrode Ep corresponding to a pixel of an image to be displayed. The pixel electrode Ep is a corresponding source line via the TFT 10. The gate terminal of the TFT 10 is connected to the corresponding gate line GLi. Of the two gate lines GLi-1 and GLi adjacent to the pixel electrode Ep, the first parasitic capacitance Cgd1 is between the corresponding gate line (hereinafter referred to as “corresponding adjacent gate line”) GLi and the pixel electrode Ep. In addition, there is a second parasitic capacitance Cgd2 between the other gate line (hereinafter referred to as “non-corresponding adjacent gate line”) GLi-1 and the pixel electrode Ep. Note that the pixel capacitor Cp for holding a voltage indicating the pixel (its luminance) is a liquid crystal capacitor Clc formed between the pixel electrode Ep and the common electrode COM on the CF substrate. However, when an auxiliary capacitance line is formed on the TFT substrate to hold the voltage more reliably, an auxiliary capacitance Ccs is formed between the pixel electrode Ep and the auxiliary capacitance line, and the auxiliary capacitance Ccs is also a pixel capacitance. Included in Cp. Since the auxiliary capacitor Ccs is not directly related to the present invention, description and illustration regarding the auxiliary capacitor Ccs will be omitted below.

FIG. 1 also shows the electrical configuration of the pixel formation portion Px in the liquid crystal panel 100. Hereinafter, the pixel formation portions corresponding to the gate line GLi and the source line SLj may be indicated by the symbol “Px (i, j)” instead of the symbol “Px”. As described above, the pixel forming portion Px (i, j) includes a pixel circuit (see FIG. 4) on the TFT substrate, a liquid crystal layer, a common electrode COM on the CF substrate, a color filter, and the like. Electrically, as shown in FIG. 1, the TFT 10 includes a pixel capacitor Cp (liquid crystal capacitor Clc), and first and second parasitic capacitors Cgd1 and Cgd2, and the pixel electrode Ep passes through the pixel capacitor Cp. Not only connected to the common electrode COM but also capacitively coupled to the corresponding adjacent gate line GLi via the first parasitic capacitance Cgd1 and non-corresponding adjacent gate line via the second parasitic capacitance Cgd2. It is also capacitively coupled to GLi-1. In this embodiment, the gate line GL0 that does not correspond to any pixel circuit 110 is formed on the TFT substrate as a non-corresponding adjacent gate line for the pixel electrode Ep of each pixel circuit corresponding to the first gate line GL1. . As a result, in each pixel circuit corresponding to the first gate line GL1, not only the first parasitic capacitance Cgd1 exists between the pixel electrode Ep and the corresponding adjacent gate line GL1, but also the adjacent non-corresponding to the pixel electrode. A second parasitic capacitance Cgd2 exists between the gate line GL0. As a result, in all the pixel circuits, the voltage of the pixel electrode Ep is not only influenced by the voltage change of the corresponding adjacent gate line GLi via the first parasitic capacitance Cgd1, but is not affected via the second parasitic capacitance Cgd2. It is also affected by the voltage change of the corresponding adjacent gate line GLi-1.

The display control circuit 200 receives an image signal Dv representing an image to be displayed and a timing control signal Ct from the outside, and a source driver control signal Sct comprising an image data signal based on the image signal Dv and a timing control signal for a source driver. Is generated and supplied to the source driver 300, and a gate driver control signal Gct is generated and supplied to the gate driver 400. In addition, the display control circuit 200 generates a direction designation signal Cud for designating a scanning direction corresponding to the selection order (activation order) of the gate lines GL0 to GLN, and supplies it to the gate driver 400 and the common electrode drive circuit 500. Here, the direction designation signal Cud is a scan for activating the gate line GLi for a predetermined period in order of i = 0, 1, 2,..., N, that is, a scan for selecting the gate line GLi in ascending order (hereinafter “forward scan”). Scanning for activating the gate line GLi in a predetermined period in the order of i = N, N-1,..., 1, 0, that is, scanning for selecting the gate line GLi in descending order (hereinafter referred to as “reverse scanning”). Specify one of them. The value of the direction designation signal Cud, that is, which one of the forward direction scanning and the reverse direction scanning is designated is determined based on, for example, a signal supplied to the display control circuit 200 from the outside. Can do. Alternatively, a changeover switch for setting the scanning direction is provided in the liquid crystal display device according to the present embodiment, and the value of the direction designation signal Cud is determined by operating this switch. It may be. In the following, it is assumed that forward direction scanning is designated when the direction designation signal Cud is at a high level (H level), and reverse direction scanning is designated when the direction designation signal Cud is at a low level (L level).

Based on the source driver control signal Sct, the source driver 300 generates analog voltages for driving the liquid crystal panel 100 as the data signals S1, S2,..., SM, and generates these M sources in the liquid crystal panel 100. Apply to lines SL1 to SLM, respectively.

The gate driver 400 has a built-in bidirectional shift register, and is configured so that the order in which the gate lines GL0 to GLN are activated can be switched by using the bidirectional shift register. And backward scanning are possible. The gate driver 400 generates scanning signals G0, G1,..., GN based on the gate driver control signal Gct and the direction control signal Cud, and outputs them to N + 1 gate lines GL0, GL1,. , GLN, the N + 1 gate lines GL0 to GLN are selectively activated in a predetermined period (in this embodiment, every two horizontal periods) in the order indicated by the direction designation signal Cud.

As shown in FIG. 1, the common electrode drive circuit 500 includes a first counter voltage generation circuit 51 that generates a first counter voltage VcomA that is a counter DC voltage for forward scanning, and a counter DC voltage for reverse scanning. A second counter voltage generation circuit 52 for generating a second counter voltage VcomB, and a changeover switch 54 as a selector for selecting one of the first counter voltage VcomA and the second counter voltage VcomB. The direction designation signal Cud is received from the display control circuit 200 as a control signal for the changeover switch 54. The changeover switch 54 selects the first counter voltage VcomA when the direction designation signal Cud is at the H level, and selects the second counter voltage VcomB when the direction designation signal Cud is at the L level. The counter DC voltage selected in this way is output from the common electrode drive circuit 500 as the selected counter DC voltage Vcom and is applied to the common electrode COM of the liquid crystal panel 100.

As described above, in the liquid crystal panel 100, the data signals S1 to SM based on the image signal Dv input from the outside are applied to the source lines SL1 to SLM, and scanning specified by the direction specifying signal Cud from the display control circuit 200 is performed. Scan signals G0 to GN corresponding to the directions are applied to the gate lines GL0 to GLN. Further, the selected counter DC voltage Vcom corresponding to the scanning direction designated by the direction designation signal Cud is applied to the common electrode COM from the common electrode driving circuit 500 to the common electrode COM. As a result, each pixel forming portion Px (i, j) in the liquid crystal panel 100, when the corresponding gate line GLi is activated, the data signal Sj of the corresponding source line SLj (of the corresponding source line SLj). Voltage) is taken in via the TFT 10 and applied to the pixel capacitor Cp. Thereafter, when the corresponding gate line GLi is deactivated, the voltage corresponding to the data signal Sj is applied to the pixel capacitor Cp as it is until the corresponding gate line GLi is activated again in the next frame period. Retained. In this way, the voltage corresponding to the data signal Sj is applied to and held in each pixel capacitor Cp, so that the liquid crystal panel 100 is applied with a voltage corresponding to the image signal Dv to the liquid crystal layer, thereby transmitting light. The image represented by the image signal Dv is displayed.

In the liquid crystal display device shown in FIG. 1, the source driver 300, the gate driver 400, and the common electrode driving circuit 500 are separate components from the liquid crystal panel 100. 300, the gate driver 400, and the common electrode drive circuit 500 may be configured to be formed integrally with the pixel circuit using the TFT on the TFT substrate of the liquid crystal panel 100 (simultaneously in the same process). . For example, the gate driver 400 may be configured to use a gate driver monolithic panel that is a liquid crystal panel formed integrally with a pixel circuit on a TFT substrate.

<1.2 Operation>
FIG. 2 is a timing chart for explaining the operation of the liquid crystal display device according to the present embodiment when the direction designation signal Cud is at the H level, that is, when the forward scanning is designated. In this case, the gate driver 400 sequentially sets the scanning signals G0 to GN to the H level at intervals of one horizontal period in each frame period, and sets the scanning signal Gi (i = 0 to N) at the H level to the H level for two horizontal periods. After being maintained, it is set to L level, and then maintained at L level until it is again set to H level in the next frame period. Thus, N + 1 gate lines GLi are sequentially activated at intervals of one horizontal period in order of i = 0, 1,..., N−1, N in each frame period. After being kept in the activated state for a period, it is deactivated, and then kept in the inactive state until it is activated again in the next frame period.

In this case, as shown in FIG. 2, the source driver 300 should capture and hold each source line SLj (j = 1 to M) by the pixel formation portion Px (i, j) connected thereto. The voltage, that is, the voltage indicating the pixel to be formed by the pixel forming unit Px (i, j) is output as the data signal Sj, and the polarity of the output data signal Sj is inverted every frame period, and in each frame period The polarities of the data signals S1 to SM are inverted for each source line (data signals Sj-1 and Sj having different polarities are applied to two adjacent source lines SLj-1 and SLj). The timing chart of the data signals S1 to S4 shown in FIG. 2 is composed of two upper and lower stages, the upper stage shows the polarity of the data signal Sj, the lower stage shows the value of the data signal Sj, and dij (I = 1, 2,..., N; j = 1, 2,..., M) represents a value corresponding to a voltage to be captured and held by the pixel forming portion Px (i, j) (data signal). Such a notation for the timing charts of S1 to S4 is the same in the timing charts of other figures referred to below). As can be seen from the data signals S1 to S4 shown in FIG. 2, the data signal Sj corresponding to the voltage to be taken in by each pixel forming unit Px (i, j) is activated in the corresponding gate line GLi in each frame period. This is applied to the corresponding source line SLj in the latter one horizontal period of the two horizontal periods.

In this case, the common electrode driving circuit 500 selects the first counter voltage VcomA by the changeover switch 54 and applies it to the common electrode COM of the liquid crystal panel 100 as the selected counter DC voltage Vcom. Accordingly, in each pixel forming unit Pix (i, j), the voltage of the data signal Sj applied to the pixel electrode Ep and the selected counter DC voltage Vcom with a voltage polarity based on the selected counter DC voltage Vcom = VcomA. A voltage corresponding to the difference is applied to the liquid crystal.

FIG. 3 is a timing chart for explaining the operation of the liquid crystal display device according to the present embodiment when the direction designation signal Cud is at L level, that is, when reverse scanning is designated. In this case, the gate driver 400 sequentially sets the scanning signals G0 to GN to the H level by two horizontal periods in the opposite direction to the case of forward scanning (FIG. 2) at intervals of one horizontal period in each frame period. As a result, N + 1 gate lines GLi are activated by two horizontal periods at intervals of one horizontal period in the order of i = N, N−1,..., 0 in each frame period.

Further, in this case, the source driver 300, as shown in FIG. 3, for each source line SLj (j = 1 to M), the pixel formation portion Px (i, j) (i = 1 to N) connected thereto. Is output as a data signal Sj, the polarity of the output data signal Sj is inverted every frame period, and the polarity of the data signals S1 to SM in each frame period is changed for each source line. Invert to. As can be seen from the data signals S1 to S4 shown in FIG. 3, the data signal Sj corresponding to the voltage to be taken in by each pixel forming unit Px (i, j) is activated in the corresponding gate line GLi in each frame period. This is applied to the corresponding source line SLj in the latter one horizontal period of the two horizontal periods.

In this case, the common electrode driving circuit 500 selects the second counter voltage VcomB by the changeover switch 54 and applies it to the common electrode COM of the liquid crystal panel 100 as the selected counter DC voltage Vcom. Therefore, in each pixel forming unit Pix (i, j), the voltage polarity based on the selected counter DC voltage Vcom = VcomB is used as a reference between the voltage of the data signal Sj applied to the pixel electrode Ep and the selected counter DC voltage Vcom. A voltage corresponding to the difference is applied to the liquid crystal.

As can be seen from the scanning signals G1 to G4 shown in FIGS. 2 and 3, the gate driver 400 has a pulse with a width corresponding to two horizontal periods for each scanning signal Gi, and two adjacent gate lines GLi−. The scanning signals G0 to GN are generated so that the pulses overlap each other for one horizontal period between the two scanning signals Gi-1 and Gi to be applied to 1 and GLi, respectively. In the present embodiment, the polarity of the data signals S1 to SM is inverted every frame period, but the polarity of the data signals S1 to SM is not changed within the same frame period (in the example shown in FIGS. 2 and 3). A so-called “source inversion drive” or “column inversion drive” is used. The source driver 300 generates data signals S1 to SM corresponding to such inversion driving.

According to such a configuration, the width of the pulse included in each scanning signal Gi is twice that of the conventional one (two horizontal periods), and each data signal Sj has the same polarity during this pulse width period. That is, the gate lines G0 to GN of the liquid crystal panel 100 are sequentially set to 1 in the forward direction or the reverse direction so that each pixel forming unit Px (i, j) takes in the voltage of the corresponding source line SLj as the pixel value of the image to be displayed. Not only the horizontal period is activated, but also the gate line GLj is activated in one horizontal period immediately before the one horizontal period in the activated state (hereinafter referred to as “main charging period”). The voltage polarity of the source line SLj in the period is the same as the voltage polarity of the source line SLj in one horizontal period as the main charging period. Therefore, the first horizontal period of the two horizontal periods in which the gate line GLj is activated in the immediately preceding horizontal period, that is, each frame period, functions as a preliminary charging period. Thereby, the charging rate of the pixel capacitance Cp can be improved.

<1.3 Counter DC voltage setting>
FIG. 5 is a signal waveform diagram for explaining the relationship between the scanning direction and the counter DC voltage in the liquid crystal display device according to the present embodiment. The setting of the counter DC voltage according to the scanning direction of the gate lines GL0 to GLN will be described below with reference to FIG. 5 together with FIG. 4 schematically showing the configuration of the pixel circuit.

FIG. 5A shows that when positive direction scanning is designated (when the direction designation signal Cud = H), the positive data signal Sj is a pixel of the pixel formation portion Px (i, j) (pixel circuit 110). The waveforms of the scanning signals Gi−1, Gi and the voltage of the pixel electrode Ep (hereinafter referred to as “pixel voltage Vp (i, j)”) when applied to the electrode Ep are schematically shown. At this time, when paying attention to the pixel electrode Ep of the pixel formation portion Px (i, j), the scanning signal (hereinafter referred to as “non-corresponding adjacent scanning signal”) Gi−1 of the non-corresponding adjacent gate line GL i-1 is changed from the L level. When one horizontal period elapses from the time when the level changes to H level, the scanning signal Gi (hereinafter referred to as “corresponding scanning signal”) Gi of the corresponding adjacent gate line GLi changes from L level to H level. As a result, the corresponding adjacent gate line GLi is activated, and the voltage of the corresponding source line SLj (the voltage of the data signal Sj) is applied to the pixel electrode Ep. Here, in the first horizontal period, that is, the preliminary charging period, of the two horizontal periods in which the corresponding adjacent gate line GLi is activated (two horizontal periods in which the scanning signal Gi is at the H level), the non-corresponding adjacent gate line GLi− A voltage indicating a pixel to be formed in the pixel forming portion Px (i−1, j) corresponding to 1 is applied to the corresponding source line SLj.

When one horizontal period elapses from when the corresponding scanning signal Gi changes from the L level to the H level, the non-corresponding adjacent scanning signal Gi-1 changes from the H level to the L level, and the non-corresponding adjacent gate line GLi-1. Is deactivated. At this time, the change from the H level to the L level of the non-corresponding adjacent scanning signal Gi-1 affects the pixel voltage Vp (i, j) via the second parasitic capacitance Cgd2. However, at this time, since the corresponding scanning signal Gi is at the H level and the TFT 10 is in the ON state, this influence only lowers the pixel voltage Vp (i, j) temporarily. At this time, the data signal Sj indicating the pixel to be formed by the pixel formation portion Px (i, j) is applied to the corresponding source line SLj. As a result, the voltage of the data signal Sj indicating the pixel is supplied from the corresponding source line SLj to the pixel electrode Ep of the pixel formation portion Px (i, j) via the TFT 10. That is, the main charging period for the pixel capacitance Cp of the pixel formation portion Px (i, j) is started. Thereafter, when one horizontal period elapses after the non-corresponding adjacent scanning signal Gi-1 changes from the H level to the L level, the corresponding scanning signal Gi changes from the H level to the L level, and the corresponding gate line GLi becomes non- Activated. Thereby, the main charging period ends.

The change of the corresponding scanning signal Gi from the H level to the L level at the end of the main charging period affects the pixel voltage Vp (i, j) via the first parasitic capacitance Cgd1. That is, the pixel voltage Vp (i, j) decreases by ΔVp (> 0) in accordance with the change of the corresponding scanning signal Gi from the H level to the L level. This reduced voltage ΔVp is called a pull-in voltage or the like, and the magnitude thereof is the amount of voltage change of the gate line GLi and the first parasitic capacitance Cgd1 when the corresponding scanning signal Gi changes from the H level to the L level. It depends on. Thereafter, the pixel voltage Vp (i, j) is the pixel immediately before the end of the main charging period until the corresponding scanning signal Gi becomes H level again in the next frame period (until the corresponding gate line GLi is activated again). The voltage (VwP−ΔVp), which is reduced from the voltage Vp (i, j) = VwP by the pull-in voltage ΔVp, is maintained.

FIG. 5B shows a case where the negative direction data signal Sj is the pixel of the pixel formation portion Px (i, j) (pixel circuit 110) when the forward direction scanning is designated (when the direction designation signal Cud = H). The waveforms of the scanning signals Gi-1 and Gi and the pixel voltage Vp (i, j) when applied to the electrode Ep are schematically shown. Also at this time, the pixel voltage Vp (i, j) is applied to the pixel forming portion Px (i, j) in one horizontal period (main charging period) of the latter half of the two horizontal periods in which the corresponding scanning signal Gi is at the H level. A data signal Sj indicating a pixel to be formed is applied to the corresponding source line SLj. As a result, the voltage of the negative data signal Sj indicating the pixel is supplied from the corresponding source line SLj to the pixel electrode Ep of the pixel formation portion Px (i, j) via the TFT 10. Then, at the end of the main charging period, the corresponding scanning signal Gi changes from the H level to the L level, and this change affects the pixel voltage Vp (i, j) via the first parasitic capacitance Cgd1. That is, the pixel voltage Vp (i, j) decreases by the pull-in voltage ΔVp (> 0) in accordance with the change of the corresponding scanning signal Gi from the H level to the L level. Thereafter, the pixel voltage Vp (i, j) is equal to the pixel voltage Vp (i, j) = VwN (<0) immediately before the end of the main charging period until the corresponding scanning signal Gi becomes H level again in the next frame period. Is maintained at a voltage (VwN−ΔVp) lowered by the pull-in voltage ΔVp. The magnitude of the pull-in voltage ΔVp is the same as when the positive data signal Sj is applied to the pixel electrode Ep of the pixel formation portion Px (i, j) (FIG. 5A).

Therefore, as can be seen from FIGS. 5A and 5B, the voltage Vcen corresponding to the center in the voltage range that the data signal Sj can take (hereinafter referred to as “source center voltage” or “center voltage of the data signal”) Vcen. Is applied to the common electrode COM as the counter DC voltage, the liquid crystal panel 100 is not correctly AC driven due to the pull-in voltage ΔVp, and a DC component is included in the voltage applied to the liquid crystal of the liquid crystal panel 100. As a result, flicker occurs in the displayed image, and the liquid crystal may be deteriorated.

Therefore, in the present embodiment, the counter DC voltage applied to the common electrode COM, that is, the first counter voltage VcomA when the forward scanning is designated, corresponds to the source center voltage Vcen in accordance with the pull-in voltage Δp (> 0). Is set to a reduced voltage.

FIG. 5C shows a case where the reverse direction scanning is designated (when the direction designation signal Cud = L), the positive data signal Sj is the pixel of the pixel formation portion Px (i, j) (pixel circuit 110). The waveforms of the scanning signals Gi-1 and Gi and the pixel voltage Vp (i, j) when applied to the electrode Ep are schematically shown. At this time, when attention is paid to the pixel electrode Ep of the pixel forming portion Px (i, j), the corresponding scanning signal Gi, which is the scanning signal of the corresponding adjacent gate line GLi, changes from the L level to the H level, and is H for two horizontal periods. The level is maintained, and the corresponding adjacent gate line GLi is activated in the two horizontal periods. One horizontal period in the first half of these two horizontal periods is a preliminary charging period, and in this preliminary charging period, pixels to be formed by the pixel forming portion Px (i + 1, j) corresponding to the i + 1-th gate line GLi + 1. The voltage shown is applied to the corresponding source line SLj.

When one horizontal period elapses from the time when the corresponding scanning signal Gi changes from the L level to the H level, the non-corresponding adjacent scanning signal Gi-1 changes from the L level to the H level, and the non-corresponding adjacent gate line GLi-1. Is activated. At this time, the change from the L level to the H level of the non-corresponding adjacent scanning signal Gi affects the pixel voltage Vp (i, j) via the second parasitic capacitance Cgd2. However, at this time, since the corresponding scanning signal Gi is at the H level and the TFT 10 is in the ON state, this influence only raises the pixel voltage Vp (i, j) temporarily. At this time, the data signal Sj indicating the pixel to be formed by the pixel formation portion Px (i, j) is applied to the corresponding source line SLj. As a result, the voltage of the data signal Sj indicating the pixel is supplied from the corresponding source line SLj to the pixel electrode Ep of the pixel formation portion Px (i, j) via the TFT 10. That is, the main charging period for the pixel capacitance Cp of the pixel formation portion Px (i, j) is started. Thereafter, when one horizontal period elapses after the non-corresponding adjacent scanning signal Gi-1 changes from the L level to the H level, the corresponding scanning signal Gi changes from the H level to the L level, and the corresponding gate line GLi becomes non- Activated. Thereby, the main charging period ends.

The change of the corresponding scanning signal Gi from the H level to the L level at the end of the main charging period affects the pixel voltage Vp (i, j) via the first parasitic capacitance Cgd1. That is, the pixel voltage Vp (i, j) decreases by ΔVp1 (> 0) in accordance with the change of the corresponding scanning signal Gi from the H level to the L level. The magnitude of this reduced voltage (hereinafter referred to as “first pull-in voltage”) ΔVp1 is the amount of voltage change of the gate line GLi and the first parasitic when the corresponding scanning signal Gi changes from H level to L level. It depends on the capacitance Cgd1 and the like.

When one horizontal period elapses from the time when the corresponding scanning signal Gi changes from the H level to the L level, the non-corresponding adjacent scanning signal Gi-1 changes from the H level to the L level, and the non-corresponding adjacent gate line GLi-1. Is deactivated. At this time, the change from the H level to the L level of the non-corresponding adjacent scanning signal Gi-1 affects the pixel voltage Vp (i, j) via the second parasitic capacitance Cgd2. That is, the pixel voltage Vp (i, j) further decreases by ΔVp2 (> 0) in accordance with the change of the non-corresponding adjacent scanning signal Gi-1 from the H level to the L level. The magnitude of this reduced voltage (hereinafter referred to as “second pull-in voltage”) ΔVp2 is the voltage change of the gate line GLi-1 when the non-corresponding adjacent scanning signal Gi-1 changes from H level to L level. It depends on the quantity, the second parasitic capacitance Cgd2, etc. Thereafter, the pixel voltage Vp (i, j) is changed from the pixel voltage Vp (i, j) = VwP immediately before the end of the main charging period until the corresponding scanning signal Gi becomes H level again in the next frame period. The voltage (VwP−ΔVp1−ΔVp2) decreased by the pull-in voltage ΔVp1 and the second pull-in voltage ΔVp2 is maintained.

FIG. 5D shows a case where the negative data signal Sj is a pixel of the pixel formation portion Px (i, j) (pixel circuit 110) when reverse scanning is designated (when the direction designation signal Cud = L). The waveforms of the scanning signals Gi-1 and Gi and the pixel voltage Vp (i, j) when applied to the electrode Ep are schematically shown. Also at this time, the pixel voltage Vp (i, j) is applied to the pixel forming portion Px (i, j) in one horizontal period (main charging period) of the latter half of the two horizontal periods in which the corresponding scanning signal Gi is at the H level. A data signal Sj indicating a pixel to be formed is applied to the corresponding source line SLj. As a result, the voltage of the negative data signal Sj indicating the pixel is supplied from the corresponding source line SLj to the pixel electrode Ep of the pixel formation portion Px (i, j) via the TFT 10. Then, at the end of the main charging period, the corresponding scanning signal Gi changes from the H level to the L level, and this change affects the pixel voltage Vp (i, j) via the first parasitic capacitance Cgd1. That is, the pixel voltage Vp (i, j) decreases by the first pull-in voltage ΔVp1 (> 0) in accordance with the change of the corresponding scanning signal Gi from the H level to the L level.

When one horizontal period elapses from the time when the corresponding scanning signal Gi changes from the H level to the L level, the non-corresponding adjacent scanning signal Gi-1 changes from the H level to the L level, and the non-corresponding adjacent gate line GLi-1. Is deactivated. At this time, the change from the H level to the L level of the non-corresponding adjacent scanning signal Gi-1 affects the pixel voltage Vp (i, j) via the second parasitic capacitance Cgd2. That is, the pixel voltage Vp (i, j) further decreases by the second pull-in voltage ΔVp2 (> 0) in accordance with the change of the non-corresponding adjacent scanning signal Gi-1 from the H level to the L level. Thereafter, the pixel voltage Vp (i, j) is equal to the pixel voltage Vp (i, j) = VwN (<0) immediately before the end of the main charging period until the corresponding scanning signal Gi becomes H level again in the next frame period. The voltage (VwN−ΔVp1−ΔVp2) decreased by the first pulling voltage ΔVp1 and the second pulling voltage ΔVp2 is maintained.

Here, since the first pull-in voltage ΔVp1 is determined by the voltage change amount of the gate line GLi when the corresponding scanning signal Gi changes from the H level to the L level, the first parasitic capacitance Cgd1, and the like, the forward scanning is performed. It is equal to the aforementioned pull-in voltage ΔVp in the designated case (see FIGS. 5A and 5B). Therefore, as can be seen from FIGS. 5C and 5D, when reverse scanning is designated, the pixel forming portion Px (i, j) substantially forms the pixel electrode Ep in order to form a pixel. The voltage applied to is lower by the second pull-in voltage ΔVp2 than when the forward scanning is designated.

Therefore, in the present embodiment, in order to prevent a DC component from being included in the voltage applied to the liquid crystal even when reverse scanning is specified, it is applied to the common electrode COM when reverse scanning is specified. The counter DC voltage, that is, the second counter voltage VcomB, is set to a voltage obtained by reducing the first counter voltage VcomA according to the second pull-in voltage Δp2 (> 0).

As described above, in the present embodiment, when the forward scan is designated (when the gate lines GL0 to GLN are scanned in the forward direction DirA), the counter DC voltage applied to the common electrode COM, that is, the first counter The voltage VcomA is set to a voltage value obtained by lowering the source center voltage Vcen according to the pull-in voltage ΔVp (FIGS. 5A and 5B), and reverse scanning is specified (reverse direction DirB The counter DC voltage applied to the common electrode COM when the gate lines GL0 to GLN are scanned at the same time, that is, the second counter voltage VcomB is a voltage obtained by reducing the first counter voltage VcomA according to the second pull-in voltage ΔVp2. Is set to a value (FIG. 5C and FIG. 5D). Thereby, the DC component contained in the voltage applied to the liquid crystal can be suppressed. In order to suppress the direct current component in the voltage applied to the liquid crystal in this way, more generally, the order in which the corresponding adjacent gate line is activated after the non-corresponding adjacent gate line is activated (FIG. 4). When the scanning is performed in the direction DirA), the counter DC voltage applied to the common electrode COM is set to a voltage value obtained by lowering the source center voltage Vcen according to the pull-in voltage Δp (> 0). The counter DC voltage applied to the common electrode COM when the scanning is performed in the order in which the non-corresponding adjacent gate line is activated after activation of the gate line (direction DirB in FIG. 4) is the source center voltage Vcen may be set to a voltage value reduced according to the first pull-in voltage ΔVp1 and the second pull-in voltage ΔVp2.

<1.4 Effect>
According to the present embodiment as described above, the voltage of the data signal Sj (the voltage of the source line SLj) indicating the pixel to be formed in each pixel formation portion Px (i, j) in the image to be displayed is the pixel formation. In order to apply to the pixel electrode Ep of the part Px (i, j), the corresponding gate line GLi is not only activated in one horizontal period, but also activated in the immediately preceding horizontal period (FIGS. 2 and 2). 3). That is, in each frame period, the scanning signals G0 to GN are sequentially set to the H level for every two horizontal periods at intervals of one horizontal period. (Hereinafter, driving of the gate lines GL0 to GLN by the scanning signals G0 to GN is referred to as “overlapping continuous gate pulse driving”). Further, in this embodiment, since source inversion driving is adopted as the inversion driving method of the liquid crystal panel 100 (FIGS. 2 and 3), the pixel forming portion Px in the first horizontal period of the two horizontal periods. The voltage applied to the pixel electrode Ep of (i, j) is the voltage applied to the pixel electrode Ep of the pixel formation portion Px (i, j) in the latter one horizontal period, that is, the pixel formation portion Px (i, j). The value of the voltage of the data signal Sj indicating the pixel to be formed is not necessarily the same, but the polarity is the same. For this reason, the first horizontal period of the two horizontal periods functions as a preliminary charging period. Thereby, the charging rate of the pixel capacitance Cp in each pixel forming portion Px (i, j) can be improved, and insufficient charging can be prevented even if the liquid crystal panel 100 is increased in size or resolution.

However, in the case of performing the overlapping continuous gate pulse driving as described above, as described above, the voltage to be applied to the common electrode COM (hereinafter referred to as “optimum counter DC voltage”) so that the voltage applied to the liquid crystal is correctly converted to AC Depends on the selection order of the gate lines GL0 to GLN, that is, the scanning direction (FIG. 5). On the other hand, in the present embodiment, as the counter DC voltage Vcom to be applied to the common electrode COM, the first counter voltage VcomA corresponding to the optimal counter DC voltage in the case where the forward scanning is performed and the reverse scanning are performed. The second counter voltage VcomB corresponding to the optimum counter DC voltage is generated, and when the forward scan is performed based on the direction designation signal Cud, the first counter voltage VcomA is applied to the common electrode COM, and the reverse scan is performed. Is performed, the second counter voltage VcomA is applied to the common electrode COM. As a result, the liquid crystal panel 100 is correctly AC driven so that the DC component is suppressed in the voltage applied to the liquid crystal regardless of whether the scanning is in the forward direction or the backward direction. As a result, it is possible to suppress the occurrence of flicker in the display image and prevent the deterioration of the liquid crystal, regardless of whether the scanning is in the forward direction or the backward direction.

<2. Second Embodiment>
FIG. 6 is a block diagram showing a configuration of a liquid crystal display device according to the second embodiment of the present invention. In FIG. 6, the same or corresponding components as those in the first embodiment are given the same reference numerals.

In the liquid crystal display device according to the present embodiment, as in the first embodiment, the forward scanning for activating the gate lines GLi in the order of i = 0, 1, 2,... Reverse scanning that activates in the order of N, N−1,..., 1, 0 is performed, and overlapping continuous gate pulse driving and source inversion driving are performed (FIGS. 2 and 3).

As shown in FIG. 6, the common electrode drive circuit 502 in this embodiment includes the first counter voltage generation circuit 51, but does not include the second counter voltage generation circuit, and in this respect, the first embodiment described above. This is different from the common electrode driving circuit 500 in FIG. 1 (see FIG. 1). In the present embodiment, a first counter voltage VcomA corresponding to the optimal counter DC voltage in the case of forward scanning is supplied from the first counter voltage generation circuit 51 to the changeover switch 54 as a selector in the common electrode drive circuit 502. In addition, a second counter voltage VcomB corresponding to the optimum counter DC voltage in the case of reverse scanning is applied from the outside of the liquid crystal display device. As in the case of the first embodiment, the changeover switch 54 selects the first counter voltage VcomA during forward scanning and the second counter voltage VcomB during reverse scanning. The counter DC voltage selected in this manner is applied to the common electrode COM of the liquid crystal panel 100.

Also in the present embodiment as described above, preliminary charging is performed by overlapping continuous gate pulse driving on the premise of source inversion driving, and the counter DC voltage applied to the common electrode COM corresponds to the first counter voltage according to the scanning direction. It is switched between VcomA and the second counter voltage VcomB. Therefore, according to the present embodiment, as in the first embodiment described above, insufficient charging can be prevented even when the liquid crystal panel 100 is increased in size or resolution, and both the forward scan and the reverse scan are possible. However, it is possible to suppress the occurrence of flicker in the display image and to prevent the deterioration of the liquid crystal.

In the second embodiment, the first counter voltage VcomA is generated in the liquid crystal display device (the common electrode driving circuit 502), and the second counter voltage VcomB is input from the outside of the liquid crystal display device. Instead, the first counter voltage VcomA may be input from the outside of the liquid crystal display device, and the second counter voltage VcomB may be generated in the liquid crystal display device (the common electrode drive circuit 502). Here, of the first and second counter voltages VcomA and VcomB, the counter DC voltage input from the outside has a high degree of freedom in setting the value. Therefore, considering this point, the first and second counter voltages VcomA , VcomB may be determined from the outside.

<3. Third Embodiment>
FIG. 7 is a block diagram showing a configuration of a liquid crystal display device according to the third embodiment of the present invention. In FIG. 7, the same or corresponding components as those in the first embodiment are denoted by the same reference numerals.

Similarly to the first embodiment, the liquid crystal display device according to the present embodiment scans the gate line GLi in the order of i = 0, 1, 2,... Reverse scanning that activates in the order of N, N−1,..., 1, 0 is performed, and overlapping continuous gate pulse driving and source inversion driving are performed (FIGS. 2 and 3).

As shown in FIG. 7, the common electrode driving circuit 503 in the present embodiment includes only the changeover switch 54 as a selector without including either the first counter voltage generation circuit or the second counter voltage generation circuit. In the changeover switch 54 in the present embodiment, both the first counter voltage VcomA corresponding to the optimal counter DC voltage in the case of forward scanning and the second counter voltage VcomB corresponding to the optimal counter DC voltage in the case of reverse scanning are both liquid crystal. Input from outside the display device. As in the case of the first embodiment, the changeover switch 54 selects the first counter voltage VcomA during forward scanning and the second counter voltage VcomB during reverse scanning. The counter DC voltage selected in this manner is applied to the common electrode COM of the liquid crystal panel 100.

Also in the present embodiment as described above, preliminary charging is performed by overlapping continuous gate pulse driving on the premise of source inversion driving, and the counter DC voltage applied to the common electrode COM corresponds to the first counter voltage according to the scanning direction. It is switched between VcomA and the second counter voltage VcomB. Therefore, according to the present embodiment, as in the first embodiment described above, insufficient charging can be prevented even when the liquid crystal panel 100 is increased in size or resolution, and both the forward scan and the reverse scan are possible. However, it is possible to suppress the occurrence of flicker in the display image and to prevent the deterioration of the liquid crystal. In the present embodiment, the first counter voltage VcomA corresponding to the optimum counter DC voltage in the case of forward scanning and the second counter voltage VcomB corresponding to the optimum counter DC voltage in the case of backward scanning are both external to the liquid crystal display device. Therefore, the degree of freedom in setting the value of the counter DC voltage is high in both cases of forward scanning and backward scanning. For example, according to the present embodiment, a circuit for changing the values of the first and second corresponding voltages VcomA and VcomB according to the ambient temperature of the liquid crystal display device can be provided outside.

<4. Modification>
In the first to third embodiments, preliminary charging by overlapping continuous gate pulse driving based on source inversion driving is performed, and one horizontal period immediately before the main charging period is set as the preliminary charging period (see FIG. 2 and FIG. 3), the length of the preliminary charging period is not limited to this, and for example, a preliminary charging period of two horizontal periods or more may be provided.

In the first to third embodiments, source inversion driving is adopted as the inversion driving method (FIGS. 2 and 3), but the present invention is not limited to this, and the same source is used in the same frame period. As long as the voltage polarity of the data signal Sj applied to the line SLj is the same, for example, frame inversion driving may be employed instead of source inversion driving.

In the first to third embodiments, overlapping continuous gate pulse driving is performed. However, even in a liquid crystal display device that does not perform overlapping continuous gate pulse driving, based on the structure of the liquid crystal panel, the forward scanning and the reverse direction are performed. The optimum counter DC voltage may differ between scans. Accordingly, in such a case, the values of the first counter voltage VcomA and the second counter voltage VcomB are set based on the structure of the liquid crystal panel and the voltage VcomA applied to the common electrode COM is set according to the scanning direction. And VcomB may be switched.

In the first to third embodiments, the pixel electrodes Ep of the pixel formation portions corresponding to the first gate line GL1, that is, the pixel formation portions (1, j) (j = 1 to M) in the first row. As a non-corresponding adjacent gate line, the 0th gate line GL0 is formed on the TFT substrate (FIGS. 1, 6, and 7). When the 0th gate line GL0 does not exist, each pixel formation portion (1, j) (j = 1 to M) in the first row cannot perform AC drive correctly, and the DC component is sufficient in the voltage applied to the liquid crystal. Cannot be suppressed. However, since such a problem occurs only in the pixel formation part (1, j) (j = 1 to M) in the first row, the 0th The circuit portion for generating the gate line GL0 and the scanning signal G0 corresponding thereto may be omitted.

Note that the present invention does not limit the structure or material of the thin film transistor (TFT) that constitutes the pixel circuit 110 or the like formed on the TFT substrate, and the TFT is N as in the first to third embodiments. A channel-type MOS (Metal-Oxide-Semiconductor) structure or a P-channel type MOS structure may be used. When a P-channel TFT is used as the TFT 10 in the pixel circuit 110, the gate line GLi is inactivated when the scanning signal Gi is at H level, and the gate line GLi is activated when the scanning signal Gi is at L level. It becomes a state. Therefore, the pull-in voltage generated due to the first and second parasitic capacitances Cgd1 and Cgd2 increases the pixel voltage Vp (i, j). Therefore, in this case, the first counter voltage VcomA applied to the common electrode COM when the forward scan is designated has a voltage value obtained by raising the source center voltage Vcen according to the pull-in voltage ΔVp (> 0). The second counter voltage VcomB applied to the common electrode COM when the reverse scan is set is a voltage obtained by increasing the first counter voltage VcomA according to the second pull-in voltage ΔVp2 (> 0). Will be set to the value. If this is generalized by focusing on one of the pixel electrodes (assuming that the TFT 10 as the switching element is not limited to the P-channel type or the N-channel type), the first counter voltage VcomA is determined by the corresponding adjacent gate line. The center voltage of the data signal is increased or decreased according to the voltage change amount in the corresponding adjacent gate line and the parasitic capacitance between the corresponding adjacent gate line and the pixel electrode when the active state changes to the inactive state. The second counter voltage VcomB is obtained when the non-corresponding adjacent gate line changes from the activated state to the non-activated state, and the voltage change amount in the non-corresponding adjacent gate line and the non-corresponding adjacent Obtained by increasing or decreasing the first counter voltage VcomA according to the parasitic capacitance between the gate line and the pixel electrode. It is the voltage.

In the present invention, a TFT constituting a pixel circuit or the like formed on a TFT substrate may be manufactured using, for example, amorphous silicon, polysilicon, or an oxide semiconductor. May be produced. When a TFT is manufactured using an oxide semiconductor, the channel layer is formed of InGaZnOx containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) as main components, for example. Examples of oxide semiconductors other than InGaZnOx include indium, gallium, zinc, copper (Cu), silicon (Si), tin (Sn), aluminum (Al), calcium (Ca), germanium (Ge), and lead (Pb). An oxide semiconductor containing at least one of them can be used. A TFT using such an oxide semiconductor for a channel layer has an advantage that off-leakage current is extremely small as compared with a TFT using amorphous silicon or the like for a channel layer.

In the above description, the liquid crystal display device has been described as an example. However, the present invention is not limited to this, and an active matrix type that has a common electrode and is driven by alternating current based on the voltage of the common electrode. The present invention can be applied to any display device.

The present invention can be applied to an AC drive type active matrix display device capable of switching the scanning direction, and its drive circuit and drive method.

100 ... Liquid crystal panel (display panel)
110: Pixel circuit 200: Display control circuit (control unit)
300: Source driver (data signal line driving unit)
400: Gate driver (scanning signal line driving unit)
500, 502, 503... Common electrode driving circuit (counter voltage supply unit)
10 ... Thin film transistor (switching element)
51 ... first counter voltage generation circuit 52 ... second counter voltage generation circuit 54 ... changeover switch (selector)
GLi: Gate line (scanning signal line) (i = 0 to N)
SLj: Source line (data signal line) (j = 1 to M)
COM ... Common electrode Px (i, j) ... Pixel circuit (i = 1 to N; j = 1 to M)
Ep: pixel electrode Cp: pixel capacitance Cgd1: first parasitic capacitance Cgd2: second parasitic capacitance Gi: scanning signal (i = 0 to N)
Sj: Data signal (j = 1 to M)
Vcom ... selected counter DC voltage VcomA ... first counter voltage VcomB ... second counter voltage

Claims

A plurality of data signal lines, a plurality of scanning signal lines intersecting with the plurality of data signal lines, and a plurality of pixel electrodes arranged in a matrix corresponding to the plurality of data signal lines and the plurality of scanning signal lines A common electrode disposed to face the plurality of pixel electrodes, and a control terminal provided for each pixel electrode to connect each pixel electrode to a corresponding data signal line and connected to a corresponding scanning signal line A drive circuit for a display device of an AC drive system including a switching element having
A data signal line driver that applies a plurality of data signals representing an image to be displayed to the plurality of data signal lines;
A scanning signal that sequentially activates the plurality of scanning signal lines and can switch a scanning direction corresponding to the activation order of the plurality of scanning signal lines between a first direction and a second direction that are opposite to each other. A line driver;
A counter voltage supply unit that outputs a counter voltage to be applied to the common electrode;
Select one of the first direction and the second direction as the scanning direction, and set the scanning signal line driver to activate the plurality of scanning signals in the order corresponding to the selected scanning direction. The counter voltage corresponding to the selected scanning direction is output from two different counter voltages including the first counter voltage for the first direction and the second counter voltage for the second direction. And a control unit for controlling the counter voltage supply unit.
2. The scanning signal line driving unit according to claim 1, wherein the scanning signal line driving unit drives the plurality of scanning signal lines such that periods in which adjacent scanning signal lines are activated partially overlap each other. Driving circuit.
The scanning signal line driving unit includes:
When the first direction is selected as the scanning direction, the first scanning signal connected to the control terminal of the switching element corresponding to the pixel electrode among the two scanning signal lines adjacent to each pixel electrode. Before activating the line, activate the second scanning signal line that is not connected to the control terminal of the switching element among the two scanning signal lines,
When the second direction is selected as the scanning direction, the second scanning signal line is activated after activating the first scanning signal line;
The first counter voltage includes a voltage change amount in the first scanning signal line when the first scanning signal line changes from an activated state to an inactivated state, and the first scanning signal line and the first scanning signal line. It is a voltage obtained by increasing or decreasing the center voltage of the data signal according to the parasitic capacitance between the pixel electrode,
The second counter voltage includes a voltage change amount in the second scanning signal line when the second scanning signal line changes from an activated state to an inactivated state, and the second scanning signal line and the second scanning signal line. The drive circuit according to claim 2, wherein the drive circuit is a voltage obtained by increasing or decreasing the first counter voltage according to a parasitic capacitance between the pixel electrode and the pixel electrode.
The scanning signal line drive unit displays the scanning signal line connected to the control terminal of the switching element corresponding to each pixel electrode, and the data signal indicating the pixel corresponding to the pixel electrode in the image to be displayed. In a period consisting of a main charging period to be applied to the electrode and a pre-charging period that is a predetermined period immediately before the main charging period, it is continuously activated.
4. The drive according to claim 2, wherein the data signal line driving unit generates the plurality of data signals such that the polarities of the plurality of data signals do not change within the same frame period. 5. circuit.
The counter voltage supply unit includes:
A voltage generator for generating the first and second counter voltages;
5. A selector that selects one of the first and second counter voltages as a counter voltage to be applied to the common electrode based on a control signal from the control unit. The driving circuit according to any one of the above.
At least one of the first and second counter voltages is input from the outside,
The counter voltage supply unit includes a selector that selects one of the first and second counter voltages as a counter voltage to be applied to the common electrode based on a control signal from the control unit. 5. The drive circuit according to any one of claims 1 to 4.
A display device comprising the drive circuit according to any one of claims 1 to 4.
The display device according to claim 7, wherein the switching element is a thin film transistor including a channel layer formed of an oxide semiconductor.
A plurality of data signal lines, a plurality of scanning signal lines intersecting with the plurality of data signal lines, and a plurality of pixel electrodes arranged in a matrix corresponding to the plurality of data signal lines and the plurality of scanning signal lines A common electrode arranged to face the plurality of pixel electrodes, and a control terminal provided for each pixel electrode to connect each pixel electrode to a corresponding data signal line and connected to a corresponding scanning signal line A driving method of an AC driving type display device including a switching element having,
A data signal line driving step of applying a plurality of data signals representing an image to be displayed to the plurality of data signal lines;
A scanning signal line driving step for sequentially activating the plurality of scanning signal lines;
A counter voltage supply step of outputting a counter voltage to be applied to the common electrode;
A scanning direction selection step of selecting one of a first direction and a second direction that are opposite to each other as a scanning direction corresponding to the activation order of the plurality of scanning signal lines;
In the scanning signal line driving step, the plurality of scanning signals are activated in the order corresponding to the scanning direction selected in the scanning direction selection step,
In the counter voltage supply step, the scanning direction selected in the scanning direction selection step is selected from two different counter voltages including the first counter voltage for the first direction and the second counter voltage for the second direction. A driving method, characterized in that a corresponding counter voltage is output.
10. The plurality of scanning signal lines are driven in the scanning signal line driving step so that the periods in which the adjacent scanning signal lines are activated partially overlap each other. Driving method.
In the scanning signal line driving step,
When the first direction is selected as the scanning direction, the first scanning signal connected to the control terminal of the switching element corresponding to the pixel electrode among the two scanning signal lines adjacent to each pixel electrode. Before the line is activated, the second scanning signal line that is not connected to the control terminal of the switching element is activated among the two scanning signal lines,
When the second direction is selected as the scanning direction, the second scanning signal line is activated after the first scanning signal line is activated;
The first counter voltage includes a voltage change amount in the first scanning signal line when the first scanning signal line changes from an activated state to an inactivated state, and the first scanning signal line and the first scanning signal line. It is a voltage obtained by increasing or decreasing the center voltage of the data signal according to the parasitic capacitance between the pixel electrode,
The second counter voltage includes a voltage change amount in the second scanning signal line when the second scanning signal line changes from an activated state to an inactivated state, and the second scanning signal line and the second scanning signal line. The driving method according to claim 10, wherein the driving method is a voltage obtained by increasing or decreasing the first counter voltage according to a parasitic capacitance between the pixel electrode and the pixel electrode.
In the scanning signal line driving step, the scanning signal line connected to the control terminal of the switching element corresponding to each pixel electrode receives the data signal indicating the pixel corresponding to the pixel electrode in the image to be displayed. In a period consisting of a main charging period to be applied to the electrode and a pre-charging period that is a predetermined period immediately before the main charging period, it is continuously activated.
12. The plurality of data signals are generated in the data signal line driving step so that the polarities of the plurality of data signals do not change within the same frame period. Driving method.