CN112596967B - Method, device and system for testing board card signal time sequence and server system - Google Patents
Method, device and system for testing board card signal time sequence and server system Download PDFInfo
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Abstract
The invention discloses a method, a device and a system for testing a board signal time sequence and a server system, wherein the method comprises the following steps: acquiring voltage information of a plurality of paths of signals to be detected; recording the corresponding voltage of the voltage information of the signal to be detected and the receiving time of the corresponding voltage; screening sample voltages from the corresponding voltages according to preset voltages, and acquiring the earliest receiving time of the sample voltages in the voltage information of each path of signals to be detected; and judging the time sequence of the voltage information of the multi-channel signals to be detected according to the earliest receiving time of the sample voltage corresponding to the voltage information of the multi-channel signals to be detected, and outputting and displaying the time sequence judgment result of the voltage information of the multi-channel signals to be detected. The invention can improve the test efficiency of the signal time sequence.
Description
Technical Field
The invention relates to the technical field of servers, in particular to a method, a device and a system for testing a board signal time sequence and a server system.
Background
In the server hardware test, if the abnormal function condition is met, the measurement of the time sequence of the board card signal is a common debugging direction, in the current hardware debugging process, signal point measurement is basically carried out through an oscilloscope, then whether the time sequence meets the requirement or not is judged according to the measurement result, if the time sequence does not meet the requirement, the code of a Complex Programmable Logic Device (CPLD) is modified through modification, and the measurement process is repeated after the code is modified until the server function is normal.
The existing testing method causes that research personnel can not quickly locate the problem, and needs to use the traditional testing means, such as methods of measuring signals by an oscilloscope and the like to test a hardware link, so that the efficiency is low, and the manpower is wasted. Therefore, it is desirable to provide a method for testing a board signal timing sequence, which improves the efficiency of testing the signal timing sequence.
Disclosure of Invention
The embodiment of the application provides a method, a device and a system for testing a board signal time sequence and a server system, so that the testing efficiency of the signal time sequence can be improved.
The invention provides a test method of a board signal time sequence, which comprises the following steps:
acquiring voltage information of a plurality of paths of signals to be detected;
recording the corresponding voltage of the voltage information of the signal to be detected and the receiving time of the corresponding voltage;
screening sample voltages from the corresponding voltages according to preset voltages, and acquiring the earliest receiving time of the sample voltages in the voltage information of each path of signals to be detected;
and judging the time sequence of the voltage information of the multi-channel signals to be detected according to the earliest receiving time of the sample voltage corresponding to the voltage information of the multi-channel signals to be detected, and outputting and displaying the time sequence judgment result of the voltage information of the multi-channel signals to be detected.
Preferably, the acquiring voltage information of the multiple paths of signals to be measured includes:
receiving a plurality of LVDS signals from a board card to be tested, and analyzing the plurality of LVDS signals to obtain voltage information of the signal to be tested.
Preferably, the recording the voltage corresponding to the voltage information of the signal to be measured and the receiving time of the corresponding voltage includes:
and recording the corresponding voltage of the voltage information of the signal to be detected and the receiving time of the corresponding voltage according to a preset time interval.
Preferably, the voltage value of the sample voltage is equal to the voltage value of the preset voltage.
Preferably, the determining, according to the earliest receiving time of the sample voltage corresponding to the voltage information of the multiple channels of signals to be measured, a time sequence of the voltage information of the multiple channels of signals to be measured, and outputting and displaying a time sequence determination result of the voltage information of the multiple channels of signals to be measured, includes:
and performing difference operation on the voltage information of the two paths of signals to be detected corresponding to the earliest receiving time of the sample voltage, and respectively controlling the LED lamps with different colors according to different difference operation results.
The invention also provides a testing device for the signal timing sequence of the board card, which comprises:
the first CPLD chip is used for acquiring voltage information of multiple paths of signals to be detected, recording corresponding voltage of the voltage information of the signals to be detected and receiving time of the corresponding voltage, screening sample voltage from the corresponding voltage according to preset voltage, acquiring earliest receiving time of the sample voltage in the voltage information of each path of signals to be detected, judging time sequence of the voltage information of the multiple paths of signals to be detected according to the earliest receiving time of the sample voltage corresponding to the voltage information of the multiple paths of signals to be detected, and outputting and displaying a time sequence judgment result of the voltage information of the multiple paths of signals to be detected.
Preferably, the method further comprises the following steps: a first connector;
the first CPLD chip is in communication connection with the first connector and is also used for receiving multi-path LVDS signals from a board card to be tested through the first connector and analyzing the multi-path LVDS signals to obtain voltage information of the signals to be tested.
Preferably, the first CPLD chip is configured to record, according to a preset time interval, a voltage corresponding to the voltage information of the signal to be detected and a receiving time of the corresponding voltage, perform difference operation on the voltage information of the two paths of signals to be detected corresponding to an earliest receiving time of the sample voltage, and respectively control the LEDs of different colors to light according to different difference operation results.
The invention also provides a test system of the board signal time sequence, which comprises the test device and a board to be tested which is in communication connection with the test device;
the board card to be tested is used for receiving a signal to be tested, collecting voltage information of the signal to be tested, and outputting the voltage information of the signal to be tested to the testing device.
The invention also provides a server system which comprises the testing device.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
according to the board card signal time sequence testing method, device and system and the server system, in the hardware testing process, voltage information of a plurality of paths of signals to be tested is obtained through the time sequence detection board card, the corresponding voltage of the voltage information of the signals to be tested and the receiving time of the corresponding voltage are recorded, sample voltages are screened out from the corresponding voltages according to the preset voltage, and the earliest receiving time of the sample voltages in the voltage information of each path of signals to be tested is obtained; and judging the time sequence of the voltage information of the multiple paths of signals to be detected according to the earliest receiving time of the sample voltage corresponding to the voltage information of the multiple paths of signals to be detected, and outputting and displaying the time sequence judgment result of the voltage information of the multiple paths of signals to be detected. When the timing sequence test is carried out on the signal, the timing sequence test board card is used for realizing the timing sequence test, and the signal point test is not required to be carried out through an oscilloscope, so that the damage to the board card possibly caused in the signal point test process is reduced; when a plurality of signals to be tested are tested in a time sequence mode, every two earliest receiving times corresponding to the signals to be tested are compared, a plurality of people do not need to carry out signal point test at the same time, and the labor input in the hardware testing process is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a flow chart of a method for testing the timing of a board signal according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for testing the timing of the board signal according to another embodiment of the present invention;
FIG. 3 is a timing diagram of a signal under test provided by the present invention;
FIG. 4 is a schematic block diagram of a system for testing the timing sequence of the board signal provided by the present invention;
fig. 5 is a schematic diagram of the operation of the test system for the board signal timing provided by the present invention.
Detailed Description
In order to make the present application more clearly understood by those skilled in the art to which the present application pertains, the following detailed description of the present application is made with reference to the accompanying drawings.
The invention provides a method for testing a signal timing sequence of a board card, which can be applied to a timing sequence detection board card, wherein the timing sequence detection board card comprises a first CPLD (Complex programmable logic device) chip, as shown in FIG. 1, the method comprises the following steps:
s1, acquiring voltage information of a plurality of paths of signals to be detected.
Step S1, specifically comprising:
receiving a Low-voltage differential signaling (LVDS) signal from a board card to be tested, and analyzing the LVDS signal to obtain voltage information of the signal to be tested. The time for the time sequence detection board card to receive the LVDS is almost the same as the time for the board card to be detected to receive the signal to be detected due to the high transmission efficiency of the LVDS.
The signal to be measured is, for example, an enable signal (powergood (detection logic signal of ac input voltage and dc output voltage) \ reset (reset signal) or the like. In the conventional design, the part of signals to be tested are sent or received by the second CPLD chip, while in the invention, the part of signals to be tested are transmitted to the first CPLD chip in real time for data analysis through the connector and the cable in the LVDS signal format.
And S2, recording the corresponding voltage of the voltage information of the signal to be detected and the receiving time of the corresponding voltage.
Step S2, specifically comprising:
and recording the corresponding voltage of the voltage information of the signal to be detected and the receiving time of the corresponding voltage according to the preset time interval.
S3, screening out sample voltages from the corresponding voltages according to the preset voltages, and acquiring the earliest receiving time of the sample voltages in the voltage information of each path of signals to be detected; the voltage value of the sample voltage is equal to the voltage value of the preset voltage. The voltage value of the preset voltage may be a preset standard voltage average value of the signal to be measured.
And S4, judging the time sequence of the voltage information of the multi-channel signals to be detected according to the earliest receiving time of the sample voltage corresponding to the voltage information of the multi-channel signals to be detected, and outputting and displaying the time sequence judgment result of the voltage information of the multi-channel signals to be detected.
Step S4, specifically comprising:
and performing difference operation on the voltage information of the two paths of signals to be detected corresponding to the earliest receiving time of the sample voltage, and respectively controlling the Light Emitting Diodes (LEDs) of different colors to light according to different difference operation results. That is, the voltage information of the multiple paths of signals to be measured is compared with the earliest receiving time of the sample voltage in pairs. And when the difference operation result is less than zero, controlling the LED to light a first color lamp, and when the difference operation result is more than zero, controlling the LED to light a second color lamp.
Step S4 may further include: and transmitting the difference value operation result to an upper computer through a serial port for displaying.
In another embodiment provided by the present invention, as shown in fig. 2, the board to be tested has three paths of signals to be tested net1, net2, and net3, and the timing requirements of the three paths of signals to be tested net1, net2, and net3 are as shown in fig. 3. The second CPLD chip receives the three to-be-detected signals net1, net2 and net3, converts the three to-be-detected signals net1, net2 and net3 into LVDS signals and outputs the LVDS signals to the timing sequence detection board card.
The board end of the time sequence detection board card is provided with a first connector, the board end of the board card to be detected is provided with a second connector, and the first connector and the second connector are connected through a coaxial cable.
After receiving the LVDS signals, the first CPLD chip analyzes the LVDS signals, and performs signal reduction to obtain voltage information of the three to-be-detected signals net1, net2, and net 3. The fixed time interval t is set in the first CPLD chip, voltage information corresponding to three paths of signals to be detected net1, net2 and net3 is recorded, and the time of the signal to be detected reaching each voltage value is recorded at the same time, so that the time of each signal reaching each voltage data can be recorded by nt (n =1,2,3 \8230;).
After the data acquisition and recording are finished, the first CPLD chip analyzes and processes the acquired and recorded data, and the specific steps are as follows: setting the signal standard levels to be Vs, after the timing sequence detection board card is powered on or powered on, screening the voltage information of the signals to be detected net1, net2 and net3 by the first CPLD chip, screening out the voltage equal to a preset signal standard voltage average value Vs, recording the receiving time nt (time for the timing sequence detection board card to receive the signals to be detected) of the signals to be detected corresponding to the screened voltage, if a plurality of same voltages exist in the screened voltages, selecting the earliest receiving time T1 of the signals to be detected, and similarly, acquiring the earliest receiving time T2 of the signals to be detected corresponding to the net2 to be detected and the earliest receiving time T3 of the signals to be detected corresponding to the net3 to be detected.
Calculating Δ T1= T2-T1, Δ T2= T3-T2; when the delta t1 is greater than 0, the time sequence detection board card outputs an LED1_ B _ CONTROL signal to be low, and CONTROLs an external red-blue dual-color LED1 to light a blue lamp, so that the time sequence of a signal to be detected net2 is proved to be later than that of the signal to be detected net1; when the delta t1 is less than 0, the time sequence detection board card outputs an LED1_ R _ CONTROL signal which is low, and CONTROLs an external red-blue two-color LED1 to light a red light, so that the time sequence of a signal to be detected net2 is proved to be earlier than net1. And in the same way, the lighting color of the external red and blue double-color LED2 is controlled according to the data of the delta t2, and the time sequence of net2 and net3 is judged according to the lighting color.
The calculation results delta t1 and delta t2 are transmitted to an upper computer through a serial port and are displayed through an upper computer interface, and the upper computer can be a personal computer.
The invention also provides a test device for the board signal time sequence, which comprises the following components shown in fig. 4: the device comprises a first CPLD chip 11, a first connector 12 and a display module 13. The test apparatus may be used to perform the test method described above. The first connector 12 may be an LVDS connector.
The first CPLD chip 11 is in communication connection with the first connector 12 and the display module 13, and is configured to acquire voltage information of multiple paths of signals to be measured, record corresponding voltages of the voltage information of the signals to be measured, and receive time of the corresponding voltages, further screen out sample voltages from the corresponding voltages according to preset voltages, acquire earliest receive time of the sample voltages in the voltage information of each path of signals to be measured, determine a time sequence of the voltage information of the multiple paths of signals to be measured according to the earliest receive time of the sample voltages corresponding to the voltage information of the multiple paths of signals to be measured, and output a time sequence determination result of the voltage information of the multiple paths of signals to be measured to the display module 13 for display. The display module 13 may include LED lamps that may display different colors according to different control signals. The voltage value of the sample voltage is equal to the voltage value of the preset voltage.
The first CPLD chip 11 is further configured to receive the multiple channels of LVDS signals from the board card 2 to be tested through the first connector 12, and analyze the multiple channels of LVDS signals to obtain voltage information of the signal to be tested.
Further, the first CPLD chip 11 is configured to record a corresponding voltage of the voltage information of the to-be-detected signal and a receiving time of the corresponding voltage according to a preset time interval, perform a difference operation on the voltage information of the two paths of to-be-detected signals corresponding to an earliest receiving time of the sample voltage, and respectively control the LEDs of different colors to be lit according to different difference operation results.
In a specific embodiment, as shown in fig. 5, after the data acquisition and recording are completed, the first CPLD chip 11 analyzes and processes the acquired and recorded data, and the specific steps are as follows: setting the signal standard levels to be Vs, after the timing sequence detection board card 1 is powered on or powered on, the first CPLD chip 11 screens voltage information of the signals to be detected net1, net2 and net3, screens out a voltage equal to a preset signal standard voltage average value Vs, records a signal to be detected receiving time nt (time for the timing sequence detection board card 1 to receive the signal to be detected) corresponding to the screened voltage, selects an earliest signal to be detected receiving time T1 if a plurality of identical voltages exist in the screened voltage, and similarly, obtains an earliest signal to be detected receiving time T2 corresponding to the signal to be detected net2 and an earliest signal to be detected receiving time T3 corresponding to the signal to be detected net 3.
Calculating Δ T1= T2-T1, Δ T2= T3-T2; when the delta t1 is greater than 0, the time sequence detection board card 1 outputs an LED1_ B _ CONTROL signal to be low, and CONTROLs an external red-blue dual-color LED1 to light a blue lamp, so that the time sequence of a signal to be detected net2 is proved to be later than that of the signal to be detected net1; when the delta t1 is less than 0, the time sequence detection board card 1 outputs an LED1_ R _ CONTROL signal which is low, and CONTROLs an external red-blue two-color LED1 to light a red light, so that the time sequence of the signal to be detected net2 is proved to be earlier than net1. And similarly, lighting color control is carried out on the external red and blue double-color LED2 according to the data of the delta t2, and the time sequence judgment of net2 and net3 is carried out according to the lighting color.
The invention also provides a test system of the board signal time sequence, as shown in fig. 4, the test system comprises the test device, and the board 2 to be tested and the upper computer 3 which are in communication connection with the test device.
The board card 2 to be tested is used for receiving the signal to be tested, collecting the voltage information of the signal to be tested, and outputting the voltage information of the signal to be tested to the testing device.
The timing sequence detection board card 1 is connected with the board card 2 to be detected through a coaxial cable, more specifically, the board card 2 to be detected includes a second CPLD chip 21, a first connector 12 is disposed at a board end of the timing sequence detection board card 1, a second connector 22 is disposed at a board end of the board card 2 to be detected, the second connector 22 may be an LVDS connector, and the first connector 12 is connected with the second connector 22 through a coaxial cable. The board card 2 to be tested is generally arranged inside the server.
The time sequence detection board card 1 is internally provided with a serial port 14, the first CPLD chip 11 is in communication connection with the upper computer 3 through the serial port 14, and the upper computer 3 can be used for displaying a difference value operation result calculated by the time sequence detection board card.
The invention also provides a server system which comprises the testing device.
In summary, according to the board signal timing test method, device, system and server system provided by the present invention, in the hardware test process, the timing test board 1 is used to obtain the voltage information of multiple paths of signals to be tested, record the corresponding voltage of the voltage information of the signals to be tested and the receiving time of the corresponding voltage, screen out the sample voltage from the corresponding voltage according to the preset voltage, and obtain the earliest receiving time of the sample voltage in the voltage information of each path of signals to be tested; and judging the time sequence of the voltage information of the multiple paths of signals to be detected according to the earliest receiving time of the sample voltage corresponding to the voltage information of the multiple paths of signals to be detected, and outputting and displaying the time sequence judgment result of the voltage information of the multiple paths of signals to be detected. When the signal time sequence is tested, the time sequence test board card is used for realizing the time sequence test, and the signal point test is not needed to be carried out through an oscilloscope, so that the damage to the board card possibly caused in the signal point test process is reduced; when the time sequence test of a plurality of signals to be tested is carried out, pairwise comparison is carried out on the earliest receiving time corresponding to the signals to be tested, so that the signal point test is not required to be carried out by a plurality of persons at the same time, and the manpower input in the hardware test process is reduced.
Under the condition that the requirement on the time sequence test result of the signal to be tested is rough, the time sequence can be generally evaluated only through the color of the LED lamp on the board card, the problem point is quickly positioned, and the problem solving efficiency is improved; when the LED displays, the accurate time sequence testing parameters can be displayed through the upper computer 3, and data recording in the testing process is facilitated. The CPLD chip has flexible and adjustable codes, can meet the time sequence test requirements of different signals, and is simple in connection mode with the board card 2 to be tested and strong in reusability.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. A method for testing a board signal timing sequence is characterized by comprising the following steps:
acquiring voltage information of a plurality of paths of signals to be detected;
recording the corresponding voltage of the voltage information of the signal to be detected and the receiving time of the corresponding voltage;
screening sample voltages from the corresponding voltages according to preset voltages, and acquiring the earliest receiving time of the sample voltages in the voltage information of each path of signals to be detected;
according to the earliest receiving time of the sample voltage corresponding to the voltage information of the multiple paths of signals to be detected, the time sequence of the voltage information of the multiple paths of signals to be detected is judged, and the time sequence judgment result of the voltage information of the multiple paths of signals to be detected is output and displayed, and the method comprises the following steps:
performing difference operation on the voltage information of the two paths of signals to be detected corresponding to the earliest receiving time of the sample voltage;
according to different difference operation results, the LEDs with different colors are respectively controlled to be on, and the time sequence condition is roughly judged;
the difference operation result is transmitted to the upper computer through the serial port and displayed through the upper computer, and the accurate time sequence condition display is achieved.
2. The method according to claim 1, wherein the obtaining voltage information of the plurality of paths of signals to be tested includes:
and receiving a plurality of paths of LVDS signals from a board card to be tested, and analyzing the plurality of paths of LVDS signals to obtain voltage information of the signal to be tested.
3. The method for testing the board card signal timing according to claim 1, wherein the recording of the voltage corresponding to the voltage information of the signal to be tested and the receiving time of the corresponding voltage comprises:
and recording the corresponding voltage of the voltage information of the signal to be detected and the receiving time of the corresponding voltage according to a preset time interval.
4. The method according to claim 1, wherein the voltage value of the sample voltage is equal to the voltage value of the preset voltage.
5. A test device for timing sequence of board signals is characterized by comprising:
the first CPLD chip is used for acquiring voltage information of a plurality of paths of signals to be detected, recording corresponding voltage of the voltage information of the signals to be detected and receiving time of the corresponding voltage, screening sample voltage from the corresponding voltage according to preset voltage, acquiring earliest receiving time of the sample voltage in the voltage information of each path of signals to be detected, judging time sequence of the voltage information of the plurality of paths of signals to be detected according to the earliest receiving time of the sample voltage corresponding to the voltage information of the plurality of paths of signals to be detected, and outputting and displaying a time sequence judgment result of the voltage information of the plurality of paths of signals to be detected, and comprises:
performing difference operation on the voltage information of the two paths of signals to be detected corresponding to the earliest receiving time of the sample voltage;
according to different difference operation results, the LEDs with different colors are respectively controlled to be on, and the time sequence condition is roughly judged;
the difference operation result is transmitted to the upper computer through the serial port and displayed through the upper computer, and the display of the precise time sequence condition is achieved.
6. The device for testing the timing of a board signal of claim 5, further comprising: a first connector;
the first CPLD chip is in communication connection with the first connector and is also used for receiving multi-path LVDS signals from a board card to be tested through the first connector and analyzing the multi-path LVDS signals to obtain voltage information of the signals to be tested.
7. The device for testing the timing of board signals according to claim 5, wherein the first CPLD chip is configured to record the corresponding voltage of the voltage information of the signal to be tested and the receiving time of the corresponding voltage according to a preset time interval.
8. A system for testing signal timing of a board, comprising the testing device of any one of claims 5 to 7, and a board to be tested communicatively connected to the testing device;
the board card to be tested is used for receiving a signal to be tested, collecting voltage information of the signal to be tested, and outputting the voltage information of the signal to be tested to the testing device.
9. A server system, characterized in that it comprises a testing device according to any one of claims 5-7.
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