CN112582572A

CN112582572A - Display panel, touch display screen and electronic equipment

Info

Publication number: CN112582572A
Application number: CN202011451297.5A
Authority: CN
Inventors: 盛晨
Original assignee: Kunshan New Flat Panel Display Technology Center Co Ltd
Current assignee: Kunshan New Flat Panel Display Technology Center Co Ltd
Priority date: 2020-12-09
Filing date: 2020-12-09
Publication date: 2021-03-30
Anticipated expiration: 2040-12-09
Also published as: CN112582572B

Abstract

The embodiment of the application provides a display panel, touch display screen and electronic equipment relates to and shows technical field, is located first positive pole rete on the planarization layer via hole includes with the planarization layer contact and the face towards the side that changes, when the light shines on first positive pole rete, the not equidirectional not can be arrived with light reflection to the side of different face orientations to avoid the side directional reflection light to strengthen the reverberation light intensity of planarization via hole position, with the visibility that reduces the corresponding bright line of planarization via hole position.

Description

Display panel, touch display screen and electronic equipment

Technical Field

The application relates to the technical field of display, in particular to a display panel, a touch display screen and electronic equipment.

Background

Some display panels (for example, Active-Matrix Organic Light-Emitting Diode (AMOLED) display panels) have a bright line corresponding to the position of the planarization via hole on one side of the display driving chip. Particularly, under a specific observation angle or an external strong light condition, the bright line is more obvious, which can influence the visual perception of consumers, bring about poor use experience and reduce the market competitiveness of products. How to reduce the visibility of the bright lines on the display panel is a technical problem that needs to be solved urgently by those skilled in the art.

It is noted that the information disclosed in this background section is only for enhancement of understanding of the general background of the application and should not be taken as an acknowledgement or any form of suggestion that this information constitutes prior art already known to a person skilled in the art.

Disclosure of Invention

In order to overcome the technical problems mentioned in the above technical background, embodiments of the present application provide a display panel, a touch display screen and an electronic device, which can reduce the visibility of bright lines corresponding to the positions of planarized via holes.

In a first aspect of the present application, there is provided a display screen, including:

an array substrate;

the planarization layer is positioned on the array substrate and provided with planarization layer through holes;

and manufacturing an anode film layer formed on the basis of the planarization layer, wherein the anode film layer comprises a first anode film layer positioned on the planarization layer via hole, and the first anode film layer comprises a side face which is in contact with the planarization layer and changes in face orientation.

In this scheme, first anode film layer includes and faces towards the side that changes with the planarization layer contact, and when the light shined on first anode film layer, the side of different face orientations can reflect light to different directions to avoid the side directional reflection light to strengthen the reflected light intensity of flattening same direction in via hole position department, in order to reach the visibility that reduces the corresponding bright line in flattening via hole position.

In one possible embodiment of the present application, the display panel includes a display area, a wiring area and a bonding area, the bonding area is located on a side of the display panel near to the planarization layer via hole, the wiring area is located between the bonding area and the display area, the planarization layer via hole is located in the wiring area, and an anode film layer located in the wiring area is connected to a pin of the bonding area, which provides a voltage signal;

the anode film layer of the wiring area is connected with the anode of each pixel unit in the display area through the planarization layer via hole;

the anode film layer positioned in the wiring area further comprises a second anode film layer which is not positioned on the planarization via hole, and the second anode film layer is provided with a through hole.

In this scheme, the light intensity of the reflected light is weakened by reducing the film layer area of the second anode film layer, and the visibility of the bright lines at the position of the planarized via hole can also be reduced to some extent.

In one possible embodiment of the present application, the via area includes: curvilinear regions, regions consisting of continuous annular through holes, or regions consisting of discontinuous through holes.

In one possible embodiment of the present application, the liquid crystal display further includes an antireflection film layer on the second anode film layer, wherein the antireflection film layer has a lower reflectivity to light than the anode film layer.

In the scheme, the reflectivity of the anode film layer to light can be reduced through the antireflection film layer covering the second anode film layer, the light intensity of reflected light is weakened, and the visibility of bright lines at the position of the flattened via hole can also be reduced to a certain extent.

In a second aspect of the present application, a touch display screen is further provided, which includes a display panel and a touch module,

the display panel includes:

an array substrate;

forming an anode film layer based on the planarization layer, wherein the anode film layer comprises a first anode film layer positioned on the planarization layer via hole, and the first anode film layer comprises a side face which is in contact with the planarization layer and changes in face orientation;

the touch module comprises: the touch control substrate is positioned above the display panel, and the touch control functional layer is positioned on one side, far away from the display panel, of the touch control substrate.

In one possible embodiment of the present application, the planarization layer via forms a via region on the planarization layer, the via region comprising: curvilinear regions, regions consisting of continuous annular through holes, or regions consisting of discontinuous through holes.

In one possible embodiment of the present application, the touch function layer includes touch electrode leads correspondingly located in the wiring area, and a gap between adjacent touch electrode leads varies along an extending direction of the touch electrode leads. According to the scheme, adjacent touch electrode leads can be prevented from forming gratings, the light is ensured not to generate diffraction effect after passing through the touch electrode leads in the wiring area, and bright lines cannot be formed on the anode film layer.

In a third aspect of the present application, an electronic device is further provided, where the electronic device includes the touch display screen in the second aspect.

Compared with the prior art, display panel, touch-control display screen and electronic equipment that this application embodiment provided are located first anode film layer on the planarization layer via hole includes the side that contacts and face orientation change with the planarization layer, and when the light struck was to first anode film layer, the side of different face orientations can reflect light to different directions, weakens the reverberation light intensity of planarization via hole position to reduce the visibility that the planarization via hole position corresponds the bright line.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

FIG. 1 is a schematic diagram of a multi-layer structure of a conventional touch display screen;

FIG. 2 is a schematic diagram of a multi-layer structure of a touch display screen according to a possible prior art solution;

FIG. 3 is a schematic diagram of a multi-layer structure of a touch display screen according to another possible prior art solution;

fig. 4 is a schematic diagram of a film structure of a display panel according to a first embodiment;

FIG. 5 is a schematic structural diagram of an anode film layer according to the first embodiment;

FIG. 6 is a schematic view of the structure of FIG. 5 where an emissive film layer is overlaid on the second anodic film layer;

FIG. 7 is a second schematic structural diagram of the anode layer provided in the first embodiment;

fig. 8 is a third schematic structural view illustrating an anode film layer provided in the first embodiment;

fig. 9 is a schematic view of a multi-layer structure of a touch display screen according to a second embodiment;

fig. 10 is a schematic distribution diagram of the touch electrode leads according to the second embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present application, it should be noted that the terms "upper", "lower", and the like refer to orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the application usually place when using, are only used for convenience of description and simplification of description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.

It should be noted that, in case of conflict, different features in the embodiments of the present application may be combined with each other.

In some common film stack structures of array substrates of display panels (e.g., AMOLED display panels), an uppermost layer is an anode film layer, which is a film layer where a pixel control unit (e.g., a pixel control unit of a 7-transistor 1 storage capacitor (7T1C) structure) contacts a pixel device in a display Area (Active Area, AA), and the anode film layer provides an anode voltage to the pixel device in the display Area through the pixel control unit.

Besides the above function of the anode film layer in the display area, the anode film layer in the wiring area on one side of the display driving chip also has the following two other functions.

First, the anode of each pixel unit in the display area is connected to a conductive pin of a display driver chip in the bonding area, which supplies a voltage signal, through an opening of a Planarization Layer (PLA) across a CT (Cell Test) lead and a Demux (demultiplexer) lead. Because the display screen is a current driving device, the current of a power supply line is large (generally 50 mA-200 mA), and the problem that the voltage drop is too large due to the fact that the anode film layer is designed between the CT lead and the Demux lead directly and the anode film layer is too thin is avoided. The anode film layer is arranged on the CT lead and the Demux lead in a crossing mode, so that the anode film layer has a large area, the technical problem that the anode film layer is too thin in size to cause large voltage drop can be solved, and display of the display panel is facilitated.

Secondly, the anode film layer is arranged above the CT lead wires and the Demux lead wires, and the signal interference of high-frequency driving signals of the touch module above the display panel on the CT lead wires and the Demux lead wires can be shielded.

In the prior art, in order to ensure that the anode film layer has good conductivity, an ITO/Ag/ITO composite conductive film material is often used to manufacture the anode film layer, and the anode film layer manufactured by using the material is visually bright yellow and has high light reflectivity. Meanwhile, the inventor researches and discovers that the conventional planarization layer via hole forms a via hole region on a planarization layer, wherein the via hole region is generally a linear region, so that the side surface of the anode film layer positioned on the side surface of the via hole region has a fixed surface orientation, wherein the surface orientation is the direction pointed by the normal of the finger surface. The surface faces the fixed side face and reflects incident light rays along the fixed direction, so that the light intensity of reflected light of the via hole area can be enhanced, and an obvious bright line is formed at the corresponding position of the via hole area.

In detail, referring to fig. 1, fig. 1 shows a schematic diagram of a multi-layer structure of a conventional touch display screen 10 ', where the touch display screen 10 ' may include a display panel 100 ', a touch module 200 ', a polarizer 300 ', a cover 400 ', a flexible circuit board 500 ', and a display driver chip 600 ', where the display panel 100 ', the touch module 200 ', the polarizer 300 ', and the cover 400 ' are sequentially stacked together, and one side of the display panel 100 ' is connected to the display driver chip 600 ' on the flexible circuit board 500 ' through pins. The display panel 100 'includes an anode film layer 131' on the via hole region, and the cover plate 400 'includes a cover plate ink region 410'. The distance between the cover plate ink area 410 ' and the display area AA is relatively large (generally about 200 um), and the anode film layer 131 ' located in the via hole area is relatively close to the display area AA (generally about 15 um), which results in that the cover plate ink area 410 ' cannot cover the bright line located in the via hole area, and meanwhile, the polarizer 300 ' located on the display panel 100 ' cannot completely shield the bright line located in the via hole area.

In order to solve the above technical problem, there are the following two possible solutions.

A first possible solution: referring to fig. 2, the cover plate ink region 410 'is extended to the upper side of the anode film layer 131' at the via hole region to shield the bright line formed in the via hole region.

A second possible solution is: referring to fig. 3, the anode film 131 'at the via hole region is removed and replaced with another non-metal conductive film 132' (such as an ITO film).

The inventor finds out through research that: in the first solution, the cover ink area 410 ' extending above the anode film layer 131 ' at the via hole area increases the size of the frame that is not displayed in the touch display screen 10 ', which is contrary to the market trend of increasingly narrower frames. Meanwhile, the size of the touch pattern is compressed due to the expansion of the cover ink area 410', which is not favorable for the market competitiveness of the product. And the second scheme can increase the transmission resistance of the anode film layer, cause larger voltage drop, be not beneficial to display of the display panel and influence the display effect.

In order to better solve the technical problem of the display panel with bright lines, the inventor innovatively designs the following technical scheme, which can reduce the visibility of the bright lines at the position of the flattened via hole and improve the display effect of the display panel. Specific implementations of the present application will be described in detail below with reference to the accompanying drawings.

First embodiment

Referring to fig. 4, fig. 4 is a schematic diagram illustrating a film structure of a display panel 10 according to a first embodiment of the present disclosure.

The display panel 100 provided in this embodiment may include an array substrate 110, a planarization layer 120, and an anode film layer 130.

The planarization layer 120 is disposed on the array substrate 110, and the planarization layer 120 is provided with a planarization layer via 1201.

The anode film layer 130 is formed on the planarization layer 120, the anode film layer 130 includes a first anode film layer 1301 positioned on the planarization layer via hole 1201, and the first anode film layer 1301 includes a side surface 1301a and a bottom surface 1301b, wherein the side surface 1301a of the first anode film layer is in contact with the planarization layer 120, and the bottom surface 1301b of the first anode film layer is in contact with the third metal layer M3 positioned under the planarization layer 120. The face orientation of the side surface 1301a of the first anode film layer changes along the extending direction of the bottom surface 1301b of the first anode film layer.

In the above structure, the first anode film layer 1301 on the planarization layer via hole 1201 includes the side surface 1301a that is in contact with the planarization layer 120 and has a variable surface orientation, and when light is irradiated onto the first anode film layer 1301, the side surfaces 1301a with different surface orientations reflect light to different directions, so as to prevent the side-oriented reflected light from enhancing the intensity of the reflected light at the location of the planarization via hole, and reduce the visibility of bright lines at the location of the planarization via hole.

Referring to fig. 4 again, in the present embodiment, the array substrate 110 may include a substrate 111, a buffer layer 112, and a driving layer 113.

The substrate 111 may be a glass substrate, the buffer layer 112 is located on one side of the substrate 111, and the driving layer 113 is located on one side of the buffer layer 112 away from the substrate 111. In the present embodiment, the buffer layer 112 may be made of an inorganic material, such as silicon oxide, silicon nitride, silicon oxynitride, etc. In the present embodiment, the buffer layer 112 may have a double-layer structure of a silicon nitride (SiNx) layer and a silicon oxide (SiOx) layer sequentially formed on the substrate 111.

The driving layer 113 may include an active layer 1131, a gate insulating layer 1132, a gate 1133, a source 1134, a drain 1135, a first insulating layer 1136, a second insulating layer 1137, and a first electrode 1138 and a second electrode 1139 for forming a capacitor.

The active layer 1131 is formed on the buffer layer 112 and partially covers the buffer layer 112, the active layer 1131 may be formed of an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon), an organic semiconductor, or an oxide semiconductor, and the active layer 1131 may include a source region (S), a drain region (D), and a channel region (p-si).

A gate insulating layer 1132 is formed on the active layer 1131 and the buffer layer 112 not covered by the active layer 1131 to insulate and isolate the active layer 1131 and the gate 1133. The gate insulating layer 1132 may be made of, but not limited to, silicon oxide or silicon nitride.

A gate electrode 1133 is formed on one side of the gate insulating layer 1132 at a position corresponding to the active layer 1131, and the gate electrode 1133 may be formed using one or more of metal Al, Mo, Cu, Ti, or other low resistivity metal material. Meanwhile, a first electrode 1138 of a capacitor is formed on the gate insulating layer 1132. The first electrode 1138 is formed on the gate insulating layer 1132 and partially covers the gate insulating layer 1132, the materials of the first electrode 1138 and the gate 1133 may be the same, and a first metal layer M1 may be formed on the gate insulating layer 1132, so as to achieve the purpose of simultaneously forming the gate 1133 and the first electrode 1138.

The first insulating layer 1136 is formed on the gate insulating layer 1132 and covers the gate 1133 and the first electrode 1138, and the second electrode 1139 is located on one side of the first insulating layer 1136 corresponding to the first electrode 1138. The first insulating layer 1136 serves to insulate and isolate the gate 1133 from the source 1134 and the drain 1135, and the first electrode 1138 from the second electrode 1139. The first insulating layer 1136 electrically insulates the gate electrode 1133 from the source electrode 1134 and the drain electrode 1135, respectively, and forms a capacitor between the first electrode 1138 and the second electrode 1139. The first insulating layer 1136 may also be made of inorganic materials, such as: silicon nitride and silicon oxide. The second electrode 1138 is located in a second metal layer M2 fabricated over the first insulating layer 1136.

The second insulating layer 1137 is formed on the first insulating layer 1136 and covers the second electrode 1139, for isolating the source 1134, the drain 1135 and the second electrode 1139, so that the source 1134, the drain 1135 and the second electrode 1139 are insulated from each other. The second insulating layer 1137 may also be formed of inorganic materials such as silicon nitride and silicon oxide. The second insulating layer 1137 may have a double-layer structure or a structure of three or more layers formed of silicon nitride and silicon oxide.

A source 1134 and a drain 1135 are formed on the second insulating layer 1137, the source 1134 is electrically connected to the source region (S) in the active layer 1131 through a via, and the drain 1135 is electrically connected to the drain region (D) in the active layer 1131 through a via. The electrode material of the gate 1133, the source 1134, the drain 1135, the first electrode 1138, and the second electrode 1139 may be one or more of Al, Mo, Cu, Ti, or other low resistivity metal material. The source 1134 and the drain 1135 are located in a third metal layer M3 fabricated on the second insulating layer 1137.

A planarization layer 120, an anode film layer 130 and a pixel defining layer 140 are sequentially formed on the side of the driving layer 113 away from the substrate 111. The driving layer 113 includes a TFT (Thin Film Transistor) structure formed of a gate electrode 1133, a source electrode 1134, a drain electrode 1135, an active layer 1131, and the like. The anode film layer 130 is electrically connected to the drain 1135 of the TFT through the planarization layer via 1201.

Referring to fig. 4 again, in the present embodiment, the display panel 100 may include a display area 101, a wiring area 102 and a bonding area 103. The bonding region 103 is located on a side of the display panel 100 near the side where the planarization layer via 1201 is formed, the wiring region 102 is located between the bonding region 103 and the display region 101, and the planarization layer via 1201 is located in the wiring region 102. Anode film 130 in wiring region 102 is connected to the pins of bonding area 103 that provide voltage signals. Alternatively, anode film 130 located on wiring region 102 may be connected to a pin of bonding region 103 for providing a voltage signal through a conductive wire. The display panel 100 further includes a flexible circuit board 500 and a display driving chip 600, wherein the display driving chip 600 on the flexible circuit board 500 provides a display driving signal including a voltage signal through a pin of the bonding area 103.

The anode film layer 130 of the wiring region 102 is connected to the anode of each pixel unit in the display region 101 via the planarization layer via 1201. Alternatively, the anode film layer 130 of the wiring region 102 is connected to the drain of the TFT transistor in the third metal layer M3 through the planarization layer via 1201, and the source of the TFT transistor is connected to the anode of each pixel cell in the display region 101.

In the present embodiment, the anode film layer 130 in the wiring region 102 further includes a second anode film layer 1302 not on the planarized via 1201. The inventors have also found that the surface of the second anode film layer 1302 cannot be completely planarized, and the partial reflected light of the second anode film layer 1302 also enhances the intensity of the reflected light at the position of the planarized via 1201, so as to reduce the visibility of the bright line at the position 1021 of the planarized via. The intensity of the reflected light of the second anode film 1302 can be reduced, and one possible embodiment is to reduce the area of the second anode film 1302; another possible implementation is to reduce the reflectance of light by the second anode film layer 1302.

In a first possible implementation manner, referring to fig. 5, through holes 13021 may be formed in the second anode film layer 1302, and the positions of the through holes 13021 may be randomly distributed or may be arranged according to a certain rule; the through holes 13021 may be identical in shape or different in shape. The through holes 13021 may be the same size or different sizes. In order to balance the contradiction between the area of the reflected light and the resistance, the inventor has found through research and experiments that the total area of the through holes 13021 occupies 20% to 40% of the area of the second anodic film 1302.

In a second possible implementation manner, please refer to fig. 6, the antireflection film 131 may be covered on the second anode film 1302, wherein the reflectivity of the antireflection film 131 to light is lower than the reflectivity of the second anode film 1302 to light. Optionally, the anti-reflection film 131 may be a metal film, and when the anti-reflection film is a metal film, the above scheme may be applied to other array substrate designs having a fourth metal layer, and the anti-reflection film 131 is fabricated on the second anode film 1302 at the same time as the fabrication process of the fourth metal layer, so that no additional process is added.

Referring to fig. 5-8, the planarization layer via 1201 forms a via region 121 on the planarization layer 120.

In this embodiment, there may be one or more planarization layer vias 1201. When there is one planarization layer via 1201, the area of the planarization layer via 1201 formed on the planarization layer 120 is the via area 121, as shown in fig. 5 and 6. When the planarization layer via 1201 is plural, the plural planarization layer vias 1201 constitute the via region 121. Meanwhile, if the planarization layer vias 1201 are connected to each other, the corresponding via region 121 is a connected region, as shown in fig. 7. If the plurality of planarization layer vias 1201 are spaced apart from each other, the corresponding via region 121 is a region including a plurality of discrete planarization layer vias 1201, as shown in fig. 8.

Referring to fig. 5 or fig. 6 again, in a possible implementation manner of the present embodiment, the via hole region 121 may be a curved region, the bottom surface 1301b of the first anode film layer 130 is curved, the side surface 1301a of the first anode film layer 130 curves along the bottom surface 1301b of the first anode film layer 130, and the surface orientation of the side surface 1301a is changed along the extending direction of the bottom surface 1301 b. In the above structure, the side 1301a with the changed surface orientation can reflect the incident light in the same incident direction to different directions, weaken the intensity of the reflected light in the via hole region 121, and reduce the visibility of the bright line formed in the via hole region.

Referring to fig. 7 again, in another possible implementation manner of the present embodiment, the via hole region 121 may be a region formed by a continuous annular through hole. Alternatively, the continuous annular through holes can be arranged in a line to form a bead string-like shape; the continuous annular through holes can also form a bead string shape similar to waves in an up-and-down alternating mode. In the above structure, the surface orientation of the side surface 1301a of the first anode film layer 130 formed on each annular through hole varies along the circumferential direction of the annular through hole, and when light rays in the same direction are incident on the first anode film layer 130 on the via hole region 121, the side surface 1301a may reflect the incident light rays in the same incident direction to different directions, weaken the light intensity of the reflected light of the via hole region 121, and reduce the visibility of bright lines formed in the via hole region.

Referring to fig. 8 again, in another possible implementation manner of the present embodiment, the via hole region 121 may be a region formed by discontinuous through holes. In such an embodiment, it is only necessary to ensure that the anode film layer 130 can contact the third metal layer through the discontinuous via holes. The shape of the discontinuous through holes may be square as shown in fig. 8, or may be other shapes (e.g., circular, oval, etc.), and the distribution positions of the discontinuous through holes may be staggered up and down as shown in fig. 8, may be arranged in a line, or may be arranged according to a curved track. In the above structure, the orientation of the side 1301a of the first anode film layer 130 formed at each through hole may vary with the extending direction of the edge of the through hole, and the incident light may be reflected to different directions. Meanwhile, the bottom surface 1301a of the first anode film layer has a small area compared with the bottom surface of the first anode film layer in the prior art when the first anode film layer is in contact with the third metal layer in a linear shape, the light intensity of the reflected light is weaker, and the visibility of the bright line formed in the via hole area can be reduced.

Further, when the via hole region 121 is in a non-linear structure, when the display panel 100 is bent, the bending stress is decomposed in the transverse direction and the longitudinal direction along the via hole region 121, so that the bending stress can be partially offset, which is beneficial to bending the display panel 100.

It should be understood that the foregoing embodiments are merely exemplary structures for clearly illustrating the technical solutions in the present application, and in other embodiments of the present application, the via region 121 may also have other shapes, and any shape of the via region 121 that may destroy the uniformity of the reflection angle of the first anode film layer 1301 should be included in the technical solutions in the present application, for example, the via region 121 may also be a combination of at least any two of the above-mentioned embodiments.

In the structure provided by this embodiment, the via hole region 121 formed on the planarization layer by the planarized via hole is patterned, so that the first anode film layer 130 located in the via hole region 121 has the side surface 1301a with a variable surface orientation, when light is irradiated onto the first anode film layer 130, the side surfaces 1301a with different surface orientations reflect light to different directions, thereby preventing the side-oriented reflected light from enhancing the intensity of the reflected light at the via hole region 121, and reducing the visibility of the planarized via hole region 121 corresponding to the bright line.

Second embodiment

Referring to fig. 9, the present embodiment further provides a touch display screen 10 including the display panel 100 of the first embodiment, and the structure of the touch display screen 10 provided in the present embodiment is described in detail with reference to fig. 9.

The touch display screen 10 provided in this embodiment may include a display panel 100 and a touch module 200.

Referring to fig. 4 again, the display panel 100 may include an array substrate 110, a planarization layer 120, and an anode film layer 130.

The planarization layer 120 is disposed on the array substrate 110, the planarization layer 120 is opened with a planarization layer via 1201, and the planarization layer via 1201 forms a via region 121 on the planarization layer 120.

The anode film layer 130 is formed on the planarization layer 120, the anode film layer 130 includes a first anode film layer 1301 positioned on the planarization layer via hole 1201, and the first anode film layer 1301 includes a side surface 1301a and a bottom surface 1301b, wherein the side surface 1301b of the first anode film layer is in contact with the planarization layer 120, and the bottom surface 1301b of the first anode film layer is in contact with the third metal layer M3 positioned under the planarization layer 120. The orientation of the side 1301a of the first anode film layer varies along the direction in which the bottom side 1301b of the first anode film layer extends.

The touch module 200 may include a touch substrate 210 and a touch functional layer 220, wherein the touch substrate 210 is located above the display panel 100, and the touch functional layer 220 is located on a side of the touch substrate 210 away from the display panel 100.

In this embodiment, the touch display screen 10 may further include a polarizer 300 and a cover 400, wherein the polarizer 300 is located on a side of the touch functional layer 220 away from the display panel 100, and the cover 400 is located on a side of the polarizer 300 away from the display panel 100.

Referring to fig. 9 again, in the present embodiment, the display panel 100 includes a display area 101, a wiring area 102 and a bonding area 103. Bonding area 103 is located on a side of display panel 100 where planarization layer via 1201 is formed, wiring area 102 is located between bonding area 103 and display area 101, planarization layer via 1201 is located in wiring area 102, and anode film layer 130 located in wiring area 102 is connected to a pin of bonding area 103 for providing a voltage signal. Alternatively, anode film 130 located on wiring region 102 may be connected to a pin of bonding region 103 for providing a voltage signal through a conductive wire. The display panel 100 further includes a flexible circuit board 500 and a display driving chip 600, wherein the display driving chip 600 on the flexible circuit board 500 provides a display driving signal including a voltage signal through a pin of the bonding area 103.

The anode film layer 130 of the wiring region 102 is connected to the anode of each pixel unit in the display region 101 through the planarization layer via 1201, and optionally, the anode film layer 130 of the wiring region 102 is connected to the drain of the TFT transistor in the third metal layer M3 through the planarization layer via 1201, and the source of the TFT transistor is connected to the anode of each pixel unit in the display region 101.

In the present embodiment, the anode film layer 130 in the wiring region further includes a second anode film layer 1302 not on the planarized via 1201. The inventors have also found that the surface of the second anode film layer 130 cannot be completely flat, and the partial reflected light of the second anode film layer 130 can also enhance the intensity of the reflected light at the position of the planarized via hole, in order to reduce the visibility of the bright line at the position of the planarized via hole. The intensity of the reflected light of the second anode film 1302 can be reduced, and one possible embodiment is to reduce the area of the second anode film 1302; another possible implementation is to reduce the reflectance of light by the second anode film layer 1302.

In a first possible implementation manner, please refer to fig. 5 in the first embodiment again, through holes 13021 may be formed in the second anodic film 1302, and the positions of the through holes 13021 may be randomly distributed or may be arranged according to a certain rule; the through holes 13021 may be the same or different in shape; the through holes 13021 may be the same size or different sizes. In order to balance the contradiction between the area of the reflected light and the resistance, the inventor has found through research and experiments that the total area of the through holes 13021 occupies 20% to 40% of the area of the second anodic film 1302.

In a second possible implementation manner, referring to fig. 6 again in the first embodiment, the antireflection film layer 131 may be covered on the second anode film layer 1302, wherein the reflectivity of the antireflection film layer 131 to light is lower than the reflectivity of the second anode film layer 1302 to light. Optionally, the anti-reflection film 131 may be a metal film, and when the anti-reflection film is a metal film, the above scheme may be applied to other array substrate designs having a fourth metal layer, and the anti-reflection film 131 is fabricated on the second anode film 1302 at the same time as the fabrication process of the fourth metal layer, so that no additional process is added.

Referring again to fig. 5-8 in the first embodiment, the planarization layer via 1201 forms a via region 121 on the planarization layer 120.

In this embodiment, the via hole region 121 may include: for the detailed description of the via hole region 121, reference may be made to the first embodiment, and details thereof will not be repeated.

In this embodiment, the touch function layer 220 may further include a touch electrode lead located in the wiring region 102. The inventors also found that if the incident light is diffracted, the bright line is more visible, and in order to avoid the above-mentioned defect, the inventors changed the routing manner of the touch electrode leads on the wiring region 102. Optionally, referring to fig. 10, the gap between adjacent touch electrode leads 221 in the wiring area 102 is designed to be continuously changed along the extending direction of the touch electrode leads 221, so that no grating is formed on the adjacent touch electrode leads 221. Thus, incident light can be prevented from being diffracted after passing through the touch electrode leads 221 in the wiring region, and visible bright lines are prevented from being formed on the anode film layer.

The embodiment of the present application further provides an electronic device, and the electronic device adopts the touch display screen 10 shown in the second embodiment. By adopting the electronic device of the touch display screen 10 shown in the second embodiment, the visibility of the bright line on one side of the display driving chip can be weakened, and the market competitiveness of the display device can be improved.

Through the experiment, compared with the prior art, the technical scheme provided by the application can obviously improve the visibility of the bright line to be slight or even invisible.

The embodiment of the application provides a display panel, touch-control display screen and electronic equipment, through carrying out pattern design to the via hole region that the planarization via hole formed on the planarization layer, make the first positive pole rete that is located this via hole region have the side that the face orientation changes, when the light shines on first positive pole rete, the side of different face orientations can be with light reflection to different directions, thereby avoid the reflected light intensity of side directional reflection light enhancement via hole region position, with reduce the visibility that the planarization via hole region corresponds the bright line, improve consumer's use experience, increase the market competition of product.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, comprising:

an array substrate;

2. The display panel of claim 1, wherein:

the display panel comprises a display area, a wiring area and a bonding area, wherein the bonding area is positioned on one side of the display panel close to the side provided with the planarization layer through hole, the wiring area is positioned between the bonding area and the display area, the planarization layer through hole is positioned in the wiring area, and an anode film layer positioned in the wiring area is connected with a pin for providing a voltage signal to the bonding area;

3. The display panel of claim 2,

the planarization layer via forms a via region on the planarization layer, the via region comprising: curvilinear regions, regions consisting of continuous annular through holes, or regions consisting of discontinuous through holes.

4. The display panel of claim 2 or 3, further comprising an antireflective film layer on the second anode film layer, wherein the antireflective film layer has a lower reflectivity to light than the anode film layer.

5. A touch display screen is characterized in that it comprises a display panel and a touch module,

the display panel includes:

an array substrate;

6. The touch display screen of claim 5, wherein:

7. Touch display screen according to claim 6,

8. The touch display screen of claim 7, further comprising an antireflective film layer on the second anode film layer, wherein the antireflective film layer has a lower reflectivity to light than the anode film layer.

9. The touch display screen of any one of claims 6-8, wherein:

the touch control function layer comprises touch control electrode leads correspondingly located in the wiring area, and gaps between the adjacent touch control electrode leads change along the extending direction of the touch control electrode leads.

10. An electronic device, characterized in that the electronic device comprises a touch display screen according to any one of claims 5-9.