CN112562770A - 具有测试电路的半导体装置 - Google Patents
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Abstract
本文揭示一种设备,其包含:第一半导体芯片,其包含数据I/O端子、测试端子、第一数据输入节点、第一数据输出节点、读取电路、写入电路及经配置以将从所述测试端子供应的测试数据传送到所述读取电路的测试电路;及第二半导体芯片,其包含连接到所述第一数据输出节点的第二数据输入节点、连接到所述第一数据输入节点的第二数据输出节点及存储器单元阵列。所述测试电路经配置以激活所述读取电路、所述写入电路及所述存储器单元阵列,使得所述测试数据经由所述读取电路、所述数据I/O端子、所述写入电路、所述第一数据输出节点及所述第二数据输入节点写入所述存储器单元阵列中。
Description
技术领域
背景技术
称为“HBM(高带宽存储器)”的存储器装置具有其中多个存储器核心芯片堆叠于接口芯片上的配置。在HBM的制造步骤中,执行在将存储器核心芯片堆叠于接口芯片上的状态下的操作测试,以及执行针对接口芯片的单元或存储器核心芯片的单元的操作测试。将存储器核心芯片堆叠于接口芯片上的状态下的操作测试需要经由提供于接口芯片上的外部端子来执行。然而,提供于接口芯片上的外部端子大小非常小且难以对其进行探测。因此,除一般外部端子之外,接口芯片上还提供称为“直接存取端子”的测试端子。通过将直接存取端子连接到提供于封装衬底上且大小更大的外部端子来输入或输出测试数据。在操作测试时,可操作接口芯片的输入/输出电路而不操作存储器核心芯片,或可操作存储器核心芯片而不操作接口芯片的输入/输出电路,不同于正常操作时间。
然而,当操作接口芯片的输入/输出电路而不操作存储器核心芯片时,从存储器核心芯片不产生噪声,这意味着在与不同于正常操作时间的环境的环境中测试接口芯片的输入/输出电路。类似地,当操作存储器核心芯片而不操作接口芯片的输入/输出电路时,从接口芯片的输入/输出电路不产生噪声,使得在不同于正常操作时间的环境的环境中测试存储器核心芯片。因此,需要可在操作测试中使用直接存取端子对其执行相同于正常操作时间的环境的操作环境中的操作测试的半导体装置。还需要在测试结果指示发生缺陷时将其中发生缺陷的部分分离。
发明内容
附图说明
图1是展示根据本发明的半导体装置的配置的示意图。
图2是包含于HBM中的接口芯片的电路图。
图3到6是用于解释操作测试时的测试数据流的示意图。
具体实施方式
下文将参考附图详细解释本发明的各种实施例。以下详细描述参考附图,所述附图通过说明的方式展示其中可实践本发明的特定方面及实施例。足够详细地描述这些实施例以使所属领域的技术人员能够实践本发明。可利用其它实施例,且可在不背离本发明的范围的情况下进行结构、逻辑及电改变。各种实施例必需不互斥,因为一些揭示实施例可与一或多个其它揭示实施例组合以形成新实施例。
如图1中所展示,根据本发明的半导体装置包含封装衬底1、安装于封装衬底1上的中介层2及安装于中介层2上的主机控制器3及HBM 4。封装衬底1由树脂或类似物制成,且多个凸块电极5提供于其背面上。在实际使用中,封装衬底1上的凸块电极5连接到母板(未展示)上的焊盘图案。中介层2由硅或类似物制成,且多个凸块电极6提供于其背面上。中介层2具有使主机控制器3及HBM 4彼此连接及使主机控制器3及封装衬底1彼此连接的功能。主机控制器3控制HBM 4。HBM 4具有其中堆叠接口芯片10及多个存储器核心芯片20到23的结构。尽管图1所展示的实例中将四个存储器核心芯片20到23堆叠于接口芯片10上,但堆叠存储器核心芯片的数目不受特别限制。接口芯片10及存储器核心芯片20到23与经提供以穿透半导体衬底的TSV(硅通孔)30连接。主机控制器3及HBM 4通过微凸块7连接到中介层2。微凸块7的大小非常小。HBM 4包含称为“直接存取端子”的端子。提供于HBM 4上的直接存取端子直接连接到提供于封装衬底1上的预定凸块电极8而不连接到主机控制器3。因此,可通过探测凸块电极8来直接存取HBM 4。
如图2中所展示,除数据输入/输出端子41之外,接口芯片10还包含直接存取端子42。数据输入/输出端子41接收从存储器核心芯片20到23读取的读取数据DQ及从主机控制器3供应的写入数据DQ。数据输入/输出端子41经由中介层2连接到主机控制器3。除数据输入/输出端子41之外,例如地址端子及命令端子(两者都未展示)的端子也提供于接口芯片10上且这些端子也经由中介层2连接到主机控制器3。直接存取端子42是直接连接到图1中所展示的凸块电极8的端子,且对其执行测试数据DATA的输入/输出、时钟信号CLK的输入及地址命令信号R/C的输入。将输入到直接存取端子42的测试数据DATA、时钟信号CLK及地址命令信号R/C供应到BIST(内置自测试)电路43。BIST电路43基于经由直接存取端子42输入的测试数据DATA、时钟信号CLK及地址命令信号R/C产生操作测试所需的各种信号,例如内部命令及内部地址。将由BIST电路43产生的内部命令供应到命令解码器44,且将由BIST电路43产生的内部地址供应到地址解码器45。命令解码器44对内部命令解码且与由时钟控制电路46产生的内部时钟信号同步地将解码结果供应到存储器核心芯片20到23。地址解码器45对内部地址解码且与由时钟控制电路46产生的内部时钟信号同步地将解码结果供应到存储器核心芯片20到23。时钟信号DRCLK、WCLK及WDQS从直接存取端子42或BIST电路43直接输入。时钟控制电路46输出其它时钟信号DRD及CCLK、命令解码器44的时钟信号及地址解码器45的时钟信号。基于经由直接存取端子42或BIST电路43输入的时钟信号CLK来执行由时钟控制电路46产生各种时钟信号。内部命令或内部地址可经由直接存取端子42直接输入,而无需由BIST电路43产生。
当命令信号、地址信号及时钟信号CCLK从接口芯片10供应到存储器核心芯片20到23时,存储器核心芯片20到23执行读取操作或写入操作。从存储器核心芯片20到23读取的读取数据通过TSV 31供应到接口芯片10。待写入存储器核心芯片20到23的写入数据通过TSV 31供应到存储器核心芯片20到23。从接口芯片10供应到存储器核心芯片20到23的命令信号、地址信号及时钟信号CCLK也分别通过TSV 32到34供应到存储器核心芯片20到23。
如图2中所展示,接口芯片10包含提供于TSV 31与数据输入/输出端子41之间的旁路电路50及读取电路60及提供于数据输入/输出端子41与TSV 31之间的写入电路70。旁路电路50包含选择器51及53及锁存电路52。选择器51将从TSV 31供应的读取数据及从压缩电路47供应的压缩数据中的一者供应到锁存电路52。锁存电路52响应于时钟信号DRD而锁存从选择器51供应的读取数据。选择器53将从锁存电路52供应的读取数据供应到读取电路60或直接存取端子42及BIST电路43。
读取电路60包含选择器61及63、锁存电路62及输出驱动器64。选择器61将从旁路电路50供应的读取数据及从直接存取端子42或BIST电路43供应的测试数据中的一者供应到锁存电路62。锁存电路62响应于读取时钟信号DRCLK而锁存从选择器61供应的读取数据或测试数据。如图2中所展示,锁存电路62具有其中插入一级的一个路径及其中插入二级的另一路径。因此,通过两个路径传送的读取数据或测试数据具有时间差。选择器63响应于读取时钟信号DRCLK的上升及下降而交替选择由锁存电路62构成的并行路径以执行数据的并行-串行转换。因此,将串行数据供应到输出驱动器64。输出驱动器64基于从选择器63供应的数据的逻辑电平来驱动数据输入/输出端子41。
写入电路70包含输入接收器71、锁存电路72及76及选择器73到75。输入接收器71接收供应到数据输入/输出端子41的写入数据DQ且将写入数据DQ供应到一对锁存电路72。成对锁存电路72中的一者与选通信号WDQS的上升沿同步地锁存来自输入接收器71的输出数据,且成对锁存电路72中的另一者与选通信号WDQS的下降沿同步地锁存来自输入接收器71的输出数据。因此,将从输入接收器71输出的串行数据转换成并行数据。将从锁存电路72输出的写入数据D_WDQS供应到选择器73。选择器73接收从直接存取端子42或BIST电路43供应的写入数据D_WDQS及测试数据且将数据中的任一者供应到选择器74。选择器74将从选择器73供应的数据供应到选择器75或重新映射另一端子DQ或单元。选择器75将从选择器74供应的数据或从重新映射另一端子DQ或单元供应的数据供应到锁存电路76。锁存电路76包含与延迟选通信号WDQS同步操作的先前级部分及与写入时钟信号WCLK同步操作的后续级部分,因此,与写入时钟信号WCLK同步的数据通过TSV 31供应到存储器核心芯片20到23。
首先解释实际使用中的数据流。在实际使用中,通过数据输入/输出端子41输入写入数据DQ,且通过数据输入/输出端子41输出读取数据DQ。在写入操作时,输入到数据输入/输出端子41的写入数据DQ经由写入电路70及TSV 31供应到存储器核心芯片20到23。供应到存储器核心芯片20到23的写入数据写入包含于存储器核心芯片20到23中的存储器单元阵列中。因此,在写入操作时,同时激活写入电路70及存储器核心芯片20到23。在读取操作时,从包含于存储器核心芯片20到23中的存储器单元阵列读取的读取数据DQ经由TSV 31、旁路电路50及读取电路60供应到数据输入/输出端子41。因此,在读取操作时,同时激活读取电路60及存储器核心芯片20到23。
接下来解释测试操作时的数据流。如上文描述,因为数据输入/输出端子41的平面大小非常小,所以难以在测试操作时对数据输入/输出端子41执行直接探测。因此,在测试操作时,对平面大小较大的凸块电极8执行探测,而非对数据输入/输出端子41执行探测。如图1中所展示,凸块电极8直接连接到直接存取端子42。首先,在写入操作的测试中,将从直接存取端子42或BIST电路43输入的测试数据供应到包含于读取电路60中的选择器61,如图3中所展示。在此状态下,产生读取时钟信号DRCLK、选通信号WDQS及写入时钟信号WCLK以激活读取电路60及写入电路70两者。因此,从直接存取端子42供应到选择器61的测试数据通过读取电路60、数据输入/输出端子41、写入电路70及TSV 31写入存储器核心芯片20到23。此时,因为在正常操作中类似地同时激活写入电路70及存储器核心芯片20到23,所以可在其中更准确再现正常操作中的写入操作的状态下执行操作测试。也就是说,可在同时发生来自写入电路70及存储器核心芯片20到23的电源噪声的条件下执行操作测试。此外,因为测试数据通过读取电路60及写入电路70,所以还可确认读取电路60及写入电路70是否正常操作。
接下来,在读取操作的测试中,从存储器核心芯片20到23读取的测试数据通过TSV31供应到旁路电路50,如图4中所展示。此时,包含于旁路电路50中的的选择器53选择直接存取端子42作为数据输出目的地。读取电路60(及写入电路70)也由BIST电路43操作。因此,从存储器核心芯片20到23读取的测试数据通过直接存取端子42在外部检索,且读取电路60(及写入电路70)也操作。因此,在正常操作时类似地同时激活读取电路60及存储器核心芯片20到23,使得可在其中更准确再现正常操作中的读取操作的状态下执行操作测试。也就是说,可在同时发生来自读取电路60及存储器核心芯片20到23的电源噪声的条件下执行操作测试。另外,在也操作写入电路70的情况下,可在电源噪声较严重的环境中执行测试。因此,当通过此测试时,可认为已验证比正常操作中的电源噪声的环境更严重的环境中的操作。
在读取操作的测试中,从直接存取端子42读取的测试数据经由图1中所展示的凸块电极8输入到测试器。测试器比较从存储器核心芯片20到23读取的测试数据与写入存储器核心芯片20到23的测试数据且确定两个测试数据是否匹配。当比较结果指示两个测试数据匹配时,装置被确定为无缺陷产品,而当两个测试数据不匹配时,装置被确定为有缺陷产品。
当装置被确定为有缺陷产品时,根据需要单独执行读取电路60及写入电路70的测试及存储器核心芯片20到23的测试。在读取电路60及写入电路70的测试中,将从直接存取端子42或BIST电路43输入的测试数据供应到包含于读取电路60中的选择器61,且在此状态下产生读取时钟信号DRCLK、选通信号WDQS及写入时钟WCLK以激活读取电路60及写入电路70两者,如图5中所展示。因此,从直接存取端子42供应到选择器61的测试数据通过读取电路60、数据输入/输出端子41及写入电路70。从写入电路70输出的测试数据由压缩电路47压缩以产生压缩数据。压缩数据经由旁路电路50传送到直接存取端子42或BIST电路43。因此,可通过参考从直接存取端子42输出的压缩数据而不理会写入存储器核心芯片20到23及/或从存储器核心芯片20到23读取的数据来确定读取电路60及写入电路70是否正常操作。
在存储器核心芯片20到23的测试中,将从直接存取端子42或BIST电路43输入的测试数据供应到包含于写入电路70中的选择器73,如图6中所展示。供应到选择器73的测试数据通过TSV 31写入存储器核心芯片20到23中。接下来,从存储器核心芯片20到23读取测试数据。从存储器核心芯片20到23读取的测试数据通过TSV 31供应到旁路电路50。旁路电路50将测试数据直接传送到直接存取端子42或BIST电路43,而无需将测试数据供应到读取电路60。以此方式,从直接存取端子42供应到选择器73的测试数写入存储器核心芯片20到23中而无需通过输入接收器71,且从存储器核心芯片20到23读取的测试数据从直接存取端子42读取而无需通过输出驱动器64。从直接存取端子42读取的测试数据输入到测试器且与写入存储器核心芯片20到23中的测试数据比较。在以此方式独立测试存储器核心芯片20到23的情况下,输出驱动器64及输入接收器71不操作。因此,当写入存储器核心芯片20到23中的测试数据与从存储器核心芯片20到23读取的测试数据不匹配时,可确定在存储器核心芯片20到23中存在缺陷。本发明不限于此,而是可根据测试目标使待操作的电路进行各种组合。具体来说,当要检查存储器核心芯片及接口芯片中的缺陷时,操作所有存储器核心芯片及接口芯片的读取电路及写入电路就够了。当要确定缺陷是包含于接口芯片中还是存储器核心芯片中时,防止如同上述方式使用压缩电路47来操作存储器核心芯片就够了。此外,可通过选择待操作的电路的组合来自由实现读取电路60及写入电路70是否将用作数据的路径或读取电路60及写入电路70是否将操作为电源噪声而非用作数据的路径。
如上文描述,利用根据本发明的半导体装置,可使用直接存取端子42来再现相同于正常操作时的操作条件的操作条件,且可在其中使接口芯片及存储器芯片中待测试的一部分分离的状态下执行操作测试。
尽管已在某些优选实施例及实例的上下文中揭示本发明,但所属领域的技术人员将理解,本发明超出特定揭示的实施例延伸到本发明的其它替代实施例及/或用途及其明显修改及等效物。另外,所属领域的技术人员将基于本发明来容易地明白本发明范围内的其它修改。还预期,可对实施例的特定特征及方面进行各种组合或子组合,且其仍落入本发明的范围内。应理解,所揭示实施例的各种特征及方面可彼此组合或替代以形成本发明的变化模式。因此,希望本发明的至少一些揭示内容的范围不应受上述特定揭示实施例限制。
Claims (20)
1.一种设备,其包括:
第一半导体芯片,其包含数据I/O端子、测试端子、第一数据输入节点、第一数据输出节点、经配置以将从所述第一数据输入节点供应的读取数据传送到所述数据I/O端子的读取电路、经配置以将从所述数据I/O端子供应的写入数据传送到所述第一数据输出节点的写入电路及经配置以将从所述测试端子供应的测试数据传送到所述读取电路的测试电路;及
第二半导体芯片,其包含连接到所述第一数据输出节点的第二数据输入节点、连接到所述第一数据输入节点的第二数据输出节点及连接到所述第二数据输入节点及所述第二数据输出节点的存储器单元阵列,
其中所述测试电路经配置以激活所述读取电路、所述写入电路及所述存储器单元阵列,使得所述测试数据经由所述读取电路、所述数据I/O端子、所述写入电路、所述第一数据输出节点及所述第二数据输入节点写入所述存储器单元阵列中。
2.根据权利要求1所述的设备,其进一步包括在其上安装所述第一及第二半导体芯片的封装衬底,
其中所述封装衬底包含连接到所述测试端子的外部端子,及
其中所述外部端子在大小上大于所述测试端子。
3.根据权利要求2所述的设备,其中所述测试端子具有与所述数据I/O端子相同的大小。
4.根据权利要求1所述的设备,
其中所述第二半导体芯片堆叠于所述第一半导体芯片上,
其中所述设备进一步包括连接于所述第一数据输入节点与所述第二数据输出节点之间的第一TSV及连接于所述第一数据输出节点与所述第二数据输入节点之间的第二TSV,及
其中所述第一及第二TSV中的每一者穿透所述第一及第二半导体芯片中的一者。
5.根据权利要求1所述的设备,
其中所述第一半导体芯片进一步包含连接于所述第一数据输入节点与所述读取电路之间的旁路电路,及
其中所述旁路电路经配置以将从所述数据输入节点供应的所述测试数据传送到所述测试端子。
6.根据权利要求5所述的设备,其中所述测试电路经配置以控制所述旁路电路,使得从所述存储器单元阵列读取的所述测试数据传送到所述测试端子及所述数据I/O端子两者。
7.根据权利要求1所述的设备,其中所述测试电路经配置以通过将读取时钟信号供应到所述读取电路来激活所述读取电路且通过将写入时钟信号供应到所述写入电路来激活所述写入电路。
8.根据权利要求1所述的设备,其中所述写入电路包含第一选择器,所述第一选择器经配置以选择从所述数据I/O端子供应的所述测试数据及从所述测试电路供应的所述测试数据中的一者,使得所述测试数据中的所述选定一者供应到所述第一数据输出节点。
9.根据权利要求1所述的设备,其中所述写入电路包含第二选择器,所述第二选择器经配置以将从所述数据I/O端子供应的所述测试数据供应到所述第一数据输出节点及所述测试电路中的一者。
10.根据权利要求5所述的设备,其中所述测试电路包含压缩电路,所述压缩电路经配置以在所述第一数据输出节点上压缩所述测试数据以产生压缩数据。
11.根据权利要求10所述的设备,其中所述旁路电路包含第三选择器,所述第三选择器经配置以选择从所述第一数据输入节点供应的所述测试数据及所述压缩数据中的一者。
12.一种设备,其包括:
第一半导体芯片,其包含数据I/O端子、测试端子、第一数据输入节点、经配置以驱动所述I/O端子的读取电路、经配置以将从所述第一数据输入节点供应的测试数据传送到所述读取电路及所述测试端子中的任何者的旁路电路及经配置以控制所述旁路电路的测试电路;及
第二半导体芯片,其堆叠于所述第一半导体芯片上,所述第二半导体芯片包含连接到所述第一数据输入节点的第二数据输出节点及连接到所述第二数据输出节点的存储器单元阵列,
其中所述测试电路经配置以控制所述旁路电路,使得从所述存储器单元阵列读取的所述测试数据经由所述读取电路传送到所述数据I/O端子及通过绕过所述读取电路传送到所述测试端子。
13.根据权利要求12所述的设备,其进一步包括在其上安装所述第一及第二半导体芯片的封装衬底,
其中所述封装衬底包含连接到所述测试端子的外部端子,及
其中所述外部端子在大小上大于所述测试端子。
14.根据权利要求13所述的设备,其中所述测试端子具有与所述数据I/O端子相同的大小。
15.根据权利要求12所述的设备,其进一步包括连接于所述第一数据输出节点与所述第二数据输入节点之间的TSV,
其中所述TSV穿透所述第一及第二半导体芯片中的一者。
16.根据权利要求12所述的设备,
其中所述第一半导体芯片进一步包含第一输出节点及连接于所述数据I/O端子与所述第一输出节点之间的写入电路,
其中所述第二半导体芯片进一步包含连接到所述第一输出节点的第二数据输入节点,及
其中所述测试电路经配置以激活所述读取电路、所述写入电路及所述存储器单元阵列,使得所述测试数据经由所述读取电路、所述数据I/O端子、所述写入电路、所述第一数据输出节点及所述第二数据输入节点写入所述存储器单元阵列中。
17.一种设备,其包括:
第一、第二、第三及第四外部端子;
输出驱动器电路,其具有连接到所述第一外部端子的输入节点及输出节点;
输入接收器电路,其具有连接到所述第一外部端子的输入节点及连接到所述第二外部端子的输出节点;
第一选择器电路,其具有连接到所述第三外部端子的输入节点、连接到所述第四外部端子的第一输出节点,及第二输出节点;
第二选择器电路,其具有连接到所述第一选择器电路的所述第二输出节点的第一输入节点、连接到所述第四外部端子的第二输入节点及连接到所述输出驱动器的所述输入节点的输出节点;及
测试电路,其经配置以控制所述第一及第二选择器电路,
其中所述测试电路经配置以在读取测试模式下控制所述第一选择器电路将其所述输入节点连接到其所述第一及第二输出节点两者且控制所述第二选择器电路将其所述第一输入节点连接到其所述输出节点,使得从所述第三外部端子供应的读取测试数据传送到所述第一及第四外部端子两者,及
其中所述测试电路经配置以在写入测试模式下控制所述第二选择器电路将其所述第二输入节点连接到其所述输出节点,使得从所述第四外部端子供应的写入测试数据经由所述输出驱动器及所述输入接收器电路传送到所述第二外部端子。
18.根据权利要求17所述的设备,
其中所述第一外部端子是数据I/O端子,
其中所述第二外部端子是数据输出端子,
其中所述第三外部端子是数据输入端子,及
其中所述第四外部端子是直接存取端子。
19.根据权利要求18所述的设备,其进一步包括具有连接到所述第二外部端子的数据写入端子及连接到所述第三外部端子的数据读取端子的存储器核心芯片。
20.根据权利要求19所述的设备,其进一步包括连接到所述第一及第四外部端子的中介层。
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