CN112562566A - Gate driving unit, gate driving method and display device - Google Patents
Gate driving unit, gate driving method and display device Download PDFInfo
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- CN112562566A CN112562566A CN202011456683.3A CN202011456683A CN112562566A CN 112562566 A CN112562566 A CN 112562566A CN 202011456683 A CN202011456683 A CN 202011456683A CN 112562566 A CN112562566 A CN 112562566A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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Abstract
The invention provides a gate driving unit, a gate driving method and a display device. The grid driving unit comprises a pull-down node control circuit and a pull-up node denoising circuit, wherein the pull-up node denoising circuit is electrically connected with the pull-down node, the pull-up node and the input end respectively and is used for controlling the connection or disconnection between the pull-up node and the input end under the control of the potential of the pull-down node; the pull-down node control circuit is respectively electrically connected with a first clock signal end, a pull-down node and the pull-up node, and is used for controlling the connection or disconnection between the pull-down node and the first clock signal end under the control of a first clock signal provided by the first clock signal end, and controlling the connection or disconnection between the pull-down node and the first clock signal end under the control of the potential of the pull-up node. The invention can not generate the heating of the transistor caused by short-circuit current and has the risk of burning out the transistor.
Description
Technical Field
The invention relates to the technical field of display, in particular to a gate driving unit, a gate driving method and a display device.
Background
In the conventional gate driving unit, short-circuit current is generated, so that the transistor is heated due to the short-circuit current, and the risk of burning the transistor is caused; in addition, the pull-up node and the pull-down node compete with each other, which may cause the gate driving unit to have no output.
Disclosure of Invention
The invention mainly aims to provide a gate driving unit, a gate driving method and a display device, and solves the problems that in the prior art, a transistor is heated due to short-circuit current, and the risk of burning out the transistor exists.
In order to achieve the above object, the present invention provides a gate driving unit including a pull-down node control circuit and a pull-up node noise removal circuit, wherein,
the pull-up node denoising circuit is respectively electrically connected with the pull-down node, the pull-up node and the input end and is used for controlling the connection or disconnection between the pull-up node and the input end under the control of the potential of the pull-down node;
the pull-down node control circuit is respectively electrically connected with a first clock signal end, a pull-down node and the pull-up node, and is used for controlling the connection or disconnection between the pull-down node and the first clock signal end under the control of a first clock signal provided by the first clock signal end, and controlling the connection or disconnection between the pull-down node and the first clock signal end under the control of the potential of the pull-up node.
Optionally, the gate driving unit includes an input end; the pull-up node denoising circuit comprises a first transistor;
the control electrode of the first transistor is electrically connected with the pull-down node, the first electrode of the first transistor is electrically connected with the pull-up node, and the second electrode of the first transistor is electrically connected with the input end.
Optionally, the gate driving unit includes a first scan control terminal, a second scan control terminal, a first scan voltage terminal, and a second scan voltage terminal; the pull-up node denoising circuit includes a first transistor, a second transistor, and a third transistor, wherein,
a control electrode of the first transistor is electrically connected with the pull-down node, a first electrode of the first transistor is electrically connected with the pull-up node, and a second electrode of the first transistor is electrically connected with a first electrode of the second transistor;
a control electrode of the second transistor is electrically connected to the first scan voltage terminal, a first electrode of the second transistor is electrically connected to a first electrode of the third transistor, and a second electrode of the second transistor is electrically connected to the first scan control terminal;
a control electrode of the third transistor is electrically connected with the second scanning voltage end, and a second electrode of the third transistor is electrically connected with the second scanning control end;
during forward scanning, the first scanning control end is an input end, and the second scanning control end is a reset end; during reverse scanning, the first scanning control end is a reset end, and the second scanning control end is an input end.
Optionally, the gate driving unit further includes a pull-up node control circuit;
the pull-up node control circuit is respectively electrically connected with an input end, a reset end, the pull-up node and a first voltage end, and is used for controlling the connection or disconnection between the pull-up node and the input end under the control of an input signal provided by the input end and controlling the connection or disconnection between the pull-up node and the first voltage end under the control of a reset signal provided by the reset end; alternatively, the first and second electrodes may be,
the pull-up node control circuit is respectively electrically connected with the first clock signal end, the pull-up node and the input end and is used for controlling the connection or disconnection between the pull-up node and the input end under the control of a first clock signal provided by the first clock signal end.
Optionally, the gate driving unit according to the embodiment of the present invention further includes a pull-up node control circuit;
the pull-up node control circuit is respectively electrically connected with the first scanning control end, the second scanning control end, the first scanning voltage end, the second scanning voltage end and the pull-up node, is used for controlling the connection or disconnection between the pull-up node and the first scanning voltage end under the control of a first scanning control signal provided by the first scanning control end, and is used for controlling the connection or disconnection between the pull-up node and the second scanning voltage end under the control of a second scanning control signal provided by the second scanning control end.
Optionally, the pull-down node control circuit includes a sixth transistor and a seventh transistor, wherein,
a control electrode of the sixth transistor and a first electrode of the sixth transistor are both electrically connected to the first clock signal terminal, and a second electrode of the sixth transistor is electrically connected to the pull-down node;
a control electrode of the seventh transistor is electrically connected to the pull-up node, a first electrode of the seventh transistor is electrically connected to the pull-down node, and a second electrode of the seventh transistor is electrically connected to the first clock signal terminal.
Optionally, the gate driving unit according to the embodiment of the present invention further includes a gate driving signal output terminal, a pull-up node reset circuit, a pull-down node reset circuit, and a pull-up control circuit, wherein,
the pull-up node reset circuit is respectively electrically connected with a frame reset end, the pull-up node and a first voltage end, and is used for controlling to write a first voltage signal provided by the first voltage end into the pull-up node under the control of a frame reset signal provided by the frame reset end;
the pull-down node reset circuit is respectively electrically connected with the gate drive signal output end, the pull-down node and the first voltage end, and is used for controlling the first voltage signal to be written into the pull-down node under the control of the gate drive signal output by the gate drive signal output end;
the pull-up control circuit is respectively electrically connected with the pull-up node and the grid drive signal output end and is used for controlling the potential of the pull-up node according to the grid drive signal.
Optionally, the gate driving unit further includes an output circuit and a pull-down node potential maintaining circuit; the output circuit is respectively electrically connected with the pull-up node, the pull-down node, the gate driving signal output end, a second clock signal end and a first voltage end, and is used for controlling to write a second clock signal provided by the second clock signal end into the gate driving signal output end under the control of the electric potential of the pull-up node and to write the first voltage signal into the gate driving signal output end under the control of the electric potential of the pull-down node; the pull-down node potential maintaining circuit is electrically connected with the pull-down node and is used for maintaining the potential of the pull-down node; alternatively, the first and second electrodes may be,
the grid driving unit further comprises an output circuit and a pull-down node potential maintaining circuit; the output circuit is respectively electrically connected with the pull-up node, the pull-down node, the gate driving signal output end, a second clock signal end and a second voltage end, and is used for controlling to write a second clock signal provided by the second clock signal end into the gate driving signal output end under the control of the electric potential of the pull-up node and to write a second voltage signal provided by the second voltage end into the gate driving signal output end under the control of the electric potential of the pull-down node; the pull-down node potential maintaining circuit is electrically connected with the pull-down node and is used for maintaining the potential of the pull-down node.
The invention also provides a gate driving method applied to the gate driving unit, and the gate driving method comprises the following steps:
the pull-up node denoising circuit controls the connection or disconnection between the pull-up node and the input end under the control of the potential of the pull-down node;
the pull-down node control circuit controls the pull-down node to be connected or disconnected with the first clock signal end under the control of a first clock signal provided by the first clock signal end, and controls the pull-down node to be connected or disconnected with the first clock signal end under the control of the electric potential of the pull-up node.
The invention also provides a display device, which comprises a grid drive circuit;
the gate driving circuit comprises a plurality of stages of gate driving units.
The gate driving unit, the gate driving method and the display device do not generate the risk of burning out the transistor due to heating of the transistor caused by short-circuit current, and in the input stage, the pull-up node denoising circuit controls the connection between the pull-up node and the input end under the control of the potential of the pull-down node to charge the pull-up node, and the pull-down node becomes an auxiliary node to charge the pull-up node, so that the situation that the gate driving unit has no output due to competition between the pull-up node and the pull-down node is prevented.
Drawings
Fig. 1 is a structural diagram of a gate driving unit according to at least one embodiment of the invention;
fig. 2 is a structural diagram of a gate driving unit according to at least one embodiment of the invention;
fig. 3 is a structural diagram of a gate driving unit according to at least one embodiment of the invention;
fig. 4 is a structural diagram of a gate driving unit according to at least one embodiment of the invention;
fig. 5 is a circuit diagram of a gate driving unit according to at least one embodiment of the invention;
FIG. 6 is a timing diagram illustrating the operation of the gate driving unit shown in FIG. 5 according to the present invention;
FIG. 7A is a schematic diagram illustrating the operation state of the gate driving unit shown in FIG. 5 in the first stage t1 according to the present invention;
FIG. 7B is a diagram illustrating the operation state of the gate driving unit shown in FIG. 5 in the second stage t2 according to the present invention;
fig. 7C is a schematic diagram of the operation state of the gate driving unit shown in fig. 5 in the third stage t3 according to the present invention;
FIG. 8 is a simulated operation timing diagram of the gate driving unit shown in FIG. 5 according to the present invention;
fig. 9 is a circuit diagram of a gate driving unit according to at least one embodiment of the invention;
FIG. 10 is a timing diagram illustrating the operation of the gate driving unit shown in FIG. 9 according to the present invention;
FIG. 11A is a schematic diagram illustrating the operation state of the gate driving unit shown in FIG. 9 in the first phase t1 according to the present invention;
FIG. 11B is a diagram illustrating the operation state of the gate driving unit shown in FIG. 9 during a second phase t2 according to the present invention;
fig. 11C is a schematic diagram of the operation state of the gate driving unit shown in fig. 9 in the third stage t3 according to the present invention;
FIG. 12 is a simulated operation timing diagram of the gate driving unit shown in FIG. 9 according to the present invention;
fig. 13 is a circuit diagram of a gate driving unit according to at least one embodiment of the invention;
fig. 14 is a timing diagram illustrating the operation of the gate driving unit shown in fig. 13 according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
As shown in fig. 1, the gate driving unit according to the embodiment of the present invention includes a pull-down node control circuit 11 and a pull-up node denoising circuit 12, wherein,
the pull-up node denoising circuit 12 is electrically connected with the pull-down node PD, the pull-up node PU and the Input terminal, and is configured to control the connection or disconnection between the pull-up node PU and the Input terminal under the control of the potential of the pull-down node PD;
the pull-down node control circuit 11 is electrically connected to a first clock signal terminal CLKB, a pull-down node PD, and the pull-up node PU, respectively, and is configured to control the connection or disconnection between the pull-down node PD and the first clock signal terminal CLKB under the control of a first clock signal provided by the first clock signal terminal CLKB, and to control the connection or disconnection between the pull-down node PD and the first clock signal terminal CLKB under the control of a potential of the pull-up node PU.
When the embodiment of the gate driving unit shown in fig. 1 of the present invention is in operation, when the potential of the first clock signal and the potential of the pull-up node PU are both effective voltages, since the pull-down node control circuit controls the PD to be connected to the first clock signal terminal CLKB, the transistor included in the pull-down node control circuit is turned on, but no short-circuit current is generated, and further, the risk of burning out the transistor due to the heating of the transistor caused by the short-circuit current does not occur; in addition, in the Input stage, the pull-up node denoising circuit 12 controls the connection between the pull-up node PU and the Input terminal under the control of the potential of the pull-down node PD to charge the pull-up node PU, and unlike the competition between the pull-up node PU and the pull-down node PD in the prior art, the pull-down node PD becomes an auxiliary node to charge the pull-up node PU, thereby preventing the situation that the gate driving unit has no output due to the competition between the pull-up node PU and the pull-down node PU.
According to a specific embodiment, the gate driving unit includes an input terminal; the pull-up node denoising circuit comprises a first transistor;
the control electrode of the first transistor is electrically connected with the pull-down node, the first electrode of the first transistor is electrically connected with the pull-up node, and the second electrode of the first transistor is electrically connected with the input end.
In specific implementation, when the gate driving circuit including the multi-stage gate driving unit performs unidirectional scanning, the pull-up node denoising circuit includes a first transistor, and the first transistor controls connection or disconnection between a pull-up node and an input end under the control of a pull-down node. In practical operation, the input terminal may be electrically connected to the gate driving signal output terminal of the adjacent previous gate driving unit, but is not limited thereto.
According to another specific embodiment, the gate driving unit includes a first scan control terminal, a second scan control terminal, a first scan voltage terminal, and a second scan voltage terminal; the pull-up node denoising circuit includes a first transistor, a second transistor, and a third transistor, wherein,
a control electrode of the first transistor is electrically connected with the pull-down node, a first electrode of the first transistor is electrically connected with the pull-up node, and a second electrode of the first transistor is electrically connected with a first electrode of the second transistor;
a control electrode of the second transistor is electrically connected to the first scan voltage terminal, a first electrode of the second transistor is electrically connected to a first electrode of the third transistor, and a second electrode of the second transistor is electrically connected to the first scan control terminal;
a control electrode of the third transistor is electrically connected with the second scanning voltage end, and a second electrode of the third transistor is electrically connected with the second scanning control end;
during forward scanning, the first scanning control end is an input end, and the second scanning control end is a reset end; during reverse scanning, the first scanning control end is a reset end, and the second scanning control end is an input end.
In a specific implementation, when a gate driving circuit including a plurality of stages of the gate driving units performs bidirectional scanning, the pull-up node denoising circuit includes a first transistor, a second transistor, and a third transistor;
when the gate driving circuit performs forward scanning, the second transistor is turned on, so that a second electrode of the first transistor is electrically connected to the first scanning voltage terminal;
when the gate driving circuit performs reverse scanning, the third transistor is turned on, so that the second electrode of the first transistor is electrically connected to the second scanning voltage terminal;
the first scanning voltage end is electrically connected with the grid driving signal output end of the adjacent upper-stage grid driving unit, and the second scanning voltage end is electrically connected with the grid driving signal output end of the adjacent lower-stage grid driving unit; when the gate driving circuit carries out forward scanning, the first scanning voltage end is an input end, and the second scanning voltage end is a reset end; when the gate driving circuit performs reverse scanning, the first scanning voltage end is a reset end, and the second scanning voltage end is an input end; but not limited thereto.
Optionally, as shown in fig. 2, on the basis of the embodiment of the gate driving unit shown in fig. 1, the gate driving unit according to the embodiment of the present invention further includes a pull-up node control circuit 20;
the pull-up node control circuit 20 is electrically connected to the Input terminal Input, the Reset terminal Reset, the pull-up node PU and the first voltage terminal V1, and is configured to control the connection or disconnection between the pull-up node PU and the Input terminal Input under the control of an Input signal provided by the Input terminal Input, and control the connection or disconnection between the pull-up node PU and the first voltage terminal V1 under the control of a Reset signal provided by the Reset terminal Reset.
In the embodiment of the present invention, the first voltage terminal V1 may be a low voltage terminal, but is not limited thereto.
In at least one embodiment of the present invention, the pull-up node control circuit 20 may include a fourth transistor and a fifth transistor;
a control electrode of the fourth transistor is electrically connected with a first electrode of the fourth transistor and the input end, and a second electrode of the fourth transistor is electrically connected with the pull-up node;
a control electrode of the fifth transistor is electrically connected to the reset terminal, a first electrode of the fifth transistor is electrically connected to the pull-up node, and a second electrode of the fifth transistor is electrically connected to the first voltage terminal.
In a specific implementation, when the gate driving circuit performs unidirectional scanning, the gate driving unit may further include a pull-up node control circuit, the pull-up node control circuit controls the pull-up node and the input terminal to be connected or disconnected under the control of an input signal, and the pull-up node control circuit controls the pull-up node and the first voltage terminal to be connected or disconnected under the control of the reset signal. In this case, the transistors included in the pull-up node control circuit may be n-type transistors, but not limited thereto.
Optionally, as shown in fig. 3, on the basis of the embodiment of the gate driving unit shown in fig. 1, the gate driving unit according to the embodiment of the present invention may further include a pull-up node control circuit 20;
the pull-up node control circuit 20 is electrically connected to the first clock signal terminal CLKB, the pull-up node PU, and the Input terminal, respectively, and is configured to control the connection or disconnection between the pull-up node PU and the Input terminal under the control of the first clock signal provided by the first clock signal terminal CLKB.
In at least one embodiment of the present invention, the pull-up node control circuit may include a fourth transistor;
a control electrode of the fourth transistor is electrically connected to the first clock signal terminal, a first electrode of the fourth transistor is electrically connected to the input terminal, and a second electrode of the fourth transistor is electrically connected to the pull-up node.
In specific implementation, when the gate driving circuit performs unidirectional scanning, the gate driving unit may further include a pull-up node control circuit, and the pull-up node control circuit controls connection or disconnection between the pull-up node and the input terminal under control of a first clock signal; in this case, the transistors included in the pull-up node control circuit may be p-type transistors, but not limited thereto.
In specific implementation, as shown in fig. 4, on the basis of the embodiment of the gate driving unit shown in fig. 1, the gate driving unit according to the embodiment of the present invention may further include a pull-up node control circuit 20;
the pull-up node control circuit 20 is electrically connected to the first scan control terminal S1, the second scan control terminal S2, the first scan voltage terminal CN, the second scan voltage terminal CNB, and the pull-up node PU, respectively, and is configured to control the connection or disconnection between the pull-up node PU and the first scan voltage terminal CN under the control of a first scan control signal provided by the first scan control terminal S1, and to control the connection or disconnection between the pull-up node PU and the second scan voltage terminal CNB under the control of a second scan control signal provided by the second scan control terminal S2.
In the embodiment of the present invention, S1 is electrically connected to the gate driving signal output terminal of the gate driving unit of the adjacent previous stage, and S2 is electrically connected to the gate driving signal output terminal of the gate driving unit of the adjacent next stage.
When the gate driving circuit scans in a forward direction, CN can provide a high voltage signal, and CB can provide a low voltage signal; when the gate driving circuit scans reversely, CN can provide a low voltage signal, and CB can provide a high voltage signal; but not limited thereto.
In at least one embodiment of the present invention, the pull-up node control circuit 20 may include a fourth transistor and a fifth transistor;
a control electrode of the fourth transistor is electrically connected with the first scan control terminal, a first electrode of the fourth transistor is electrically connected with the first scan voltage terminal, and a second electrode of the fourth transistor is electrically connected with the pull-up node;
the control electrode of the fifth transistor is electrically connected with the second scanning control end, the first electrode of the fifth transistor is electrically connected with the pull-up node, and the second electrode of the fifth transistor is electrically connected with the second scanning voltage end.
Optionally, the pull-down node control circuit includes a sixth transistor and a seventh transistor, wherein,
a control electrode of the sixth transistor and a first electrode of the sixth transistor are both electrically connected to the first clock signal terminal, and a second electrode of the sixth transistor is electrically connected to the pull-down node;
a control electrode of the seventh transistor is electrically connected to the pull-up node, a first electrode of the seventh transistor is electrically connected to the pull-down node, and a second electrode of the seventh transistor is electrically connected to the first clock signal terminal.
In the embodiment of the present invention, the gate driving unit further includes a gate driving signal output terminal, a pull-up node reset circuit, a pull-down node reset circuit, and a pull-up control circuit, wherein,
the pull-up node reset circuit is respectively electrically connected with a frame reset end, the pull-up node and a first voltage end, and is used for controlling to write a first voltage signal provided by the first voltage end into the pull-up node under the control of a frame reset signal provided by the frame reset end;
the pull-down node reset circuit is respectively electrically connected with the gate drive signal output end, the pull-down node and the first voltage end, and is used for controlling the first voltage signal to be written into the pull-down node under the control of the gate drive signal output by the gate drive signal output end;
the pull-up control circuit is respectively electrically connected with the pull-up node and the grid drive signal output end and is used for controlling the potential of the pull-up node according to the grid drive signal.
Optionally, the pull-up node reset circuit may include an eighth transistor;
a control electrode of the eighth transistor is electrically connected with the frame reset terminal, a first electrode of the eighth transistor is electrically connected with the pull-up node, and a second electrode of the eighth transistor is electrically connected with the first voltage terminal;
the pull-down node reset circuit may include a ninth transistor;
a control electrode of the ninth transistor is electrically connected with the gate drive signal output end, a first electrode of the ninth transistor is electrically connected with the pull-down node, and a second electrode of the ninth transistor is electrically connected with the first voltage end;
the pull-up control circuit comprises a first capacitor;
the first end of the first capacitor is electrically connected with the pull-up node, and the second end of the first capacitor is electrically connected with the gate driving signal output end.
According to a specific embodiment, the gate driving unit further includes an output circuit and a pull-down node potential maintaining circuit; the output circuit is respectively electrically connected with the pull-up node, the pull-down node, the gate driving signal output end, a second clock signal end and a first voltage end, and is used for controlling to write a second clock signal provided by the second clock signal end into the gate driving signal output end under the control of the electric potential of the pull-up node and to write the first voltage signal into the gate driving signal output end under the control of the electric potential of the pull-down node; the pull-down node potential maintaining circuit is electrically connected with the pull-down node and is used for maintaining the potential of the pull-down node.
Alternatively, the output circuit may include a tenth transistor and an eleventh transistor, wherein,
a control electrode of the tenth transistor is electrically connected with the pull-up node, a first electrode of the tenth transistor is electrically connected with the second clock signal end, and a second electrode of the tenth transistor is electrically connected with the gate drive signal output end;
a control electrode of the eleventh transistor is electrically connected with the pull-down node, a first electrode of the eleventh transistor is electrically connected with the gate drive signal output end, and a second electrode of the eleventh transistor is electrically connected with the first voltage end;
the pull-down node potential maintaining circuit comprises a second capacitor;
the first end of the second capacitor is electrically connected with the pull-down node, and the second end of the second capacitor is electrically connected with the first voltage end.
In at least one embodiment of the present invention, the first voltage terminal may be a low voltage terminal, and the driving transistor in the pixel circuit controlled by the gate driving signal generated by the gate driving unit is an n-type transistor.
According to another specific embodiment, the gate driving unit further includes an output circuit and a pull-down node potential maintaining circuit; the output circuit is respectively electrically connected with the pull-up node, the pull-down node, the gate driving signal output end, a second clock signal end and a second voltage end, and is used for controlling to write a second clock signal provided by the second clock signal end into the gate driving signal output end under the control of the electric potential of the pull-up node and to write a second voltage signal provided by the second voltage end into the gate driving signal output end under the control of the electric potential of the pull-down node; the pull-down node potential maintaining circuit is electrically connected with the pull-down node and is used for maintaining the potential of the pull-down node.
Alternatively, the output circuit may include a tenth transistor and an eleventh transistor, wherein,
a control electrode of the tenth transistor is electrically connected with the pull-up node, a first electrode of the tenth transistor is electrically connected with the second clock signal end, and a second electrode of the tenth transistor is electrically connected with the gate drive signal output end;
a control electrode of the eleventh transistor is electrically connected with the pull-down node, a first electrode of the eleventh transistor is electrically connected with the gate drive signal output end, and a second electrode of the eleventh transistor is electrically connected with the second voltage end;
the pull-down node potential maintaining circuit comprises a second capacitor;
the first end of the second capacitor is electrically connected with the pull-down node, and the second end of the second capacitor is electrically connected with the second voltage end.
In at least one embodiment of the present invention, the second voltage terminal may be a high voltage terminal, and the driving transistor in the pixel circuit controlled by the gate driving signal generated by the gate driving unit is a p-type transistor.
As shown in fig. 5, the gate driving unit according to the embodiment of the present invention includes a pull-down node control circuit 11, a pull-up node denoising circuit 12, a pull-up node control circuit 20, a gate driving signal Output end, a pull-up node reset circuit 51, a pull-down node reset circuit 52, a pull-up control circuit 53, an Output circuit 54, and a pull-down node potential maintaining circuit 55;
the pull-up node denoising circuit 12 includes a first transistor M1;
the gate of the first transistor M1 is electrically connected to a pull-down node PD, the source of the first transistor M1 is electrically connected to the pull-up node PU, and the drain of the first transistor M1 is electrically connected to the Input terminal Input;
the pull-up node control circuit 20 includes a fourth transistor M4 and a fifth transistor M5;
the gate of the fourth transistor M4 is electrically connected to the source of the fourth transistor M4 and the Input terminal Input, and the drain of the fourth transistor M4 is electrically connected to the pull-up node PU;
the gate of the fifth transistor M5 is electrically connected to the reset terminal RST, the source of the fifth transistor M5 is electrically connected to the pull-up node PU, and the drain of the fifth transistor M5 is electrically connected to the low voltage terminal; the low voltage end is used for providing a low voltage VGL;
the pull-down node control circuit 11 includes a sixth transistor M6 and a seventh transistor M7, wherein,
a gate of the sixth transistor M6 and a source of the sixth transistor M6 are both electrically connected to the first clock signal terminal CLKB, and a drain of the sixth transistor M6 is electrically connected to the pull-down node PD;
a gate of the seventh transistor M7 is electrically connected to the pull-up node PU, a source of the seventh transistor M7 is electrically connected to the pull-down node PD, and a drain of the seventh transistor M7 is electrically connected to the first clock signal terminal CLKB;
the pull-up node reset circuit 51 includes an eighth transistor M8;
a gate of the eighth transistor M8 is electrically connected to the frame reset terminal TT _ RST, a source of the eighth transistor M8 is electrically connected to the pull-up node PU, and a drain of the eighth transistor M8 is electrically connected to the low voltage terminal;
the pull-down node reset circuit 52 includes a ninth transistor M9;
a gate of the ninth transistor M9 is electrically connected to the gate driving signal Output terminal Output, a source of the ninth transistor M9 is electrically connected to the pull-down node PD, and a drain of the ninth transistor M9 is electrically connected to the low voltage terminal;
the pull-up control circuit 53 includes a first capacitor C1;
a first end of the first capacitor C1 is electrically connected to the pull-up node PU, and a second end of the first capacitor C1 is electrically connected to the gate driving signal Output terminal Output;
the output circuit 54 includes a tenth transistor M10 and an eleventh transistor M11, wherein,
a gate of the tenth transistor M10 is electrically connected to the pull-up node PU, a source of the tenth transistor M10 is electrically connected to the second clock signal terminal CLK, and a drain of the tenth transistor M10 is electrically connected to the gate driving signal Output terminal Output;
a gate of the eleventh transistor M11 is electrically connected to the pull-down node PD, a source of the eleventh transistor M11 is electrically connected to the gate driving signal Output terminal Output, and a drain of the eleventh transistor M11 is electrically connected to the low voltage terminal;
the pull-down node potential holding circuit 55 includes a second capacitor C2;
a first terminal of the second capacitor C2 is electrically connected to the pull-down node PD, and a second terminal of the second capacitor C2 is electrically connected to the low voltage terminal.
In the embodiment shown in fig. 5, all transistors are NMOS transistors (NMOS transistors), but not limited thereto.
When the embodiment of the gate driving unit shown in fig. 5 of the present invention is in operation, TT _ RST is active during the blank period between two frame display times (i.e., TT _ RST provides a high voltage signal during the blank period to turn on M8, but not limited thereto).
As shown in fig. 6, when the embodiment of the gate driving unit of the present invention shown in fig. 5 is operated,
in a first stage t1, CLK provides a low voltage, CLKB provides a high voltage, Input provides a high voltage, RST provides a low voltage, as shown in fig. 7A, M4 is turned on, M5 is turned off, the Input signal provided by Input charges PU through M4 to raise the potential of PU, M6 and M7 are both turned on, since the source of M6 is electrically connected to CLKB, and the drain of M7 is electrically connected to CLKB, the potential of PD is a high voltage at this time, and although M6 and M7 are turned on, no short-circuit current is generated; m1 is turned on, so that the Input signal provided by Input charges PU through M1 at the same time, the embodiment of the present invention is completely different from the competition of pull-up node and pull-down node in the existing gate driving unit, and the pull-down node becomes an auxiliary node for charging the pull-up node;
in the second stage t2, Input and CLKB provide low voltage, RST provides low voltage, as shown in fig. 7B, M4 and M5 are turned off, CLK provides high voltage, M10 is turned on, Output outputs high voltage, the potential of PU is coupled to higher potential by C1, M7 is kept on, the potential of PD is pulled down, since M6 is turned off, there is no path and no short-circuit current;
in the third stage t3, Input and CLK provide a low voltage, RST provides a high voltage, as shown in fig. 7C, M4 turns off, M5 turns on, the potential of PU is reset to a low voltage, CLKB provides a high voltage, M6 turns on, the first clock signal provided by CLKB charges PD to raise the potential of PD, M7 turns off, there is no path, and therefore there is no short-circuit current, M11, M1 turn on, and perform noise removal for Output and PU, respectively.
Fig. 8 is a simulated operation timing diagram of the gate driving unit shown in fig. 5 according to the present invention. In fig. 8, reference Ipd corresponds to the current of PD, and as can be seen from fig. 8, there is no constant short-circuit current throughout, except for transient currents.
In the simulation operation timing chart shown in fig. 8, the horizontal axis represents time in units of us.
As shown in fig. 9, the gate driving circuit according to the embodiment of the present invention includes a pull-down node control circuit 11, a pull-up node denoising circuit 12, a pull-up node control circuit 20, a gate driving signal Output terminal Output, a pull-up node reset circuit 51, a pull-down node reset circuit 52, a pull-up control circuit 53, an Output circuit 54, and a pull-down node potential maintaining circuit 55;
the pull-up node denoising circuit 12 includes a first transistor M1, a second transistor M2, and a third transistor M3, wherein,
the gate of the first transistor M1 is electrically connected to the pull-down node PD, the source of the first transistor M1 is electrically connected to the pull-up node PU, and the drain of the first transistor M1 is electrically connected to the source of the second transistor M2;
a gate of the second transistor M2 is electrically connected to the first scan voltage terminal CN, a source of the second transistor M2 is electrically connected to a source of the third transistor M3, and a drain of the second transistor M2 is electrically connected to the first scan control terminal S1;
a gate of the third transistor M3 is electrically connected to the second scan voltage terminal CNB, and a drain of the third transistor M3 is electrically connected to the second scan control terminal S2;
the pull-up node control circuit 20 includes a fourth transistor M4 and a fifth transistor M5;
a gate of the fourth transistor M4 is electrically connected to the first scan control terminal S1, a source of the fourth transistor M4 is electrically connected to the first scan voltage terminal CN, and a drain of the fourth transistor M4 is electrically connected to the pull-up node PU;
a gate of the fifth transistor M5 is electrically connected to the second scan control terminal S2, a source of the fifth transistor M5 is electrically connected to the pull-up node PU, and a drain of the fifth transistor M5 is electrically connected to the second scan voltage terminal CNB;
the pull-down node control circuit 11 includes a sixth transistor M6 and a seventh transistor M7, wherein,
a gate of the sixth transistor M6 and a source of the sixth transistor M6 are both electrically connected to the first clock signal terminal CLKB, and a drain of the sixth transistor M6 is electrically connected to the pull-down node PD;
a gate of the seventh transistor M7 is electrically connected to the pull-up node PU, a source of the seventh transistor M7 is electrically connected to the pull-down node PD, and a drain of the seventh transistor M7 is electrically connected to the first clock signal terminal CLKB;
the pull-up node reset circuit 51 includes an eighth transistor M8;
a gate of the eighth transistor M8 is electrically connected to the frame reset terminal TT _ RST, a source of the eighth transistor M8 is electrically connected to the pull-up node PU, and a drain of the eighth transistor M8 is electrically connected to the low voltage terminal; the low voltage end is used for providing a low voltage VGL;
the pull-down node reset circuit 52 includes a ninth transistor M9;
a gate of the ninth transistor M9 is electrically connected to the gate driving signal Output terminal Output, a source of the ninth transistor M9 is electrically connected to the pull-down node PD, and a drain of the ninth transistor M9 is electrically connected to the low voltage terminal;
the pull-up control circuit 53 includes a first capacitor C1;
a first end of the first capacitor C1 is electrically connected to the pull-up node PU, and a second end of the first capacitor C1 is electrically connected to the gate driving signal Output terminal Output.
The output circuit 54 includes a tenth transistor M10 and an eleventh transistor M11, wherein,
a gate of the tenth transistor M10 is electrically connected to the pull-up node PU, a source of the tenth transistor M10 is electrically connected to the second clock signal terminal CLK, and a drain of the tenth transistor M10 is electrically connected to the gate driving signal Output terminal Output;
a gate of the eleventh transistor M11 is electrically connected to the pull-down node PD, a source of the eleventh transistor M11 is electrically connected to the gate driving signal Output terminal Output, and a drain of the eleventh transistor M11 is electrically connected to the low voltage terminal;
the pull-down node potential holding circuit 55 includes a second capacitor C2;
a first terminal of the second capacitor C2 is electrically connected to the pull-down node PD, and a second terminal of the second capacitor C2 is electrically connected to the low voltage terminal.
In at least one embodiment of the present invention, the first voltage terminal may be a low voltage terminal, and the driving transistor in the pixel circuit controlled by the gate driving signal generated by the gate driving unit is an n-type transistor, but not limited thereto.
In the embodiment of the gate driving circuit shown in fig. 9 of the present invention, all the transistors are NMOS transistors, but not limited thereto.
In the embodiment of the gate driving circuit shown in fig. 9, during the forward direction scan, the first scan control terminal S1 is an input terminal, the second scan control terminal S2 is a reset terminal, the first scan voltage terminal CN provides a high voltage signal, and the second scan voltage terminal CNB provides a low voltage signal; in the reverse scan, the first scan control terminal S1 is a reset terminal, the second scan control terminal S2 is an input terminal, the first scan voltage terminal CN provides a low voltage signal, and the second scan voltage terminal CNB provides a high voltage signal. The embodiment of the gate driving circuit of the present invention as shown in fig. 9 can perform bidirectional scanning.
The operation process will be described by taking the forward scanning as an example of the embodiment of the gate driving circuit shown in fig. 9.
As shown in fig. 10, when the embodiment of the gate driving circuit of the present invention shown in fig. 9 is in operation,
in the first stage t1, CLK provides low voltage, CLKB provides high voltage, TT _ RST provides low voltage, S1 provides high voltage signal, S2 provides low voltage signal, as shown in fig. 11A, M4 is turned on, M5 is turned off, and the high voltage signal provided by S1 charges C1 through M4 to raise the potential of PU; since the source of M6 and the drain of M7 are both electrically connected to CLKB, the potential of PD at this time is high voltage, and no short-circuit current is generated although M6 and M7 are both on; m1 and M2 are turned on, so that the high voltage signal provided by S1 charges C1 through M1 at the same time to raise the potential of PU; m10 and M11 are turned on, Output outputs low voltage, M3 is turned off, M8 is turned off,
in the second stage t2, CLK provides high voltage, CLKB provides low voltage, S1 provides low voltage signal, S2 provides low voltage signal, TT _ RST provides low voltage, as shown in fig. 11B, M4 and M5 are turned off, M8 is turned off, M2 is turned on, M3 is turned off, M6 is turned off, the potential of PU is coupled to higher voltage, M7 is maintained on to pull down the potential of PD, there is no short circuit current because M6 is turned off without a path; m10 is turned on, M11 is turned off, Output outputs high voltage, and M9 is turned on to assist in pulling down the potential of PD;
in the third stage t3, CLK provides a low voltage, CLKB provides a high voltage, S1 provides a low voltage signal, S2 provides a high voltage signal, TT _ RST provides a low voltage, as shown in fig. 11C, M4 is turned off, M5 is turned on, and the potential of PU is reset to a low voltage; m6 is turned on to charge C2 to raise the potential of PD, M7 is turned off without a path, and thus no short-circuit current; the potential of the PD is high voltage, M11 and M1 are turned on, noise removal is carried out on the PD and the PU respectively, and the Output outputs low voltage.
In the embodiment of the gate driving circuit of the present invention shown in fig. 9, M2 is controlled by CN and M3 is controlled by CNB, so that it can be ensured that only the input signal provided by the input terminal is active and the reset signal provided by the reset terminal is masked regardless of the forward scanning or the reverse scanning.
Fig. 12 is a simulated operation timing diagram of the gate driving unit shown in fig. 9 according to the present invention. In fig. 12, reference Ipd corresponds to the current of PD, and as can be seen from fig. 12, there is no constant short-circuit current throughout, except for transient currents.
In fig. 12, the horizontal axis represents time in units of us.
As shown in fig. 13, the gate driving unit according to the embodiment of the present invention includes a pull-down node control circuit 11, a pull-up node denoising circuit 12, a pull-up node control circuit 20, a gate driving signal Output terminal Output, a pull-up control circuit 53, an Output circuit 54, and a pull-down node potential maintaining circuit 55;
the pull-up node denoising circuit 12 includes a first transistor M1;
the gate of the first transistor M1 is electrically connected to a pull-down node PD, the source of the first transistor M1 is electrically connected to the pull-up node PU, and the drain of the first transistor M1 is electrically connected to the Input terminal Input;
the pull-up node control circuit 20 includes a fourth transistor M4;
a gate of the fourth transistor M4 is electrically connected to the first clock signal terminal CLKB, a source of the fourth transistor M4 is electrically connected to the Input terminal Input, and a drain of the fourth transistor M4 is electrically connected to the pull-up node PU;
the pull-down node control circuit 11 includes a sixth transistor M6 and a seventh transistor M7, wherein,
a gate of the sixth transistor M6 and a source of the sixth transistor M6 are both electrically connected to the first clock signal terminal CLKB, and a drain of the sixth transistor M6 is electrically connected to the pull-down node PD;
a gate of the seventh transistor M7 is electrically connected to the pull-up node PU, a source of the seventh transistor M7 is electrically connected to the pull-down node PD, and a drain of the seventh transistor M7 is electrically connected to the first clock signal terminal CLKB;
the pull-up control circuit 53 includes a first capacitor C1;
a first end of the first capacitor C1 is electrically connected to the pull-up node PU, and a second end of the first capacitor C1 is electrically connected to the gate driving signal Output terminal Output;
the output circuit 54 includes a tenth transistor M10 and an eleventh transistor M11, wherein,
a gate of the tenth transistor M10 is electrically connected to the pull-up node PU, a source of the tenth transistor M10 is electrically connected to the second clock signal terminal CLK, and a drain of the tenth transistor M10 is electrically connected to the gate driving signal Output terminal Output;
a gate of the eleventh transistor M11 is electrically connected to the pull-down node PD, a source of the eleventh transistor M11 is electrically connected to the gate driving signal Output terminal Output, and a drain of the eleventh transistor M11 is electrically connected to the high voltage terminal; the high voltage end is used for providing a high voltage VGH;
the pull-down node potential holding circuit 55 includes a second capacitor C2;
a first terminal of the second capacitor C2 is electrically connected to the pull-down node PD, and a second terminal of the second capacitor C2 is electrically connected to the high voltage terminal.
In the embodiment shown in fig. 13, all transistors are PMOS transistors (P-type metal-oxide-semiconductor transistors), but not limited thereto.
In the embodiment of the present invention shown in fig. 13, the first voltage terminal may be a high voltage terminal, and the driving transistor in the pixel circuit controlled by the gate driving signal generated by the embodiment of the gate driving unit shown in fig. 13 of the present invention is a p-type transistor, but not limited thereto.
As shown in fig. 14, in operation of the embodiment of the gate driving unit of the present invention shown in fig. 13,
in the first stage t1, CLK provides a high voltage, CLKB provides a low voltage, Input provides a low voltage signal, M4 is turned on to charge C1 with the low voltage signal provided by Input, so as to pull down the potential of the pull-up node PU; m6 is on, M7 is on, and since the source of M6 and the drain of M7 are both electrically connected to CLKB, there is no short circuit current; the potential of the PD is low, M1 is turned on, and the PU is charged by the Input signal provided by the Input, the embodiment of the present invention is completely different from the competition of the pull-up node and the pull-down node in the existing gate driving unit, and the pull-down node becomes an auxiliary for charging the pull-up node; m10 and M11 are both open, Output outputs high voltage;
in the second stage t2, CLK provides a low voltage, CLKB provides a high voltage, M4 is turned off, M10 is turned on, and the potential of PU is pulled low by bootstrap C1; m6 is off, M7 is on, and there is no short circuit current since M6 is off without a path; the potential of PD is high voltage; m1 is turned off, M11 is turned off, and Output outputs low voltage;
in the third stage t3, CLK provides a high voltage, CLKB provides a low voltage, Input provides a high voltage signal, M4 is turned on, the potential of PU is reset to a high voltage, M10 and M7 are both turned off, M7 is turned off without a path, and thus no short-circuit current; m6 is on so that the potential of PD is low, M1 is on; m11 is open and Output outputs a high voltage. The gate driving method according to the embodiment of the present invention is applied to the gate driving unit, and includes:
the pull-up node denoising circuit controls the connection or disconnection between the pull-up node and the input end under the control of the potential of the pull-down node;
the pull-down node control circuit controls the pull-down node to be connected or disconnected with the first clock signal end under the control of a first clock signal provided by the first clock signal end, and controls the pull-down node to be connected or disconnected with the first clock signal end under the control of the electric potential of the pull-up node.
The display device comprises a grid drive circuit;
the gate driving circuit comprises a plurality of stages of gate driving units.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A gate driving unit includes a pull-down node control circuit and a pull-up node noise removal circuit, wherein,
the pull-up node denoising circuit is respectively electrically connected with the pull-down node, the pull-up node and the input end and is used for controlling the connection or disconnection between the pull-up node and the input end under the control of the potential of the pull-down node;
the pull-down node control circuit is respectively electrically connected with a first clock signal end, a pull-down node and the pull-up node, and is used for controlling the connection or disconnection between the pull-down node and the first clock signal end under the control of a first clock signal provided by the first clock signal end, and controlling the connection or disconnection between the pull-down node and the first clock signal end under the control of the potential of the pull-up node.
2. A gate drive unit as claimed in claim 1, wherein the gate drive unit comprises an input terminal; the pull-up node denoising circuit comprises a first transistor;
the control electrode of the first transistor is electrically connected with the pull-down node, the first electrode of the first transistor is electrically connected with the pull-up node, and the second electrode of the first transistor is electrically connected with the input end.
3. The gate driving unit of claim 1, wherein the gate driving unit comprises a first scan control terminal, a second scan control terminal, a first scan voltage terminal, and a second scan voltage terminal; the pull-up node denoising circuit includes a first transistor, a second transistor, and a third transistor, wherein,
a control electrode of the first transistor is electrically connected with the pull-down node, a first electrode of the first transistor is electrically connected with the pull-up node, and a second electrode of the first transistor is electrically connected with a first electrode of the second transistor;
a control electrode of the second transistor is electrically connected to the first scan voltage terminal, a first electrode of the second transistor is electrically connected to a first electrode of the third transistor, and a second electrode of the second transistor is electrically connected to the first scan control terminal;
a control electrode of the third transistor is electrically connected with the second scanning voltage end, and a second electrode of the third transistor is electrically connected with the second scanning control end;
during forward scanning, the first scanning control end is an input end, and the second scanning control end is a reset end; during reverse scanning, the first scanning control end is a reset end, and the second scanning control end is an input end.
4. The gate drive unit of claim 2, further comprising a pull-up node control circuit;
the pull-up node control circuit is respectively electrically connected with an input end, a reset end, the pull-up node and a first voltage end, and is used for controlling the connection or disconnection between the pull-up node and the input end under the control of an input signal provided by the input end and controlling the connection or disconnection between the pull-up node and the first voltage end under the control of a reset signal provided by the reset end; alternatively, the first and second electrodes may be,
the pull-up node control circuit is respectively electrically connected with the first clock signal end, the pull-up node and the input end and is used for controlling the connection or disconnection between the pull-up node and the input end under the control of a first clock signal provided by the first clock signal end.
5. A gate drive unit as claimed in claim 3, further comprising a pull-up node control circuit;
the pull-up node control circuit is respectively electrically connected with the first scanning control end, the second scanning control end, the first scanning voltage end, the second scanning voltage end and the pull-up node, is used for controlling the connection or disconnection between the pull-up node and the first scanning voltage end under the control of a first scanning control signal provided by the first scanning control end, and is used for controlling the connection or disconnection between the pull-up node and the second scanning voltage end under the control of a second scanning control signal provided by the second scanning control end.
6. The gate drive unit of any of claims 1 to 5, wherein the pull-down node control circuit comprises a sixth transistor and a seventh transistor, wherein,
a control electrode of the sixth transistor and a first electrode of the sixth transistor are both electrically connected to the first clock signal terminal, and a second electrode of the sixth transistor is electrically connected to the pull-down node;
a control electrode of the seventh transistor is electrically connected to the pull-up node, a first electrode of the seventh transistor is electrically connected to the pull-down node, and a second electrode of the seventh transistor is electrically connected to the first clock signal terminal.
7. The gate drive unit of any one of claims 1 to 5, further comprising a gate drive signal output terminal, a pull-up node reset circuit, a pull-down node reset circuit, and a pull-up control circuit, wherein,
the pull-up node reset circuit is respectively electrically connected with a frame reset end, the pull-up node and a first voltage end, and is used for controlling to write a first voltage signal provided by the first voltage end into the pull-up node under the control of a frame reset signal provided by the frame reset end;
the pull-down node reset circuit is respectively electrically connected with the gate drive signal output end, the pull-down node and the first voltage end, and is used for controlling the first voltage signal to be written into the pull-down node under the control of the gate drive signal output by the gate drive signal output end;
the pull-up control circuit is respectively electrically connected with the pull-up node and the grid drive signal output end and is used for controlling the potential of the pull-up node according to the grid drive signal.
8. The gate drive unit of claim 7, further comprising an output circuit and a pull-down node potential maintenance circuit; the output circuit is respectively electrically connected with the pull-up node, the pull-down node, the gate driving signal output end, a second clock signal end and a first voltage end, and is used for controlling to write a second clock signal provided by the second clock signal end into the gate driving signal output end under the control of the electric potential of the pull-up node and to write the first voltage signal into the gate driving signal output end under the control of the electric potential of the pull-down node; the pull-down node potential maintaining circuit is electrically connected with the pull-down node and is used for maintaining the potential of the pull-down node; alternatively, the first and second electrodes may be,
the grid driving unit further comprises an output circuit and a pull-down node potential maintaining circuit; the output circuit is respectively electrically connected with the pull-up node, the pull-down node, the gate driving signal output end, a second clock signal end and a second voltage end, and is used for controlling to write a second clock signal provided by the second clock signal end into the gate driving signal output end under the control of the electric potential of the pull-up node and to write a second voltage signal provided by the second voltage end into the gate driving signal output end under the control of the electric potential of the pull-down node; the pull-down node potential maintaining circuit is electrically connected with the pull-down node and is used for maintaining the potential of the pull-down node.
9. A gate driving method applied to the gate driving unit as claimed in any one of claims 1 to 8, the gate driving method comprising:
the pull-up node denoising circuit controls the connection or disconnection between the pull-up node and the input end under the control of the potential of the pull-down node;
the pull-down node control circuit controls the pull-down node to be connected or disconnected with the first clock signal end under the control of a first clock signal provided by the first clock signal end, and controls the pull-down node to be connected or disconnected with the first clock signal end under the control of the electric potential of the pull-up node.
10. A display device is characterized by comprising a gate driving circuit;
the gate driving circuit includes a plurality of stages of gate driving units as claimed in any one of claims 1 to 8.
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