CN112558921A

CN112558921A - Device and method for realizing cross-correlation operation

Info

Publication number: CN112558921A
Application number: CN202011545988.1A
Authority: CN
Inventors: 宋桂童; 刘贵林; 周成龙; 闫冬; 汤博先; 虞连贵; 李尚严; 杨文轩
Original assignee: Gowin Semiconductor Corp
Current assignee: Gowin Semiconductor Corp
Priority date: 2020-12-23
Filing date: 2020-12-23
Publication date: 2021-03-26
Anticipated expiration: 2040-12-23
Also published as: CN112558921B

Abstract

The application provides a device and a method for realizing cross-correlation operation, wherein the device comprises: the device comprises a delay time generating circuit, a data reading circuit and a multiplication accumulator; a delay time generation circuit configured to determine more than one delay value and send each delay value to the data reading circuit; a data reading circuit configured to determine first data based on each delay value and the first signal sequence received, determine second data based on each delay value and the second signal sequence received, and output the first data and the second data to the multiplier-accumulator; and the multiplication accumulator is arranged to obtain the cross-correlation value of the first signal sequence and the second signal sequence at each delay value according to the first data and the second data output by the data reading circuit. According to the technical scheme, the cross-correlation calculation of different delays can be realized through the delay time generation circuit and the data reading circuit, and the complexity of the cross-correlation calculation of different delays is effectively reduced.

Description

Device and method for realizing cross-correlation operation

Technical Field

The present invention relates to, but not limited to, the field of computers, and more particularly, to an apparatus and method for performing cross-correlation operations.

Background

An FPGA (Field Programmable Gate Array) can be repeatedly programmed for an unlimited number of times, thereby reducing the overhead of hardware. In digital circuits, there are some complex functional blocks that can be repeatedly used, so in order to reduce the repetitive labor of designers, an IP Core (Intellectual Property Core), i.e., an Intellectual Property Core, has come into play. The designer can realize the required functions by calling the IP core without self-design, so that the designer can realize complex functions in a short time and improve the quality of design.

Cross-correlation (CrossCorrelation) indicates the degree of correlation between two signal sequences. There are many applications that require cross-correlation to determine the correlation between two signal sequences, such as echo cancellation, sound direction determination, oil pipeline breakage position determination, etc., so cross-correlation IP cores have been designed. However, the existing method for calculating the cross-correlation of the sequences is complex.

Disclosure of Invention

The technology to be solved by the application is to provide a device and a method for realizing cross-correlation operation, which can reduce the complexity of cross-correlation calculation with different delays.

In order to solve the above technical problem, the present application provides an apparatus for implementing a cross-correlation operation, including: the device comprises a delay time generating circuit, a data reading circuit and a multiplication accumulator;

the delay time generating circuit is set to determine more than one delay value and send each delay value to the data reading circuit;

the data reading circuit is arranged to determine first data according to each delay value and first signal sequence received, determine second data according to each delay value and second signal sequence received, and output the first data and the second data to the multiplication accumulator;

and the multiplication accumulator is arranged to obtain the cross-correlation value of the first signal sequence and the second signal sequence at each delay value according to the first data and the second data output by the data reading circuit.

In one illustrative example, the data reading circuit includes a first address generation module, a first data output module, a second address generation module, and a second data output module;

the first address generation module is configured to receive the delay value sent by the delay time generation circuit; determining first state information according to the received delay value, or the received delay value and second state information sent by the second address generation module, and sending the first state information to the first data output module; wherein the first state information includes: the first address generation module generates address information and first mark information used for identifying an address which starts to be generated by the first address generation module, or first control information used for identifying an address which does not start to be generated by the first address generation module, or first end information used for identifying that data reading of the first signal sequence corresponding to the current delay value is finished;

the second address generation module is configured to receive the delay value sent by the delay time generation circuit; determining second state information according to the received delay value, or the received delay value and the first state information sent by the first address generation module, and sending the second state information to the second data output module; wherein the second state information includes: the address information generated by the second address generation module and second flag information used for identifying that the second address generation module starts generating an address, or second control information used for identifying that the second address generation module does not start generating an address, or second end information used for identifying that data reading of the second signal sequence corresponding to the current delay value is finished;

the first data output module is configured to determine the first data according to the received first state information and the first signal sequence stored in the first data output module, and output the first data to the multiplication accumulator;

and the second data output module is configured to determine the second data according to the received second state information and the second signal sequence stored in the second data output module, and output the second data to the multiplication accumulator.

In one illustrative example, the first address generation module includes a first judgment sub-circuit and a first address generator; the second address generation module comprises a second judgment sub-circuit and a second address generator;

the first judging sub-circuit is set to determine the sequence of starting generating addresses by the first address generator and the second address generator under the delay value according to the received delay value; when the first address generator is determined to generate an address first, the first mark information is sent to the first address generator and the first data output module; when the data reading of the first signal sequence corresponding to the delay value is finished, the first end information is sent to the first address generator and the first data output module; when an address is generated after the first address generator is determined, sending the first control information to the first address generator and the first data output module before sending the first flag information to the first address generator;

the first address generator is configured to start generating an address when the first flag information sent by the first judgment sub-circuit is received, and send the generated address information to the first data output module, so that the first data output module reads data from the first signal sequence according to the address information;

the second judgment sub-circuit is set to determine the sequence of the second address generator and the first address generator starting to generate addresses according to the received delay value; when the second address generator is determined to generate an address first, the second mark information is sent to the second address generator and the second data output module; when the data reading of the second signal sequence corresponding to the delay value is finished, sending the second end information to the second address generator and the second data output module; when the address is generated after the second address generator is determined, sending the second control information to the second address generator and the second data output module before sending the second flag information to the second address generator;

the second address generator is configured to start generating an address when receiving the second flag information sent by the second judgment sub-circuit, and send the generated address information to the second data output module, so that the second data output module reads data from the second signal sequence according to the address information.

It should be noted that the first flag information is information for identifying that the first address generator starts generating an address, and in other embodiments, information with other names may also be used for identifying that the first address generator starts generating an address, and the first flag information is an exemplary name in this embodiment. Similar to the first flag information with respect to the first control information, the first end information, the second flag information, the second control information, and the second end information, other names may be used for identification in other embodiments.

In one illustrative example, the first data output module includes a first memory and a first output subcircuit; the second data output module comprises a second memory and a second output sub-circuit;

the first memory is arranged to read data from the first signal sequence stored in the first memory according to the address information when the address information sent by the first address generator is received, and send the read data to the first output sub-circuit;

the first output sub-circuit is configured to determine first data according to one or more of the first flag information, the first control information, the first end information, and data sent by the first memory, which are sent by the first judging sub-circuit, and send the first data to the multiplication accumulator;

the second memory is set to read data from the second signal sequence stored in the second memory according to the address information when receiving the address information sent by the second address generator, and send the read data to the second output sub-circuit;

the second output sub-circuit is configured to determine second data according to one or more of the second flag information, the second control information, the second end information, and data sent by the second memory, which are sent by the second judgment sub-circuit, and send the second data to the multiply accumulator.

In one illustrative example, the first output sub-circuit is specifically configured to:

if the first mark information sent by the first judgment sub-circuit and the data sent by the first memory are received, outputting the data sent by the first memory to the multiplication accumulator as first data;

if first control information sent by the first judgment sub-circuit is received, outputting data zero serving as first data to the multiplication accumulator;

if first end information sent by the first judgment sub-circuit is received, outputting data zero as first data to the multiplication accumulator;

the second output sub-circuit is specifically configured to:

if the second flag information sent by the second judgment sub-circuit and the data sent by the second memory are received, outputting the data sent by the second memory to the multiplication accumulator as second data;

if second control information sent by the second judgment sub-circuit is received, outputting data zero as second data to the multiplication accumulator;

and if second ending information sent by the second judgment sub-circuit is received, outputting data zero as second data to the multiplication accumulator.

In an illustrative example, the first address generator is further configured to send the generated address information to the second judgment sub-circuit;

the second address generator is also configured to send the generated address information to the first judgment sub-circuit;

the first judging sub-circuit is further configured to determine a time point of sending the first flag information to the first address generator according to the received address information sent by the second address generator and a current delay value when the address is generated after the first address generator is determined;

the second judgment sub-circuit is further configured to determine, when the address is generated after the second address generator is determined, a time point at which the second flag information is sent to the second address generator according to the received address information sent by the first address generator and the current delay value.

In an exemplary embodiment, the first determining sub-circuit is specifically configured to:

for the current delay value i, when i is a negative number, determining that the first address generator starts generating an address first, and sending the first mark information to the first address generator; when i is a positive number, determining the first address generator to generate an address, and when the first address generator is determined to generate the address and the value of the address contained in the address information sent by the second address generator is | i | -1, sending the first flag information to the first address generator; when i is zero, determining that the first address generator and the second address generator generate addresses simultaneously, and sending the first mark information to the first address generator;

the second judgment sub-circuit is specifically configured to:

for the current delay value i, when i is a positive number, determining that the second address generator starts generating an address first, and sending the second mark information to the second address generator; when i is a negative number, determining the address generated after the second address generator, and when the address generated after the second address generator is determined and the numerical value of the address contained in the address information sent by the first address generator is | i | -1, sending the second flag information to the second address generator; when i is zero, determining that the second address generator generates an address simultaneously with the first address generator, and sending the second flag information to the second address generator;

wherein, m is not less than i and not more than m, m is a preset positive integer, the initial values of the addresses started to be generated by the first address generator and the second address generator are zero, and the value of the address increases by 1 in each clock cycle.

In an illustrative example, the first address generator is further configured to send the generated address information to the first judgment sub-circuit;

the second address generator is further configured to send the generated address information to the second judgment sub-circuit;

the first judging sub-circuit is configured to send the first end information to the first address generator and the first data output module when the data reading of the first signal sequence corresponding to the delay value is completed, and the first judging sub-circuit comprises:

when the received numerical value of the address contained in the address information sent by the first address generator is equal to a-1, stopping sending the mark information to the first address generator and the first output sub-circuit, and sending the first end information to the first address generator and the first output sub-circuit; wherein a is the number of data in the first signal sequence, and a is a positive integer;

the second judging sub-circuit is configured to send the second end information to the second address generator and the second data output module when the data reading of the second signal sequence corresponding to the delay value is completed, and the second judging sub-circuit includes:

when the received numerical value of the address contained in the address information sent by the second address generator is equal to b-1, stopping sending the flag information to the second address generator and the second output sub-circuit, and sending the second end information to the second address generator and the second output sub-circuit; wherein b is the number of data in the second signal sequence, and b is a positive integer.

In an exemplary embodiment, the first determining sub-circuit is further configured to send the first end information to the delay time generating circuit when a value of an address included in the received address information sent by the first address generator is equal to a-1;

the second judgment sub-circuit is further configured to send the second end information to the delay time generation circuit when a value of an address included in the received address information sent by the second address generator is equal to b-1;

the delay time generation circuit, configured to send each delay value to the data reading circuit, includes:

when the first end information sent by the first judging sub-circuit is received and the second end information sent by the second judging sub-circuit is received, sending the next delay value until all the delay values are sent to the data reading circuit.

The present application further provides a method for implementing cross-correlation operation, which is applied to any one of the above-mentioned apparatuses for implementing cross-correlation operation, and includes:

determining more than one delay value;

determining first data according to each received delay value and a first signal sequence, and determining second data according to each received delay value and a second signal sequence;

and deriving a cross-correlation value of the first signal sequence and the second signal sequence at each delay value according to the first data and the second data.

The application provides a device and a method for realizing cross-correlation operation, wherein the device comprises: the device comprises a delay time generating circuit, a data reading circuit and a multiplication accumulator; the delay time generating circuit is set to determine more than one delay value and send each delay value to the data reading circuit; the data reading circuit is arranged to determine first data according to each delay value and first signal sequence received, determine second data according to each delay value and second signal sequence received, and output the first data and the second data to the multiplication accumulator; and the multiplication accumulator is arranged to obtain the cross-correlation value of the first signal sequence and the second signal sequence at each delay value according to the first data and the second data output by the data reading circuit. According to the technical scheme, the cross-correlation calculation of different delays can be realized through the delay time generation circuit and the data reading circuit, and the complexity of the cross-correlation calculation of different delays is effectively reduced.

Drawings

The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

Fig. 1 is a schematic diagram of a first apparatus for implementing a cross-correlation operation according to a first embodiment of the present application;

FIG. 2 is a diagram of a second apparatus for performing a cross-correlation operation according to a first embodiment of the present application;

FIG. 3 is a schematic diagram of a third apparatus for performing a cross-correlation operation according to a first embodiment of the present application;

FIG. 4 is a diagram of a fourth apparatus for performing a cross-correlation operation according to a first embodiment of the present application;

FIG. 5 is a diagram of a fifth apparatus for performing a cross-correlation operation according to a first embodiment of the present application;

FIG. 6 is a flowchart of a method for implementing a cross-correlation operation according to a first embodiment of the present application;

fig. 7 is a schematic circuit diagram of an embodiment of the present application to implement a cross-correlation operation.

Detailed Description

The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

Example one

As shown in fig. 1, the present embodiment provides an apparatus for implementing a cross-correlation operation, including: a delay time generating circuit 1, a data reading circuit 2 and a multiplication accumulator 3;

the delay time generating circuit 1 is configured to determine more than one delay value and send each delay value to the data reading circuit;

the data reading circuit 2 is configured to determine first data according to each delay value and first signal sequence received, determine second data according to each delay value and second signal sequence received, and output the first data and the second data to the multiplication accumulator;

the multiplication accumulator 3 is configured to obtain a cross-correlation value of the first signal sequence and the second signal sequence at each delay value according to the first data and the second data output by the data reading circuit.

According to the technical scheme, the cross-correlation calculation of different delays can be realized through the delay time generation circuit and the data reading circuit, and the complexity of the cross-correlation calculation of different delays is effectively reduced.

As shown in fig. 2, in an illustrative example, the data reading circuit 2 includes a first address generating module 21, a first data outputting module 22, a second address generating module 23, and a second data outputting module 24;

the first address generating module 21 is configured to receive the delay value sent by the delay time generating circuit; determining first state information according to the received delay value, or the received delay value and second state information sent by the second address generation module, and sending the first state information to the first data output module; wherein the first state information includes: the first address generation module generates address information and first mark information used for identifying an address which starts to be generated by the first address generation module, or first control information used for identifying an address which does not start to be generated by the first address generation module, or first end information used for identifying that data reading of the first signal sequence corresponding to the current delay value is finished;

the second address generating module 23 is configured to receive the delay value sent by the delay time generating circuit; determining the second state information according to the received delay value, or the received delay value and the first state information sent by the first address generation module, and sending the second state information to the second data output module; wherein the second state information includes: the address information generated by the second address generation module and second flag information used for identifying that the second address generation module starts generating an address, or second control information used for identifying that the second address generation module does not start generating an address, or second end information used for identifying that data reading of the second signal sequence corresponding to the current delay value is finished;

the first data output module 22 is configured to determine the first data according to the received first state information and the first signal sequence stored in the first data output module, and output the first data to the multiply accumulator;

the second data output module 24 is configured to determine the second data according to the received second state information and the second signal sequence stored in the second data output module, and output the second data to the multiply accumulator.

As shown in fig. 3, in an exemplary embodiment, the first address generating module 21 includes a first judging sub-circuit 211 and a first address generator 212; the second address generating module 23 includes a second judging sub-circuit 231 and a second address generator 232;

the first judging sub-circuit 211 is configured to determine, according to the received delay value, an order in which the first address generator and the second address generator start generating addresses in the delay value; when the first address generator is determined to generate an address first, the first mark information is sent to the first address generator and the first data output module; when the data reading of the first signal sequence corresponding to the delay value is finished, the first end information is sent to the first address generator and the first data output module; when an address is generated after the first address generator is determined, sending the first control information to the first address generator and the first data output module before sending the first flag information to the first address generator;

the first address generator 212 is configured to start generating an address when receiving the first flag information sent by the first judgment sub-circuit, and send the generated address information to the first data output module, so that the first data output module reads data from the first signal sequence according to the address information;

the second judgment sub-circuit 231 is configured to determine, according to the received delay value, an order in which the second address generator and the first address generator start generating addresses in the delay value; when the second address generator is determined to generate an address first, the second mark information is sent to the second address generator and the second data output module; when the data reading of the second signal sequence corresponding to the delay value is finished, sending the second end information to the second address generator and the second data output module; when the address is generated after the second address generator is determined, sending second control information to the second address generator and the second data output module before sending the second flag information to the second address generator;

the second address generator 232 is configured to start generating an address when receiving the second flag information sent by the second judgment sub-circuit, and send the generated address information to the second data output module, so that the second data output module reads data from the second signal sequence according to the address information.

As shown in fig. 4 and 5, in an illustrative example, the first data output module 22 includes a first memory 221 and a first output sub-circuit 222; the second data output module 24 includes a second memory 241 and a second output sub-circuit 242;

the first memory 221, configured to, when receiving address information sent by the first address generator, read data from the first signal sequence stored in the first memory according to the address information, and send the read data to the first output sub-circuit;

the first output sub-circuit 222 is configured to determine first data according to one or more of the first flag information, the first control information, the first end information, and data sent by the first memory sent by the first determining sub-circuit, and send the first data to the multiply accumulator;

the second memory 241 is configured to, when receiving address information sent by the second address generator, read data from the second signal sequence stored in the second memory according to the address information, and send the read data to the second output sub-circuit;

the second output sub-circuit 242 is configured to determine second data according to one or more of the second flag information, the second control information, the second end information, and data sent by the second memory sent by the second determining sub-circuit, and send the second data to the multiply accumulator.

the second output sub-circuit is specifically configured to:

In this embodiment, taking the first judging sub-circuit as an example, the first judging sub-circuit may send a message to the first output sub-circuit every clock cycle, where the message may be the first flag message, or the first end message, or the first control message, that is, in every clock cycle, the first output sub-circuit determines the first data according to the received message. The first decision sub-circuit may also be such that each type of information is sent only once. For example, when the first address generator does not start generating an address, the first control information is sent to the first output sub-circuit only once, and the first output sub-circuit determines the first data in a state corresponding to the first control information by default until other information is received, so that the first output sub-circuit always outputs zero data as the first data to the multiply accumulator. When the first judging sub-circuit determines that the first address generator starts to generate the address, the first flag information is sent to the first output sub-circuit only once, and similarly, before other information is received, the first data is determined in a state corresponding to the first flag information by default, namely, the data sent by the first memory is output to the multiplication accumulator as the first data. When the first judging sub-circuit determines that the data of the first signal sequence is completely read, the first ending information is sent to the first output sub-circuit only once, and the first output sub-circuit determines the first data in a state corresponding to the first ending information by default before receiving other information, namely, the data zero is output to the multiplication accumulator as the first data.

When the first judgment sub-circuit determines that the first address generator starts generating the address, the first flag information may be sent to the first address generator every clock cycle, that is, the first address generator determines whether the address needs to be generated according to whether the first flag information is received. The first judging sub-circuit may further send the first flag information to the first address generator only once, automatically generate the address as long as the first address generator receives the first flag information, and increase the address value by 1 at each clock cycle until receiving the first end information sent by the first judging sub-circuit, the first address generator stops generating the address, and when the first address generator stops generating the address, the first address generator does not send the address information to the first memory any more.

The second determining sub-circuit sends information in a manner similar to that of the first determining sub-circuit, and is not described herein again.

the second judgment sub-circuit is specifically configured to:

In one illustrative example, the delay time generation circuit configured to determine the one or more delay values comprises:

and according to the received set positive integer m, obtaining more than one delay value as a set of all integers meeting the following conditions: greater than or equal to-m and less than or equal to m.

In an illustrative example, the multiply accumulator is specifically configured to:

performing multiply-add calculation on the first data and the second data received in each clock cycle;

and obtaining the cross-correlation value of the first signal sequence and the second signal sequence under each delay value according to all the multiply-add calculation results corresponding to each delay value.

As shown in fig. 6, this embodiment further provides a method for implementing a cross-correlation operation, which is applied to any one of the apparatuses for implementing a cross-correlation operation described above, and includes:

step S101, determining more than one delay value;

step S102, determining first data according to each received delay value and a first signal sequence, and determining second data according to each received delay value and a second signal sequence;

and step S103, obtaining a cross-correlation value of the first signal sequence and the second signal sequence at each delay value according to the first data and the second data.

Example two

The method of implementing the cross-correlation calculation of the present application is further described below.

As shown in fig. 7, a circuit diagram for implementing the cross-correlation calculation includes a delay time generation circuit, a judgment sub-circuit a, an address generator a, a block memory a, an output sub-circuit a, a judgment sub-circuit B, an address generator B, a block memory B, an output sub-circuit B, and a multiplication accumulator. (in the present embodiment, A and B correspond to the first and second ones described above, for example, the judgment sub-circuit A corresponds to the first judgment sub-circuit)

The delay time generating circuit is respectively connected with the judging sub-circuit A and the judging sub-circuit B, the address generator A is connected with the judging sub-circuit B, the judging sub-circuit A is connected with the address generator A, the judging sub-circuit B is connected with the address generator B, the address generator A is connected with the block memory A, and the address generator B is connected with the block memory B; the block memory A is connected with the output sub-circuit A, and the block memory B is connected with the output sub-circuit B; the output sub-circuit A and the output sub-circuit B are respectively connected with the multiplication accumulator; the judgment sub-circuit A is connected with the output sub-circuit A, and the judgment sub-circuit B is connected with the output sub-circuit B.

The working principle of the delay time generation circuit and the data reading circuit (including the judgment sub-circuit a, the address generator a, the block memory a, the output sub-circuit a, the judgment sub-circuit B, the address generator B, the block memory B, and the output sub-circuit B) is further described as follows:

the cross-correlation IP is to realize the multiply-add operation of two signal sequences under different delay conditions, and output the result after the calculation is finished. In this embodiment, the signal sequence a may be stored in the block memory a, and the signal sequence B may be stored in the block memory B.

It is assumed that the cross-correlation value of the signal sequence a and the signal sequence b under different delay conditions needs to be calculated. Firstly, setting the maximum delay time number as m (m is a positive integer), inputting the maximum delay time number m into a delay time generating circuit, and obtaining all delay values required to be output by the delay time generating circuit according to m, wherein the delay values comprise-m, - (m-1) … … 0 … …, m-1 and m, and the total time is 2m-1, and accordingly, 2m-1 cross-correlation calculation results can be obtained.

If the address generator connected with the judgment sub-circuit generates an address first, the address generator connected with the judgment sub-circuit determines when the address generator connected with the judgment sub-circuit starts to generate the address according to the value of the delay value and the value of the address generated by the other address generator. In this example, the judgment sub-circuit instructs the address generator to start generating the address by sending flag information to the address generator connected to itself.

In this example, the address generator generates the address immediately after receiving the flag information, the initial address has a value of 0, the address increases by 1 every clock cycle, and the address generator that generates the address later starts generating the address when another address generator generates the address having a value of one minus the absolute value of the delay value, that is, the address generator that generates the address later generates the address after the address generator that generates the address first reads the data of the absolute value of the delay value from the memory to which the address generator that generates the address first is connected.

Each block memory reads the data stored in the block memory according to the address generated by the address generator correspondingly connected, when the data in the block memory A and the block memory B are all read, namely the data used for calculating the cross correlation value of the signal sequence a and the signal sequence B under the current delay value is completely read, the delay time generation circuit sends the next delay value, and so on, until all the delay values are all sent to the data reading circuit.

In this embodiment, the delay time generation circuit may sequentially send each delay value to the data reading circuit from-m. If the delay time is negative, the signal sequence B in the block memory B is slid backward and then the multiply-add operation is performed, and if the delay time is positive, the signal sequence B in the block memory B is slid forward and then the multiply-add operation is performed. Therefore, when the delay time is a positive number, the address generator B generates the address first, so as to achieve the purpose of sliding the sequence in the block memory B forwards; when the delay time is negative, the address generator A generates the address first, so as to achieve the purpose of backward sliding of the sequence in the block memory B.

The following illustrates the data reading process:

1. suppose that the delay value sent by the current delay time generation circuit is-m

The delay time generating circuit sends m to the judging sub-circuit A and the judging sub-circuit B, and the judging sub-circuit A determines that the address generator A starts generating the address first because the delay value is a negative number, so that the first mark information is sent to the address generator A immediately, and meanwhile, the judging sub-circuit A also sends the first mark information to the output sub-circuit A. After receiving the first flag information, the address generator a starts generating an address, and sends the generated address to the block memory a (the initial value of the address generated by the address generator is 0, and one is added to the address every clock cycle), the block memory a reads data in the signal sequence a according to the address sent by the address generator a, and then outputs the read data to the multiplier-accumulator until the data in the block memory a is completely read. In the reading process, because the data in the block memory a is read first, the data in the block memory a can be read out before the data in the block memory B is read out, that is, when the data in the block memory a is read out, the data in the block memory B is not read out yet, therefore, after the data in the block memory a is read out, the judgment sub-circuit a sends first end information to the address generator a and the output sub-circuit a to identify that the data in the block memory a is read out completely under the current delay value, and meanwhile, the judgment sub-circuit a also sends the first end information to the delay time generation circuit. The output sub-circuit A determines data output to the multiplication accumulator according to the received information sent by the judgment sub-circuit A, if first flag information sent by the judgment sub-circuit A is received, the data sent by the block-shaped memory A is output to the multiplication accumulator as first data, if first end information sent by the judgment sub-circuit A is received, the data in the block-shaped memory A is indicated to be completely read, the data zero is output to the multiplication accumulator as the first data, and the data zero is output to the multiplication accumulator until the data in the block-shaped memory B is completely read. The address generator a determines whether to generate an address according to the received information sent by the judgment sub-circuit a, generates an address if receiving the first flag information sent by the judgment sub-circuit a, and does not generate an address if receiving the first end information sent by the judgment sub-circuit a.

In this example, the address generator a further sends each generated address to the judgment sub-circuit a and the judgment sub-circuit B, the judgment sub-circuit a determines whether the data in the block memory a is completely read at the current delay value according to the value of the address sent by the address generator a, and determines that the data in the block memory a is completely read if the value of the address sent by the address generator a is the number of the data in the signal sequence a minus one, and then sends the first end information to the address generator a and the output sub-circuit a.

Since the judgment sub-circuit B determines that the address generator B generates an address after determining, the address generator B sends second control information to the address generator B and the output sub-circuit B before sending the second flag information to the address generator B, so that the address generator B does not generate an address and identifies that the address generator B does not start generating an address. When the output sub-circuit B receives the second control information, since the data in the block memory B does not start to be read at this time, the output sub-circuit B outputs the data zero as the second data to the multiply accumulator, and outputs the data zero to the multiply accumulator every clock cycle before the second flag information is received.

Meanwhile, the judgment sub-circuit B determines a time point of sending the second flag information to the address generator B according to the received address sent by the address generator a, in this example, when the value of the address sent by the address generator a is the absolute value of the current delay value minus one, the judgment sub-circuit B sends the second flag information to the address generator B, the address generator B starts to generate the address after receiving the second flag information, the initial value of the generated address is zero, and the address is incremented by one every clock cycle. The address generator B sends the generated address to the block memory B, the block memory B reads data from the signal sequence B according to the received address and outputs the read data to the multiplication accumulator, and the judgment sub-circuit B sends second end information to the delay time generation circuit until all the data in the block memory B are read. At this time, the data of the signal sequence a and the signal sequence b corresponding to the delay value-m are completely read, and the multiplication accumulator also calculates the cross-correlation value under the delay value-m.

The delay time generation circuit transmits a next delay value when receiving the first end information and receiving the second end information.

It can be seen from the above process that in each clock cycle, the output sub-circuit a and the output sub-circuit B output one data to the multiply accumulator, the output sub-circuit B always outputs data 0 in the first m clock cycles, and the output sub-circuit a always outputs data 0 in the last m clock cycles, so that the purpose of sliding the signal sequence in the block memory B backward and then performing multiply-add operation is achieved.

2. Suppose that the delay value sent by the current delay time generation circuit is m

The delay time generating circuit sends m to the judging sub-circuit A and the judging sub-circuit B, and because the delay value is a positive number, the judging sub-circuit B determines that the address generator B starts generating the address first, so that the second mark information is sent to the address generator B immediately, and meanwhile, the judging sub-circuit B also sends the second mark information to the output sub-circuit B. And after receiving the second mark information, the address generator B starts to generate an address, sends the generated address to the block memory B (the initial value of the address generated by the address generator is 0, and one is added to the address every clock cycle), reads data in the signal sequence B according to the address sent by the address generator B, and then outputs the read data to the multiplication accumulator until the data in the block memory B is completely read. In the reading process, because the data in the block memory B is read first, the data in the block memory B can be read before the data in the block memory a is completely read, that is, when the data in the block memory B is completely read, the data in the block memory a is not completely read, therefore, after the data in the block memory B is completely read, the judgment sub-circuit B sends the second end information to the address generator B and the output sub-circuit B to identify that the data in the block memory B is completely read in the current delay value, and meanwhile, the judgment sub-circuit B also sends the second end information to the delay time generation circuit. The output sub-circuit B determines data output to the multiplication accumulator according to the received information sent by the judgment sub-circuit B, if second flag information sent by the judgment sub-circuit B is received, the data sent by the block-shaped memory B is output to the multiplication accumulator as second data, if second end information sent by the judgment sub-circuit B is received, the data in the block-shaped memory B is read completely, the data zero is output to the multiplication accumulator as the second data, and the data zero is output to the multiplication accumulator until the data in the block-shaped memory A is read completely. The address generator B can determine whether to generate an address according to the received information sent by the judgment sub-circuit B, if the second flag information sent by the judgment sub-circuit B is received, the address is generated, and if the second end information sent by the judgment sub-circuit B is received, the address is not generated.

In this example, the address generator B further sends each generated address to the judgment sub-circuit B and the judgment sub-circuit a, the judgment sub-circuit B determines whether the data in the block memory B is completely read at the current delay value according to the value of the address sent by the address generator B, and determines that the data in the block memory B is completely read if the value of the address sent by the address generator B is the number of the data in the signal sequence B minus one, and at this time, sends second end information to the address generator B and the output sub-circuit B.

Since the judgment sub-circuit a determines that the address generator a generates an address after determining that the address generator a generates an address, the judgment sub-circuit a sends first control information to the address generator a and the output sub-circuit a before sending the first flag information to the address generator a to control the address generator a not to generate an address and identify that the address generator a does not start generating an address. When the output sub-circuit a receives the first control information, since the data in the block memory a does not start to be read at this time, the output sub-circuit a outputs the data zero as the first data to the multiply accumulator, and outputs the data zero to the multiply accumulator every clock cycle before the first flag information is received.

Meanwhile, the judgment sub-circuit a determines the time point of sending the first flag information to the address generator a according to the received address sent by the address generator B, in this example, when the value of the address sent by the address generator B is the absolute value of the current delay value minus one, the judgment sub-circuit A sends first mark information to the address generator A, the address generator A starts to generate the address after receiving the first mark information, the initial value of the generated address is zero, the address is added by one in each clock cycle, the address generator A sends the generated address to the block memory A, the block memory A reads data from the signal sequence a according to the received address, and outputting the read data to the multiplication accumulator until the data in the block memory A is completely read, and sending the first end information to the delay time generation circuit by the judgment sub-circuit A. At this time, the data of the signal sequence a and the signal sequence b corresponding to the delay value m are all read completely, and the multiplication accumulator also calculates the cross-correlation value under the delay value m.

It can be seen from the above process that in each clock cycle, the output sub-circuit a and the output sub-circuit B respectively output one data to the multiply accumulator, in the first m clock cycles, the output sub-circuit a always outputs data 0, and in the last m clock cycles, the output sub-circuit B always outputs data 0, so that the purpose of sliding the signal sequence in the block memory B forward and then performing multiply-add operation is achieved.

The calculation of the cross-correlation is described in detail below:

assuming that a delay value sent by a current delay time generation circuit is i, in each clock cycle, an output sub-circuit A and an output sub-circuit B respectively output a data to a multiplication accumulator, the multiplication accumulator performs multiplication and addition calculation on each received group of data (each group of data comprises the data output by the output sub-circuit A and the data output by the output sub-circuit B), and after the data in the block memory A and the block memory B are all read, the multiplication and addition calculation process of the data corresponding to the delay value i is finished, so as to obtain a cross-correlation value of a signal sequence a and a signal sequence B under the condition of the delay value i.

Then, data is output to the multiplication accumulator according to the next delay value, and the operations are repeated to obtain the cross-correlation value corresponding to the next delay value. Until a cross-correlation value of 2m-1 is obtained.

Through the technical scheme, the signal sequence a and the signal sequence b are still stored in the corresponding block memories, but the output data already has the delay value generated by the delay time generator, and the delay time generator generates the next delay value at this moment, so that the sequences corresponding to different delay values can be output.

By adopting the technical scheme, the resource consumption can be reduced, the cross-correlation operation can be realized only by few hardware resources, the complexity of the cross-correlation operation with different delays is reduced, and the accuracy of the correlation calculation is kept on the basis of reducing the resource consumption.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

Claims

1. An apparatus for performing a cross-correlation operation, comprising: the method comprises the following steps: the device comprises a delay time generating circuit, a data reading circuit and a multiplication accumulator;

2. The apparatus for performing a cross-correlation operation as claimed in claim 1, wherein:

the data reading circuit comprises a first address generation module, a first data output module, a second address generation module and a second data output module;

3. The apparatus for performing a cross-correlation operation as claimed in claim 2, wherein:

the first address generation module comprises a first judgment sub-circuit and a first address generator; the second address generation module comprises a second judgment sub-circuit and a second address generator;

4. The apparatus for performing a cross-correlation operation as claimed in claim 3, wherein:

the first data output module comprises a first memory and a first output sub-circuit; the second data output module comprises a second memory and a second output sub-circuit;

5. The apparatus for performing a cross-correlation operation as claimed in claim 4, wherein:

the first output sub-circuit is specifically configured to:

the second output sub-circuit is specifically configured to:

6. The apparatus for performing a cross-correlation operation as claimed in claim 3, wherein:

the first address generator is further configured to send the generated address information to the second judgment sub-circuit;

7. The apparatus for performing a cross-correlation operation as claimed in claim 6, wherein:

the first judgment sub-circuit is specifically configured to:

the second judgment sub-circuit is specifically configured to:

8. The apparatus for performing a cross-correlation operation as claimed in claim 6, wherein:

the first address generator is also configured to send the generated address information to the first judgment sub-circuit;

9. The apparatus for performing a cross-correlation operation of claim 8, wherein:

the first judging sub-circuit is further configured to send the first end information to the delay time generating circuit when a value of an address included in the received address information sent by the first address generator is equal to a-1;

10. A method for implementing cross-correlation operation, applied to the apparatus for implementing cross-correlation operation as claimed in any one of claims 1 to 9, comprising:

determining more than one delay value;