CN112542428A - Chip packaging structure and chip connecting structure - Google Patents
Chip packaging structure and chip connecting structure Download PDFInfo
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- CN112542428A CN112542428A CN202011383645.XA CN202011383645A CN112542428A CN 112542428 A CN112542428 A CN 112542428A CN 202011383645 A CN202011383645 A CN 202011383645A CN 112542428 A CN112542428 A CN 112542428A
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- chip
- solder
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- substrate
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 20
- 229910000679 solder Inorganic materials 0.000 claims abstract description 100
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 238000002844 melting Methods 0.000 claims abstract description 30
- 230000008018 melting Effects 0.000 claims abstract description 30
- 230000017525 heat dissipation Effects 0.000 claims description 42
- 239000000463 material Substances 0.000 claims description 21
- 230000001681 protective effect Effects 0.000 claims description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 229910045601 alloy Inorganic materials 0.000 description 9
- 239000000956 alloy Substances 0.000 description 9
- 229910052797 bismuth Inorganic materials 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910052738 indium Inorganic materials 0.000 description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 239000000155 melt Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 229910000765 intermetallic Inorganic materials 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The application discloses chip package structure and chip connection structure, chip package structure includes: the surface of the substrate is provided with a plurality of conductive pieces, the conductive pieces are wrapped by the solder layer, and the melting point of the conductive pieces is higher than that of the solder layer. In the embodiment, the melting point of the conductive piece is higher than that of the solder layer, when the chip packaging structure is connected with the printed circuit board, the solder layer is melted at high temperature, and the conductive piece continuously keeps the existing shape. The melted solder layer is connected with the substrate and the printed circuit board, so that the bridging problem of two adjacent conductive pieces when the chip packaging structure is connected with the printed circuit board is effectively avoided.
Description
Technical Field
The application relates to the technical field of chip packaging, in particular to a chip packaging structure and a chip connecting structure.
Background
The chip packaging structure comprises a heat dissipation cover, a chip and a substrate, wherein the chip and the heat dissipation cover are connected to the substrate, and the chip is located in the heat dissipation cover. Solder balls are arranged on the surface of the substrate, which is opposite to the chip.
When the chip packaging structure is connected with the printed circuit board, the reflow soldering melts the solder balls so that the substrate is connected with the printed circuit board. In the above process, the bridging problem is easily generated between two adjacent solder balls.
Disclosure of Invention
Accordingly, the present invention provides a chip package structure and a chip connection structure, which at least partially solve the above-mentioned problems.
In a first aspect:
the invention provides a chip packaging structure, which comprises:
the surface of the substrate is provided with a plurality of conductive pieces, the conductive pieces are wrapped by the solder layer, and the melting point of the conductive pieces is higher than that of the solder layer.
Most preferably, the conductive member and the solder layer are connected by a connecting layer, the connecting layer encasing the conductive member.
As an optimal realization mode, the protection device further comprises a passive component, wherein the passive component is connected to the surface, facing away from the conductive piece, of the substrate, and is covered by a protection material.
As an optimal mode for realization, the chip-type soldering terminal further comprises a chip and a heat dissipation cover, wherein the chip and the heat dissipation cover are connected to the surface of the substrate, which faces away from the conductive piece, the passive component and the chip are located in the heat dissipation cover, the heat dissipation cover and the chip are connected through a heat conduction layer, and the melting point of the heat conduction layer is higher than that of the solder layer.
Most preferably, the conductivity of the conductive member is greater than the conductivity of the solder layer.
Most preferably, the conductive member has a thermal conductivity greater than that of the solder layer.
In a second aspect:
the invention provides a chip connecting structure, which comprises a chip packaging structure and a printed circuit board, wherein the chip packaging structure comprises a substrate, the substrate and the printed circuit board are oppositely arranged,
the surface of the substrate facing the printed circuit board is provided with a plurality of conductive pieces;
the surface of the printed circuit board facing the substrate is coated with a plurality of solder blocks arranged at intervals, each solder block corresponds to one conductive piece, the solder blocks are connected with the printed circuit board and the conductive pieces, and the melting point of the conductive pieces is higher than that of the solder blocks.
Most preferably, the conductivity of the conductive member is higher than the conductivity of the solder mass.
Most preferably, the conductive member has a thermal conductivity higher than that of the solder mass.
As an optimal way to realize, the chip packaging structure further comprises a chip and a heat dissipation cover, wherein the chip and the heat dissipation cover are connected to the surface of the substrate opposite to the conductive block, and the chip is located in the heat dissipation cover,
the heat dissipation cover and the chip are connected through a heat conduction layer, and the melting point of the heat conduction layer is higher than that of the solder block.
In the embodiment, the melting point of the conductive piece is higher than that of the solder layer, when the chip packaging structure is connected with the printed circuit board, the solder layer is melted at high temperature, and the conductive piece continuously keeps the existing shape. The melted solder layer is connected with the substrate and the printed circuit board, so that the problem of bridging of two adjacent conductive pieces when the chip packaging structure is connected with the printed circuit board is effectively avoided, one pin of the chip corresponds to one pin of the printed circuit board one by one, and the two pins stably transmit information; the protective material on the passive component avoids the erosion of molten liquid drops to the passive component, and the passive component can stably run; the melting point of the heat conduction layer is higher than that of the solder layer, so that the increase of the multiple-reflux voidage of the heat conduction layer is avoided.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1 is a first schematic structural diagram of a chip package structure according to an embodiment of the present application;
fig. 2 is a schematic diagram of a chip connection structure according to an embodiment of the present application;
fig. 3 is a first schematic structural diagram of another chip package structure according to an embodiment of the present application;
fig. 4 is a schematic diagram of another chip connection structure according to an embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant application and are not limiting of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. It should be noted that, for the convenience of description, only the portions relevant to the application are shown in the drawings.
In the description of the present application, it is to be understood that the terms "radial," axial, "" upper "inner," "outer," and the like refer to an orientation or positional relationship based on that shown in the drawings, which is for convenience in describing the present application and simplifying the description, and does not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted", "disposed" and "connected" are to be understood in a broad sense, e.g. either fixedly or detachably or integrally connected: may be directly connected or indirectly connected through an intermediate. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
Fig. 1 shows a schematic structural diagram of a chip package structure.
A chip package structure includes: heat dissipation cover 10, chip 30 and substrate 40. The heat-dissipating cap 10 and the chip 30 are attached on the same surface of the substrate 40, and the chip 30 is located inside the heat-dissipating cap 10. Several conductive elements 50 are disposed on the surface of the substrate 40 facing away from the chip 30, and the conductive elements 50 are wrapped by the solder layer 61, wherein the melting point of the conductive elements 50 is higher than that of the solder layer 61. For example, the conductive member 50 may be made of a copper material, a nickel material, or other suitable materials; the solder layer 61 may be solder paste SAC305, solder paste SAC307, Sn 58% Bi 42% alloy, or the like.
Referring to fig. 2, when the chip package structure is connected to a printed circuit board 70 (PCB), a high temperature melts the solder layer 61, and the conductive member 50 continues to maintain the existing shape. The melted solder adheres to the conductive member 50 while the solder connects the substrate 40 with the printed circuit board 70. The structure of the chip package structure effectively avoids the bridging problem of two adjacent conductive pieces 50 when the chip package structure is connected with the printed circuit board 70, so that one pin of the chip 30 corresponds to one pin of the printed circuit board 70 one by one, and the two pins stably transmit information.
In some preferred embodiments, the chip package structure further includes a passive component 80, the passive component 80 is connected to a surface of the substrate 40 facing away from the conductive member 50, and the passive component 80 is covered by the protection material 90.
Referring to fig. 1, in the present embodiment, the chip package structure includes a substrate 40, a chip 30, a heat dissipation cover 10 and a plurality of passive components 80. A plurality of conductive members 50 are disposed on a surface of the substrate 40, and the conductive members 50 are surrounded by a solder layer 61. The heat dissipation cover 10, the chip 30 and the passive component 80 are connected to the surface of the substrate 40 opposite to the heat conducting member, the chip 30 and the passive component 80 are located in the heat dissipation cover 10, and the plurality of passive components 80 are arranged around the chip 30. The heat dissipation cover 10 includes a top portion and a side portion surrounding the top portion, the side portion of the heat dissipation cover 10 is connected to the substrate 40 by an adhesive, and the top portion of the heat dissipation cover 10 is connected to the chip 30 by the heat conductive layer 20. The passive component 80 is covered with a protective material 90.
The solder layer 61 of the chip package structure is a solder paste, such as a solder paste SAC305 or a solder paste SAC307, and has a melting point of 217-227 ℃. And the thermally conductive layer 20 is an indium layer having a melting point of 156 c. When the chip package structure is connected to a printed circuit board 70 (PCB), the solder layer 61 is melted at a high temperature. Since the melting point of the heat conducting layer 20 is lower than the melting point of the solder layer 61, the heat conducting layer 20 melts before the solder layer 61, and the molten droplets of the heat conducting layer 20 are sputtered onto the passive component 80. The protective material 90 on the passive component 80 prevents molten droplets from eroding the passive component 80, so that the passive component 80 can operate stably.
Further, the heat dissipation cover 10 and the chip 30 are connected by the heat conductive layer 20, and the melting point of the heat conductive layer 20 is higher than that of the solder layer 61.
In the present embodiment, the solder layer 61 of the chip package structure is Sn 58% Bi 42% alloy, and Sn 58% Bi 42% alloy with a melting point of 139 ℃. And the material of the heat conducting layer 20 is an indium layer, and the melting point of indium is 156 ℃. When the chip package structure is connected with the printed circuit board 70 (PCB), the solder layer 61 is melted at a high temperature, and the heat conduction layer 20 continues to keep the existing state and is not melted because the melting point of the heat conduction layer 20 is higher than that of the solder layer 61, thereby avoiding the increase of the multiple reflux void ratio of the heat conduction layer 20. And the low-temperature reflow can effectively inhibit the warping of the substrate 40, and the packaging performance of the chip packaging structure is improved.
In some preferred embodiments, conductive element 50 is connected to solder layer 61 by a connecting layer that encapsulates conductive element 50.
Referring to fig. 1, in the present embodiment, a plurality of conductive members 50 are disposed on a surface of the substrate 40 facing away from the chip 30, and the conductive members 50 are arranged in a rectangular array, so that a distance between any two adjacent conductive members 50 is a fixed value C. Conductive piece 50 can be made by the copper material, and conductive piece 50 is spherical, and conductive piece 50's diameter is 80 ~ 700 um. The solder layer 61 wraps the conductive piece 50, the solder layer 61 is Sn 58% Bi 42% alloy, and the thickness of the solder layer 61 is 10-30 um.
In some preferred embodiments, the conductivity of conductive member 50 is greater than the conductivity of solder layer 61.
In the present embodiment, a plurality of conductive members 50 are disposed on a surface of the substrate 40 facing away from the chip 30, and the conductive members 50 are arranged in a rectangular array, so that a distance between any two adjacent conductive members 50 is a fixed value C. The conductive member 50 can be made of a copper material, a nickel material or other suitable materials, the conductive member 50 is spherical, and the diameter of the conductive member 50 is 80-700 um. The solder layer 61 wraps the conductive member 50, the solder layer 61 is made of tin paste SAC305, tin paste SAC307, Sn 58% Bi 42% alloy and the like, and the thickness of the solder layer 61 is 10-30 um.
When the chip package structure is connected to a printed circuit board 70 (PCB), since the conductivity of the conductive member 50 is greater than the conductivity of the solder layer 61, compared with the solder ball as the conductive member 50 in the related art, the conductive member 50 of the present application is beneficial to the conduction between the chip 30 and the printed circuit board 70, and improves the information transmission efficiency between the chip 30 and the printed circuit board 70.
In some preferred embodiments, the conductive member 50 has a thermal conductivity greater than that of the solder layer 61.
In the present embodiment, the chip package structure includes a substrate 40, a chip 30, and a heat dissipation cover 10. The heat-dissipating cap 10 and the chip 30 are attached on the same surface of the substrate 40, and the chip 30 is located inside the heat-dissipating cap 10. The heat dissipation cover 10 includes a top portion and a side portion surrounding the top portion, the side portion of the heat dissipation cover 10 is connected to the substrate 40 by an adhesive, and the top portion of the heat dissipation cover 10 is connected to the chip 30 by the heat conductive layer 20. On the surface of the substrate 40 facing away from the chip 30, a plurality of conductive members 50 are disposed, and the conductive members 50 are wrapped by solder layers 61.
After the chip package structure is connected to the printed circuit board 70 (PCB), except that the heat of the chip 30 is dissipated through the heat dissipating cover 10, because the thermal conductivity of the conductive member 50 is greater than that of the solder layer 61, compared with the solder ball in the related art as the conductive member 50, the conductive member 50 of the present application is beneficial to the heat transfer between the chip 30 and the printed circuit board 70, thereby improving the heat transfer efficiency between the chip 30 and the printed circuit board 70 and further reducing the temperature of the chip 30.
Fig. 4 shows a schematic structural diagram of a chip connection structure.
Referring to fig. 3 and 4, a chip connection structure includes a chip package structure and a printed circuit board 70, and the chip package structure and the printed circuit board 70 are oppositely disposed. The chip package structure includes a substrate 40, a chip 30 and a heat dissipation cover 10, wherein the chip 30 and the heat dissipation cover 10 are connected to the same surface of the substrate 40, and the chip 30 is located in the heat dissipation cover 10. A plurality of conductive members 50 are disposed on a surface of the substrate 40 facing away from the chip 30. The conductive member 50 can be made of a copper material, a nickel material or other suitable materials, the conductive member 50 is spherical, and the diameter of the conductive member 50 is 80-700 um.
When the chip package structure is connected to the printed circuit board 70, the substrate 40 of the chip package structure faces the printed circuit board 70, and the conductive member 50 is located between the substrate 40 and the printed circuit board 70. A plurality of solder bumps 62 are coated on the surface of the printed circuit board 70 facing the substrate 40, and each solder bump 62 corresponds to one of the conductive members 50. The solder mass 62 may be solder paste SAC305, solder paste SAC307, Sn 58% Bi 42% alloy, or the like. Wherein the melting point of the solder mass 62 is lower than the melting point of the conductive member 50.
The solder mass 62 is melted at a high temperature, and since the melting point of the solder mass 62 is lower than the melting point of the conductive member 50, the solder mass 62 melts and the conductive member 50 continues to maintain the existing shape. The melted solder mass 62 connects the substrate 40 to the printed circuit board 70. The above connection mode of the chip package structure and the printed circuit board 70 effectively avoids the bridging problem of two adjacent conductive members 50, so that one pin of the chip 30 corresponds to one pin of the printed circuit board 70 one by one, and the two pins stably transmit information.
In some preferred embodiments, the chip package structure further includes a chip 30 and a heat dissipation cover 10, the chip 30 and the heat dissipation cover 10 are connected to the substrate 40, and the chip 30 is located in the heat dissipation cover 10. The heat dissipation cover 10 and the chip 30 are connected by the heat conduction layer 20, and the melting point of the heat conduction layer 20 is higher than that of the solder block 62.
Referring to fig. 3, in the present embodiment, the solder bump 62 of the chip package structure is Sn 58% Bi 42% alloy, and Sn 58% Bi 42% alloy having a melting point of 139 ℃. And the material of the heat conducting layer 20 is an indium layer, and the melting point of indium is 156 ℃. When the chip package structure is connected to a printed circuit board 70 (PCB), the solder block 62 is melted at a high temperature, and the heat conduction layer 20 continues to be in the existing state and is not melted because the melting point of the heat conduction layer 20 is higher than that of the solder block 62, thereby avoiding the increase of the multiple backflow void ratio of the heat conduction layer 20. And the low-temperature reflow can effectively inhibit the warping of the substrate 40, and the packaging performance of the chip packaging structure is improved.
In some preferred embodiments, the conductivity of conductive member 50 is greater than the conductivity of solder mass 62.
In the present embodiment, a plurality of conductive members 50 are disposed on a surface of the substrate 40 facing away from the chip 30, and the conductive members 50 are arranged in a rectangular array, so that a distance between any two adjacent conductive members 50 is a fixed value C. The conductive member 50 can be made of a copper material, a nickel material or other suitable materials, the conductive member 50 is spherical, and the diameter of the conductive member 50 is 80-700 um. The solder block 62 wraps the conductive member 50, the solder block 62 is solder paste SAC305, solder paste SAC307, Sn 58% Bi 42% alloy, and the like, and the thickness of the solder block 62 is 10-30 um.
When the chip package structure is connected to a printed circuit board 70 (PCB), since the conductivity of the conductive member 50 is greater than that of the solder block 62, compared with the solder ball as the conductive member 50 in the related art, the conductive member 50 of the present application is beneficial to the conduction between the chip 30 and the printed circuit board 70, and improves the information transmission efficiency between the chip 30 and the printed circuit board 70.
In some preferred embodiments, the conductive member 50 has a thermal conductivity greater than the thermal conductivity of the solder mass 62.
In the present embodiment, the chip package structure includes a substrate 40, a chip 30, and a heat dissipation cover 10. The heat-dissipating cap 10 and the chip 30 are attached on the same surface of the substrate 40, and the chip 30 is located inside the heat-dissipating cap 10. The heat dissipation cover 10 includes a top portion and a side portion surrounding the top portion, the side portion of the heat dissipation cover 10 is connected to the substrate 40 by an adhesive, and the top portion of the heat dissipation cover 10 is connected to the chip 30 by the heat conductive layer 20. On the surface of the substrate 40 facing away from the chip 30, a plurality of conductive members 50 are disposed, and the conductive members 50 are surrounded by solder bumps 62.
After the chip package structure is connected to the printed circuit board 70 (PCB), except that the heat of the chip 30 is dissipated through the heat dissipating cover 10, because the thermal conductivity of the conductive member 50 is greater than that of the solder block 62, compared with the solder ball in the related art as the conductive member 50, the conductive member 50 of the present application is beneficial to the heat transfer between the chip 30 and the printed circuit board 70, thereby improving the heat transfer efficiency between the chip 30 and the printed circuit board 70 and further reducing the temperature of the chip 30.
The above embodiments are merely illustrative of the application and are not limiting, and although the present application will be described in detail with reference to the embodiments, those skilled in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A chip package structure, comprising:
the surface of the substrate is provided with a plurality of conductive pieces, the conductive pieces are wrapped by the solder layer, and the melting point of the conductive pieces is higher than that of the solder layer.
2. The chip package structure according to claim 1, wherein the conductive member is connected to the solder layer through a connection layer, and the connection layer encapsulates the conductive member.
3. The chip package structure according to claim 1, further comprising a passive component connected to a surface of the substrate facing away from the conductive member, the passive component being covered with a protective material.
4. The chip package structure according to claim 3, further comprising a chip and a heat dissipation cover, wherein the chip and the heat dissipation cover are connected to a surface of the substrate facing away from the conductive member, the passive component and the chip are located in the heat dissipation cover, the heat dissipation cover and the chip are connected through a heat conduction layer, and a melting point of the heat conduction layer is higher than a melting point of the solder layer.
5. The chip package structure according to any one of claims 1 to 4, wherein the conductive member has a conductivity greater than that of the solder layer.
6. The chip package structure according to any one of claims 1 to 4, wherein the conductive member has a thermal conductivity greater than that of the solder layer.
7. A chip connection structure is characterized by comprising a chip packaging structure and a printed circuit board, wherein the chip packaging structure comprises a substrate, the substrate and the printed circuit board are oppositely arranged,
the surface of the substrate facing the printed circuit board is provided with a plurality of conductive pieces;
the surface of the printed circuit board facing the substrate is coated with a plurality of solder blocks arranged at intervals, each solder block corresponds to one conductive piece, the solder blocks are connected with the printed circuit board and the conductive pieces, and the melting point of the conductive pieces is higher than that of the solder blocks.
8. The chip connection structure according to claim 7, wherein the conductive member has a higher conductivity than the solder bumps.
9. The chip connection structure according to claim 7, wherein a thermal conductivity of the conductive member is higher than a thermal conductivity of the solder bump.
10. The chip connection structure according to claim 7, wherein the chip package structure further comprises a chip and a heat dissipation cover, the chip and the heat dissipation cover are connected to a surface of the substrate facing away from the conductive bumps, and the chip is located in the heat dissipation cover,
the heat dissipation cover and the chip are connected through a heat conduction layer, and the melting point of the heat conduction layer is higher than that of the solder block.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011383645.XA CN112542428A (en) | 2020-12-01 | 2020-12-01 | Chip packaging structure and chip connecting structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011383645.XA CN112542428A (en) | 2020-12-01 | 2020-12-01 | Chip packaging structure and chip connecting structure |
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| CN112542428A true CN112542428A (en) | 2021-03-23 |
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| CN202011383645.XA Pending CN112542428A (en) | 2020-12-01 | 2020-12-01 | Chip packaging structure and chip connecting structure |
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| CN111063667A (en) * | 2019-11-12 | 2020-04-24 | 通富微电子股份有限公司 | Integrated circuit package and preparation method thereof |
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