CN112540950B - Reconfigurable processor based on configuration information shared storage and shared storage method thereof - Google Patents
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Abstract
The invention discloses a reconfigurable processor based on configuration information shared storage and a shared storage method thereof, wherein the method comprises the following steps: the processing unit array and the configuration information share storage module; wherein the processing unit array includes: a plurality of processor units; the configuration information sharing storage module comprises: and the plurality of memory banks are used for storing the configuration information of each processor unit. The configuration memories originally arranged in the processing units are moved to the outside of the processing unit array, so that the processing units can share the storage bodies in the configuration information sharing storage module to store the configuration information, the processing units with less configuration information can share the configuration information of the processing units with higher configuration storage pressure, and the space utilization rate of the reconfigurable processor for storing the configuration information is greatly improved.
Description
Technical Field
The invention relates to the field of reconfigurable computing, in particular to a reconfigurable processor based on configuration information shared storage and a shared storage method thereof.
Background
This section is intended to provide a background or context to the embodiments of the invention that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.
Different from the traditional von Neumann computing architecture, reconfigurable computing means that a hardware circuit participating in computing is not fixed and unchanged any more, and hardware can achieve the purpose of accelerating execution of a specific task through cutting and recombination according to the computing characteristics of the task. The FPGA is typical reconfigurable hardware, different designs are quickly mapped into an actual circuit through a look-up table LUT mode, hardware description languages (VHDL and Verilog HDL) and special processes (EEPROM, SRAM, antifuse and the like), rich computing architectures are realized, and the reconfigurable purpose is achieved.
Processors of Coarse-Grained Reconfigurable Architecture (CGRA) have emerged in this context, due to the shortcomings of FPGAs, such as being too small in design granularity, expensive to manufacture, and inferior in performance to ASIC. CGRA is a new computing architecture that combines the flexibility of a general purpose processor with the high performance of an application specific integrated circuit. In the data path of the CGRA, the data bit width of the reconfigurable operation unit is greater than or equal to 4 bits, and thus, the CGRA is referred to as a coarse-grained processor architecture.
The low energy consumption, high performance and high energy efficiency of the CGRA and the flexible and dynamic reconfigurable characteristics enable the CGRA to be suitable for data-intensive computing tasks with very high parallelism. Under the background that rich and colorful applications such as big data, artificial intelligence, everything interconnection and the like are continuously rising nowadays, the CGRA gets more and more attention. Have a more optimized computational strategy in the face of different artificial intelligence algorithms. The architectural features of CGRA itself make it better able to meet these application requirements because it combines the flexibility of a general purpose processor with the high performance of an ASIC.
CGRA also requires "instructions" similar to those in conventional computing architectures to control the execution of computing tasks, referred to as configuration in CGRA. The harvard architecture is a memory structure that separates program instruction storage from data storage, and the division and execution of the system architecture is not separate from von neumann architecture, but can be viewed as a variation of the von neumann architecture. The harvard architecture has two distinct features: the memories for storing instructions and data are independent of each other, and each memory does not allow instructions and data to coexist; two independent buses are used as a special communication path between the CPU and the two memories, so that the two buses can work simultaneously, and the data throughput rate is improved. The configuration and storage of data in the CGRA is also separate and requires far more than two memory cells since the architecture itself has multiple arrays of processing units. In addition, in order to break through the bottleneck of the so-called "storage wall", the storage configured in the CGRA is also designed into a hierarchical structure: both the slowest speed, largest storage capacity DRAM and the fastest speed, smallest storage capacity on-chip SRAM are needed. When designing the size of the configured storage unit SRAM, the speed of the processing unit and the area of the whole circuit are considered to achieve the purpose of compromise.
In a conventional CGRA, there are a plurality of processing units PE, each PE has its own separate configuration Memory unit (CM), and CMs between PEs are independent and cannot share with each other. This, in turn, leads to the problem of insufficient CM storage for some PEs, which have spare CM storage.
In view of the above problems, no effective solution has been proposed.
Disclosure of Invention
The embodiment of the invention provides a reconfigurable processor based on configuration information shared storage, which is used for solving the technical problem that the utilization rate of a configuration storage space is lower because a configuration memory is arranged in each processing unit to store the configuration information of the processing unit in the conventional reconfigurable processor, and comprises the following components: the processing unit array and the configuration information share storage module; wherein the processing unit array includes: a plurality of processor units; the configuration information sharing storage module comprises: and the plurality of memory banks are used for storing the configuration information of each processor unit.
The embodiment of the invention also provides a configuration information sharing and storing method of a reconfigurable processor, which is applied to the reconfigurable processor and used for solving the technical problem that the utilization rate of a configuration storage space is lower because a configuration memory is arranged in each processing unit to store the configuration information of the processing unit in the existing reconfigurable processor, and the device comprises: acquiring the configuration information memory space of a processor unit to be operated, wherein the processor unit to be operated is a processor unit to be operated in a processing unit array; determining one or more memory banks for storing the configuration information of the processor unit to be operated in the configuration information sharing memory module according to the configuration information memory capacity of the processor unit to be operated and the size of the memory space provided by each memory bank in the configuration information sharing memory module; and storing the configuration information of the processor unit to be operated into one or more corresponding memory banks in the configuration information sharing memory module.
The embodiment of the invention also provides computer equipment, which is used for solving the technical problem that the utilization rate of a configuration storage space is low because a configuration storage is arranged in each processing unit in the conventional reconfigurable processor to store the configuration information of the processing unit.
The embodiment of the invention also provides a computer readable storage medium, which is used for solving the technical problem that the utilization rate of a configuration storage space is low because a configuration memory is arranged in each processing unit to store the configuration information of the reconfigurable processor in the prior reconfigurable processor.
The reconfigurable processor provided in the embodiment of the invention is provided with a configuration information sharing storage module outside the processor unit array, and stores the configuration information of each processing unit in the processor unit array by using each memory bank in the configuration information sharing module.
According to the embodiment of the invention, the configuration memories originally arranged in the processing units are moved out of the processing unit array, so that the processing units can share the memory banks in the configuration information sharing memory module to store the configuration information, the processing units with less configuration information can share the configuration information of the processing units with higher configuration storage pressure, and the space utilization rate of the reconfigurable processor for storing the configuration information is greatly improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts. In the drawings:
fig. 1 is a schematic structural diagram of a PEA in a reconfigurable processor provided in the prior art;
fig. 2 is a schematic structural diagram of a PE in a reconfigurable processor provided in the prior art;
FIG. 3 is a schematic diagram of an improvement on a reconfigurable processor provided in an embodiment of the present invention;
FIG. 4 is a diagram of a reconfigurable processor based on configuration information shared storage according to an embodiment of the present invention;
fig. 5 is a flowchart of a configuration information sharing storage method according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a computer device provided in an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention are further described in detail below with reference to the accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.
Before discussing embodiments of the present invention, the processing element Array (i.e. PE Array, PEA for short) and the processing element PE in the CGRA will be described first. To meet the computational requirements, CGRA requires a total of 16 PEA's with 8 × 8 PE's per PEA.
Fig. 1 is a schematic structural diagram of a PEA in a reconfigurable processor provided in the prior art, and as shown in fig. 1, an 8 × 8PEA, a Global register Global Reg of a PE, a Coprocessor Interface, a Data controller Data Control, a Data Shared Memory, a PEA controller, and a configuration controller Context Control are integrated in a PEA module.
Fig. 2 is a schematic structural diagram of a PE in a reconfigurable processor provided in the prior art, and as shown in fig. 2, core portions inside the PE include: PE controller PE Control, configuration memory CM, local register LR, PE Router, PE execution units (ALU, MUL, and LSU), and Debug module Deb. It can be seen that without the improvement of the local sharing scheme, the configuration memory CM is internal to each PE, and each CM has a depth of 16, i.e. it is possible to store 16 pieces of configuration information for use by each PE.
As can be seen from fig. 1 and 2, in the conventional CGRA, each PE has its own separate Configuration Memory (CM), and CMs between PEs are independent and cannot be shared with each other. This, in turn, leads to the problem of insufficient CM storage for some PEs, which have spare CM storage.
In order to solve the foregoing problems, an embodiment of the present invention provides a reconfigurable processor based on configuration information shared storage, where CMs in PEs are moved out and are collected onto a PEA array, and PE arrays are grouped, so that two banks on the CMs can be shared between every two PEs. Therefore, the PEs with less configuration information in the CGRA can share and configure the configuration information of the PE with larger storage pressure, and the storage space utilization rate is improved.
Fig. 3 is a schematic diagram illustrating a principle of improving a reconfigurable processor according to an embodiment of the present invention, and as shown in fig. 3, a context memory originally inside a PE is removed, and then a configuration information sharing memory module (PEA _ context _ memory) is constructed in a PEA array, so that each PE can access more than one Bank.
Fig. 4 is a schematic diagram of a reconfigurable processor based on configuration information shared storage according to an embodiment of the present invention, and as shown in fig. 4, the reconfigurable processor includes: the processing unit array 1 and the configuration information share a memory module 2.
Wherein, the processing unit array 1 includes: a plurality of processor units 101 (PE); the configuration information sharing storage module 2 includes: a plurality of memory banks 201 (banks) for storing configuration information of the respective processor units 101.
It should be noted that since there was originally one CM per PE, there were 8 × 8 PEs, and 64 CMs, the size of the CMs now present on the PEA array must be increased accordingly. Meanwhile, in order for multiple PEs to be able to access simultaneously, the configuration information sharing memory module needs to be divided into 64 independent memory banks (banks), and the depth of each Bank is still 16.
In an embodiment, as shown in fig. 4, the reconfigurable processor provided in the embodiment of the present invention may further include: a multiplexer 3 and a control module 4; the control module 4 is configured to control the multiplexer 3 to change the connection relationship between each processor unit 101 and each memory bank 201.
In a specific implementation, in addition to centralizing the distributed CMs in the conventional CGRA, additional hardware such as the multiplexer 3 and the control module 4 is required to be added, so that the multiplexer 3 connects the processor unit 101 (PE) which performs the calculation to one or more memory banks 201 (Bank) under the control of the control module 4.
In one embodiment, in the reconfigurable processor provided in the embodiment of the present invention, the number of the memory banks 201 in the configuration information sharing memory module 2 is the same as the number of the processor units in the processing unit array 1, and corresponds to each other.
Further, in an embodiment, in the reconfigurable processor provided in the embodiment of the present invention, two processor units 101 in the processing unit array 1 form a pair, and the shared configuration information shares the storage space provided by two storage banks 201 in the storage module. By means of the embodiment, local shared storage of configuration information can be achieved.
For an 8 × 8PEA, there are 64 PEs, and in practical implementation, the 64 PEs in the PEA array may be divided into two groups, the first group is PE0 to PE31, and the second group is PE32 to PE63; the PE at the upper and lower positions form a pair, for example, PE0 and PE32 form a pair, PE1 and PE33 form a pair, and so on. After PE0 and PE32 are paired, configuration storage of two banks, bank0 and Bank1, in the configuration information sharing storage module can be shared, as can sharing of other PEs.
Further, in order to improve the storage utilization, in one embodiment, a processor unit 101 with a usage rate higher than a preset threshold and a processor unit 101 with a usage rate lower than the preset threshold in the processing unit array 1 may be paired. By this embodiment, a PE with a high usage rate (which performs operations frequently) and a PE with a low usage rate (which does not perform operations frequently) are paired to share their banks, so that banks of PEs which do not perform operations can be shared more sufficiently.
Since the algorithm mapping of the CGRA tends to have spatial locality, that is, the operation tends to be concentrated in a certain area. For example, in fig. 4, the upper PE often performs operations, and the lower PE does not often perform operations, so the number of PE0 configurations is likely to exceed 16, and PE32 does not need to store configurations, and then PE0 can use two banks to store configurations. The configuration information sharing and storing of the reconfigurable processor provided in the embodiment of the present invention supports the following centralized mode, taking PE0 and PE32 as an example:
(1) When the needed configurations of PE0 and PE32 are less than 16, the configuration of PE0 is stored in Bank0, and the configuration of PE32 is stored in Bank1;
(2) When the number of the PE0 required configuration is more than 16 and the PE32 does not operate, that is, the configuration is not stored, the configuration of the PE0 is stored in Bank0 and Bank1;
(3) When the required configuration of PE32 is greater than 16 and PE0 does not operate, i.e. does not store the configuration, the configuration of PE0 is stored in Bank0 and Bank1.
It should be noted that, in the implementation, for two PEs (for example, PE0 and PE 32) that share and store the configuration information, a case may occur where Bank0 and Bank1 are both needed to be used, and some access conflict resolution methods may be further adopted to resolve the access conflict.
Optionally, the reconfigurable processor provided in the embodiment of the present invention may further include: the device comprises a global register, a coprocessor interface, a data controller, a data sharing storage module, a processing unit array controller and a configuration controller.
Optionally, in the reconfigurable processor provided in the embodiment of the present invention, the processor unit includes: the system comprises a processing unit controller, a local register, a router, an execution unit and a debugging module. In the embodiment of the invention, after the configuration information sharing module is set in the CGRA, a CM does not need to be set in each PE. The configuration information of the traditional CGRA is stored in the interior of the PEs in a distributed manner, and if some PEs do not perform operation or perform few operations, the storage space of the configuration information is wasted. After the CGRA provided by the embodiment of the invention is changed into local sharing, as each PE can access two banks, the utilization of the storage space is more flexible, and the storage utilization rate is also improved.
As can be seen from the above, the reconfigurable processor based on configuration information shared storage provided in the embodiment of the present invention improves the configuration information originally stored in a PE in a distributed manner into a local shared centralized manner, so that the space utilization rate of configuration storage can be well improved, and the performance of the entire CGRA is further improved.
Based on the same inventive concept, the embodiment of the invention also provides a configuration information sharing storage method of the reconfigurable processor, and the method can be applied to but is not limited to the reconfigurable processor.
As described in the examples below. Because the principle of the method for solving the problems is similar to that of the reconfigurable processor based on the configuration information sharing storage, the implementation of the method can refer to the implementation of the reconfigurable processor based on the configuration information sharing storage, and repeated parts are not described again.
Fig. 5 is a flowchart of a configuration information sharing storage method provided in an embodiment of the present invention, and as shown in fig. 5, the method includes the following steps:
s501, obtaining the configuration information storage capacity of a processor unit to be operated, wherein the processor unit to be operated is a processor unit to be operated in a processing unit array.
S502, according to the configuration information storage volume of the processor unit to be operated and the size of the storage space provided by each storage volume in the configuration information sharing storage module, one or more storage volumes in the configuration information sharing storage module for storing the configuration information of the processor unit to be operated are determined.
S503, storing the configuration information of the processor unit to be operated into one or more corresponding memory banks in the configuration information sharing memory module.
In a specific implementation, the configuration information sharing storage module may be divided into a plurality of memory banks, the number of the memory banks is consistent with the number of PEs in the processing unit array PEA, and each PE corresponds to one memory bank. By setting a local sharing relationship, two PEs can form a pair to share the corresponding memory banks.
The to-be-operated processor unit refers to a PE to be operated to perform an operation task in the processing unit array PEA, for example, any one of PE0 to PE32 that operate frequently. When the size of the memory space (17 pieces of configuration information) required for the processor unit to be operated (e.g., PE 0) to store the configuration information is larger than the size of the memory space (16 pieces of configuration information) provided by its corresponding Bank (Bank 0), the memory Bank (Bank 0) corresponding to the processor unit to be operated and the memory Bank (Bank 32) sharable by the processor unit to be operated in the configuration information sharing memory module store the configuration information of the processor unit to be operated.
Based on the same inventive concept, an embodiment of the present invention further provides a computer device, so as to solve the technical problem that in an existing reconfigurable processor, a configuration memory is arranged inside each processing unit to store configuration information of the processing unit, and a utilization rate of a configuration storage space is low, as shown in fig. 6, fig. 6 is a schematic diagram of a computer device provided in an embodiment of the present invention, as shown in fig. 6, the computer device 60 includes a memory 601, a processor 602, and a computer program stored in the memory 601 and capable of running on the processor 602, and when the processor 602 executes the computer program, the configuration information sharing storage method of the reconfigurable processor is implemented.
Based on the same inventive concept, embodiments of the present invention further provide a computer-readable storage medium, so as to solve the technical problem that, in an existing reconfigurable processor, a configuration memory is arranged inside each processing unit to store configuration information of the processing unit, and the utilization rate of a configuration storage space is low.
In summary, embodiments of the present invention provide a reconfigurable processor based on configuration information sharing storage, a configuration information sharing storage method for a reconfigurable processor, a computer device, and a computer-readable storage medium, where a configuration information sharing storage module is disposed outside a processor unit array, and configuration information of each processing unit in the processor unit array is stored by using each memory bank in the configuration information sharing module. Embodiments of the invention may be applied, but are not limited to, the fields of reconfigurable computing, very Large Scale Integration (VLSI), and computer architecture.
By the embodiment of the invention, the configuration memories originally arranged in the processing units are moved to the outside of the processing unit array, so that the processing units can share the storage bodies in the configuration information sharing storage module to store the configuration information, the processing units with less configuration information can share the configuration information of the processing units with higher configuration storage pressure, and the space utilization rate of the reconfigurable processor for storing the configuration information is greatly improved.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above-mentioned embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, and it should be understood that the above-mentioned embodiments are only examples of the present invention and should not be used to limit the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. A reconfigurable processor sharing storage based on configuration information, comprising: the system comprises a processing unit array (1) and a configuration information sharing storage module (2);
wherein the processing unit array (1) comprises: a plurality of processor units (101);
the configuration information sharing storage module (2) comprises: a plurality of memory banks (201) for storing configuration information for respective processor units (101);
wherein, two processor units (101) in the processing unit array (1) form a pair, and share the storage space provided by two storage banks (201) in the configuration information sharing storage module; one processor unit (101) with the utilization rate higher than a preset threshold value in the processing unit array (1) and one processor unit (101) with the utilization rate lower than the preset threshold value form a pair.
2. The reconfigurable processor of claim 1, further comprising: a multiplexer (3) and a control module (4);
the control module (4) is used for controlling the multiplexer (3) to change the connection relation between each processor unit (101) and each memory bank (201).
3. The reconfigurable processor according to claim 1, wherein the number of memory banks (201) in the configuration information sharing memory module (2) is the same as the number of processor units in the processing unit array (1) and corresponds one to one.
4. A reconfigurable processor according to any of claims 1 to 3, further comprising: the device comprises a global register, a coprocessor interface, a data controller, a data sharing storage module, a processing unit array controller and a configuration controller.
5. A reconfigurable processor according to any of claims 1 to 3, wherein the processor unit comprises: the system comprises a processing unit controller, a local register, a router, an execution unit and a debugging module.
6. A configuration information sharing storage method of a reconfigurable processor, the method being applied to the reconfigurable processor of any one of claims 1 to 5, comprising:
acquiring the configuration information storage capacity of a processor unit to be operated, wherein the processor unit to be operated is a processor unit to be operated in the processing unit array;
determining one or more memory banks for storing the configuration information of the processor unit to be operated in the configuration information sharing memory module according to the configuration information memory capacity of the processor unit to be operated and the size of the memory space provided by each memory bank in the configuration information sharing memory module;
storing the configuration information of the processor unit to be operated into one or more corresponding memory banks in the configuration information sharing memory module;
two processor units in the processing unit array form a pair, and share the storage space provided by two storage banks in the configuration information sharing storage module; and one processor unit with the utilization rate higher than a preset threshold value and one processor unit with the utilization rate lower than the preset threshold value in the processing unit array form a pair.
7. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the configuration information sharing storage method of the reconfigurable processor according to claim 6 when executing the computer program.
8. A computer-readable storage medium storing a computer program for executing the configuration information sharing storage method of the reconfigurable processor according to claim 6.
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