CN103927270B - Shared data caching device for a plurality of coarse-grained dynamic reconfigurable arrays and control method - Google Patents
Shared data caching device for a plurality of coarse-grained dynamic reconfigurable arrays and control method Download PDFInfo
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Abstract
The invention discloses a shared data caching device for a plurality of coarse-grained dynamic reconfigurable arrays and a control method of the shared data caching device. The shared data caching device comprises a reconfigurable array data caching control unit, a reconfigurable array data caching unit, an external memory data prefetching caching unit and a data memory access reconfiguration unit, wherein the reconfigurable array data caching control unit is used for controlling data interaction between the reconfigurable arrays and the reconfigurable array data caching unit and data interaction between the reconfigurable array data caching unit and an external memory, the reconfigurable array data caching unit is used for storing data fetched from the external memory, the external memory data prefetching caching unit is used for prefetching data to be accessed to the reconfigurable array data caching unit, and the data memory access reconfiguration unit is used for sending address information and step length information needed by the reconfigurable array data caching unit. The control method is used for achieving data sharing between the coarse-grained dynamic reconfigurable arrays in a reconfigurable system. By means of the shared data caching device and the control method, access conflict is reduced, data processing time of the reconfigurable system is shortened, and the calculation performance of large-scale coarse-grained reconfigurable arrays is improved.
Description
Technical field
The present invention relates to imbedded reconfigurable design field, in particular it relates to one kind dynamically can weigh towards multiple coarsenesses
The shared data buffer storage of structure array and control method.
Background technology
Processor and special IC（ASIC）It is the computing platform in traditional Computer Systems Organization field, processor
Be characterized by execute instruction concentration dependent instruction come to complete calculate, do not spend change bottom hardware environment.But place
The arithmetic speed of reason device is slow more a lot of than ASIC, and each independent operation has higher executive overhead.Special IC
Feature is that the operation being realized with hardware applying has very high speed, efficiency and precision, but has a disadvantage in that the construction cycle
Oversize, cost is too high, and hardware circuit can not arbitrarily be changed after once making.
The appearance of FPGA Reconfiguration Technologies, the method significantly changing traditional embedded design, Reconfigurable Computation conduct
A kind of computation schema of new time-space domain, obtains and more and more widely pays close attention to, and its main application is included at multimedia
Reason, mobile communication, Digital Signal Processing, data encrypting and deciphering etc..However, closing in military target coupling, Large-number operation, sonar wave beams
Among one-tenth, genome coupling, image vectorization filling, the computer-aided design of integrated circuit etc., with the difference of application scenario,
Reconfigurable system also differs widely to the raising degree of performance.Generally, in system, FPGA quantity is more, overall performance
Higher, carry out averagely by the number of chips of FPGA in system, every piece of FPGA can make arithmetic speed improve 7 ~ 30 times of left sides
The right side, but the speed multiple that averagely every chip block improves is lower.
With the raising calculating performance requirement, the more and more higher of computation complexity, the calculating of the reconstruction structure of coarseness
Resource also rolls up, and completes these applications using multiple reconfigurable arrays, carries out data in multiple reconfigurable arrays simultaneously
When access, access conflict being caused, produce access delay, increased the access time of data so that calculating performance significantly
Reduce.How to reduce the access time of data, improve the access speed of data, become raising reconfigurable system calculating performance and grind
One of study carefully important topic.
Content of the invention
It is an object of the invention to, for the problems referred to above, provide a kind of towards multiple coarseness dynamic reconfigurable arrays
Shared data buffer storage and control method, to improve the performance of extensive coarseness reconfigurable system.
For achieving the above object, the technical solution used in the present invention is：
A kind of shared data caching towards multiple coarseness dynamic reconfigurable arrays, including reconfigurable arrays data buffer storage
Control unit, reconfigurable arrays data buffer storage unit, external memory data prefetches buffer unit, data memory access reconfiguration unit;
Described reconfigurable arrays data buffer storage unit：For storing the data got from external memory storage；
Described external memory data prefetches buffer unit：For prefetching the data that will access to number from external memory storage
According to buffer unit；
Described reconfigurable arrays data buffer storage control unit：For controlling reconfigurable arrays and reconfigurable arrays data buffer storage
Data interaction between unit and reconfigurable arrays data buffer storage unit and external memory storage；
Described data memory access reconfiguration unit：For sending address information and the step information needed for data buffer storage unit.
According to a preferred embodiment of the invention, described reconfigurable arrays data buffer storage control unit is it is characterised in that hard
Part structure includes, address resolver and step-length resolver；
Described address resolver：For parsing the address information receiving from data memory access reconfiguration unit, believed according to address
Breath judges that reconfigurable arrays data buffer storage unit is now to carry out data interaction with external memory storage, or enters with reconfigurable arrays
Row data interaction；
Described step-length resolver：For parsing the step information that receives from data memory access reconfiguration unit, for there being N number of number
According to the data storage cell of storage section, step-length value bag N kind（N span 1-8）, 0,1,2 ... ..., N-1；
According to a preferred embodiment of the invention, described for storing the reconfigurable arrays data got from external memory storage
Buffer unit, comprises N number of storage section（The span of N is 1-8）, the address information according to receiving judges reconfigurable arrays
Data buffer storage unit is to carry out data interaction with external memory storage, or carries out data interaction with reconfigurable arrays, according to step-length
Information determines the storage section that each reconfigurable arrays can access；
Towards the control method of the shared data buffer storage of multiple coarseness dynamic reconfigurable arrays, when multiple coarsenesses
When reconfigurable arrays access reconfigurable arrays data buffer storage unit simultaneously, each reconfigurable arrays can only correspond in the same time can
One of restructuring array data buffer storage unit stores section, with line number M of reconfigurable arrays data buffer storage unit, N is taken
Mould (mod) computing, operation result is n, i.e. M mod N=n, then the reconfigurable arrays data buffer storage unit represented by this line number
It is defined as storing section #n.
Each reconfigurable arrays is determined by step-length with the corresponding relation of storage section.It is N-1 for step-length, restructural battle array
Row #0 accesses storage section #N-1, and reconfigurable arrays #1 accesses storage section #0, and reconfigurable arrays #N-1 accesses storage section #N-
2.For example：If step-length is 0, reconfigurable arrays #0 corresponding storage section #0, reconfigurable arrays #1 corresponding storage section #1, can
Restructuring array #N-1 accesses storage section #N-1；If step-length is 1, reconfigurable arrays #0 accesses storage section #1, restructural
Array #1 accesses storage section #2, and reconfigurable arrays #N-2 accesses storage section #N-1, and reconfigurable arrays #N-1 accesses storage piece
Area #0；If step-length is 2, reconfigurable arrays #0 accesses storage section #2, and reconfigurable arrays #1 accesses storage section #3, restructural
Array #N-1 accesses storage section #1.
Technical scheme is passed through to provide a kind of shared data towards multiple coarseness dynamic reconfigurable arrays to delay
Cryopreservation device and its control method are so that access conflict reduction, data access when multiple reconfigurable arrays access data buffer storage simultaneously
Time reduces, and changes the access mode of data buffer storage in traditional reconfigurable system, thus improve the meter of reconfigurable system
Calculate performance.
Other features and advantages of the present invention will illustrate in the following description, and, partly become from description
Obtain it is clear that or being understood by implementing the present invention.The purpose of the present invention and other advantages can be by the explanations write
In book, claims and accompanying drawing, specifically noted structure is realizing and to obtain.
Below by drawings and Examples, technical scheme is described in further detail.
Brief description
Accompanying drawing is used for providing a further understanding of the present invention, and constitutes a part for description, the reality with the present invention
Apply example and be used for explaining the present invention together, be not construed as limiting the invention.In the accompanying drawings：
Fig. 1 is the shared data buffer storage schematic diagram towards multiple coarseness dynamic reconfigurable arrays；
Fig. 2 is reconfigurable arrays data buffer storage control unit schematic diagram；
Fig. 3 is reconfigurable arrays data buffer storage control unit workflow diagram；
Fig. 4 be the shared data buffer control method towards multiple coarseness dynamic reconfigurable arrays reconfigurable arrays with
The corresponding relation block diagram of storage section；
Fig. 5 is the shared data buffer storage towards multiple coarseness dynamic reconfigurable arrays described in the embodiment of the present invention
And the application connection figure of control method.
Specific embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are illustrated it will be appreciated that preferred reality described herein
Apply example to be merely to illustrate and explain the present invention, be not intended to limit the present invention.
As shown in figure 1, towards the shared data buffer storage of multiple coarseness dynamic reconfigurable arrays and control method, bag
Include reconfigurable arrays data buffer storage control unit：For controlling reconfigurable arrays and reconfigurable arrays data buffer storage unit and can
Data interaction between restructuring array data buffer storage unit and external memory storage；Reconfigurable arrays data buffer storage unit：For depositing
Store up the data got from external memory storage；External memory data prefetches buffer unit：Will for prefetching from external memory storage
The data accessing is to reconfigurable arrays data buffer storage unit；Data memory access reconfiguration unit：Delay for sending reconfigurable arrays data
Address information needed for memory cell and step information.
As shown in Fig. 2 reconfigurable arrays data buffer storage control unit, hardware configuration includes address resolver and step-length parses
Device；Address resolver is used for the address information that parsing receives from data memory access reconfiguration unit, judges to weigh according to address information
Structure array data buffer unit is now to carry out data interaction with external memory storage, or carries out data friendship with reconfigurable arrays
Mutually；Step-length resolver is used for the step information that receives from data memory access reconfiguration unit of parsing, for there being N number of data storage section
Data storage cell, step-length value bag N kind（N span 1-8）, 0,1,2 ... ..., N-1；
As shown in figure 3, in reconfigurable system reconfigurable arrays data buffer storage control unit workflow, first, data
Memory access reconstructed module sends address information and step information to reconfigurable arrays data buffer storage unit, then address resolver according to
The address information receiving, judges it is now reconfigurable arrays access data or reconfigurable arrays data buffer storage unit and outside
Memorizer carries out data interaction.If reconfigurable arrays access data, then step-length resolver is to the step information receiving
Parsed, reconfigurable arrays access corresponding storage section according to corresponding step value, if external memory access number
According to then line access being entered to the data of reconfigurable arrays data buffer storage unit using the access mode of continuation address.
As shown in figure 4, the control method of the shared data buffer storage towards multiple coarseness dynamic reconfigurable arrays.When
When multiple coarse-grained reconfigurable arrays access data buffer storage unit simultaneously, each reconfigurable arrays can only correspond to number in the same time
Store section according to one of buffer unit, with line number M of data storage cell, N is carried out with delivery (mod) computing, operation result
For n, i.e. M mod N=n, then the data storage cell represented by this line number is defined as storing section #n.
Each reconfigurable arrays is determined by step-length with the corresponding relation of storage section.It is N-1 for step-length, restructural battle array
Row #0 accesses storage section #N-1, and reconfigurable arrays #1 accesses storage section #0 ... ..., and reconfigurable arrays #N-1 accesses storage piece
Area #N-2.For example：If step-length is 0, reconfigurable arrays #0 corresponding storage section #0, reconfigurable arrays #1 corresponding storage piece
Area #1 ... ..., reconfigurable arrays #N-1 access storage section #N-1；If step-length is 1, reconfigurable arrays #0 accesses storage piece
Area #1, reconfigurable arrays #1 access storage section #2 ... ..., and reconfigurable arrays #N-2 accesses storage section #N-1, restructural battle array
If row #N-1 accesses storage section, #0 step-length is 2, and reconfigurable arrays #0 accesses storage section #2, and reconfigurable arrays #1 accesses and deposits
Stocker area #3 ... ..., reconfigurable arrays #N-1 access storage section #1.
As shown in figure 5, H.264 the high-definition digital video of agreement decodes（H.264 1080p@30fps HiP@Level4）Adopt
With the proposed shared data buffer storage towards multiple coarseness dynamic reconfigurable arrays and control method, can
The high definition video decoding realizing H.264 1080p@30fps HiP@Level4 requires.The structure of this system includes：As master control
The ARM7TDMI processor of device, reconfigurable arrays data buffer storage, reconfigurable arrays RCA, ahb bus, DDR SDRAM.Select tool
There is ARM7TDMI processor that small-sized, quick, low energy consumption, compiler supported as master cpu, for control system
The scheduling running；Reconfigurable arrays data buffer storage is connected with ARM7TDMI processor by the ahb bus of 32bit, and outside is deposited
The most frequently used embedded external memory storage DDR SDRAM selected by reservoir, supports the data access bit wide of 64bit, has good
Cost performance and observable index；RCA has 4, and each RCA all containing 8 × 8 PE, identifies RCA0 ~ RCA3 successively.Restructural battle array
Column data buffer unit, comprises 4 storage sections, and size is 64KB altogether.
Test as a comparison, be provided with a contrast verification system, the difference with above-mentioned checking system is restructural battle array
In column data buffer unit not by the way of sub-module, the access mode of reconfigurable arrays data storage cell is using tradition
In design, conventional continuation address reads data pattern, and the size of reconfigurable arrays data storage cell is identical with structure.Real
Test result to show, using the shared data buffer storage of multiple coarseness dynamic reconfigurable arrays proposed by the present invention, restructural
The average access conflict of array data memory element compares and reduces by 38.9% than checking system, and data access required time reduces 50%
More than, that is, calculate performance and improve more than 2 times.
Wherein reconfigurable arrays（ReConfigurable Array）Abbreviation RCA；Basic processing unit（Processing
Element）Abbreviation PE.
Finally it should be noted that：The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention,
Although being described in detail to the present invention with reference to the foregoing embodiments, for a person skilled in the art, it still may be used
To modify to the technical scheme described in foregoing embodiments, or equivalent is carried out to wherein some technical characteristics.
All any modification, equivalent substitution and improvement within the spirit and principles in the present invention, made etc., should be included in the present invention's
Within protection domain.
Claims (4)
1. a kind of shared data buffer storage towards multiple coarseness dynamic reconfigurable arrays is it is characterised in that include weighing
Structure array data caching control unit, reconfigurable arrays data buffer storage unit, external memory data prefetch buffer unit, data
Memory access reconfiguration unit；
Described reconfigurable arrays data buffer storage unit：For storing the data got from external memory storage；
Described external memory data prefetches buffer unit：Delay for prefetching, from external memory storage, the data to data that will access
Memory cell；
Described reconfigurable arrays data buffer storage control unit：For controlling reconfigurable arrays and reconfigurable arrays data buffer storage unit
And the data interaction between reconfigurable arrays data buffer storage unit and external memory storage；
Described data memory access reconfiguration unit：For sending address information and the step information needed for data buffer storage unit；
Reconfigurable arrays data buffer storage unit comprises N number of storage section, and the span of N is 1-8, according to the address letter receiving
Breath judges that reconfigurable arrays data buffer storage unit is to interact with external memory storage, or interacts with reconfigurable arrays,
The storage section that each reconfigurable arrays can access is determined according to step information.
2. shared data buffer storage according to claim 1 is it is characterised in that reconfigurable arrays data buffer storage controls list
Unit includes address resolver, step-length resolver；
Described address resolver：For parsing the address information receiving from data memory access reconfiguration unit, sentenced according to address information
Disconnected reconfigurable arrays data buffer storage unit is now to carry out data interaction with external memory storage, or enters line number with reconfigurable arrays
According to interaction；
Described step-length resolver：For parsing the step information receiving from data memory access reconfiguration unit, deposit for there being N number of data
The data storage cell in stocker area, step-length value includes N kind, N span 1-8,0,1,2 ... ..., N-1.
3. the shared number towards multiple coarseness dynamic reconfigurable arrays described in any one in a kind of utilization claim 1-2
According to buffer storage control method it is characterised in that the workflow of described reconfigurable arrays data buffer storage control unit is：First
First, data memory access reconstructed module sends address information and step information to reconfigurable arrays data buffer storage control unit, then
Location resolver, according to the address information receiving, judges it is now that reconfigurable arrays are carried out with reconfigurable arrays data buffer storage unit
Data interaction or reconfigurable arrays data buffer storage unit and external memory storage carry out data interaction；If reconfigurable arrays from
Reading/writing data in reconfigurable arrays data buffer storage unit, then step-length resolver the step information receiving is parsed,
Reconfigurable arrays access corresponding storage section according to corresponding step value；If reconfigurable arrays data buffer storage unit is from outer
Portion's memorizer reading/writing data, then be read out to data using the access mode of continuation address or write restructural number
According to buffer unit.
4. control method according to claim 3 it is characterised in that when multiple coarse-grained reconfigurable arrays access simultaneously can
During restructuring array data buffer storage unit, each reconfigurable arrays can only correspond to reconfigurable arrays data buffer storage unit in the same time
One of storage section, with line number M of reconfigurable arrays data buffer storage unit, N is carried out with mod computing, mod computing is delivery
Computing, operation result is n, i.e. M mod N=n, then the reconfigurable arrays data buffer storage unit represented by this line number is defined as
Storage section #n；
Each reconfigurable arrays is determined by step information with the corresponding relation of storage section；
It is N-1 for step-length, reconfigurable arrays #0 accesses storage section #N-1, reconfigurable arrays #1 accesses storage section #
0 ... ... reconfigurable arrays #N-1 accesses storage section #N-2.
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| CN104679670B (en) * | 2015-03-10 | 2018-01-30 | 东南大学 | A kind of shared data buffer structure and management method towards FFT and FIR |
| CN104915213B (en) * | 2015-06-19 | 2018-05-18 | 东南大学 | A kind of Partial Reconstruction controller of reconfigurable system |
| CN109474641B (en) * | 2019-01-03 | 2020-05-12 | 清华大学 | Reconfigurable switch forwarding engine resolver capable of destroying hardware trojans |
| CN111176582A (en) * | 2019-12-31 | 2020-05-19 | 北京百度网讯科技有限公司 | Matrix storage method, matrix access device and electronic equipment |
| CN111815451A (en) * | 2020-07-20 | 2020-10-23 | 南京艾科朗克信息科技有限公司 | Security counter report table item quick access method based on FPGA |
| CN111930319B (en) * | 2020-09-30 | 2021-09-03 | 北京清微智能科技有限公司 | Data storage and reading method and system for multi-library memory |
| CN112306500B (en) * | 2020-11-30 | 2022-06-07 | 上海交通大学 | Compiling method for reducing multi-class access conflict aiming at coarse-grained reconfigurable structure |
| CN112540950B (en) * | 2020-12-18 | 2023-03-28 | 清华大学 | Reconfigurable processor based on configuration information shared storage and shared storage method thereof |
| CN112732639B (en) * | 2021-04-01 | 2021-06-25 | 南京大学 | Coarse-grained dynamic reconfigurable processor and data processing method thereof |
| CN114064560A (en) * | 2021-11-17 | 2022-02-18 | 上海交通大学 | Configurable scratch pad cache design method for coarse-grained reconfigurable array |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102279729A (en) * | 2011-06-14 | 2011-12-14 | 清华大学 | Method, buffer and processor for dynamic reconfigurable array to schedule configuration information |
| CN102968390A (en) * | 2012-12-13 | 2013-03-13 | 东南大学 | Configuration information cache management method and system based on decoding analysis in advance |
| CN103455367A (en) * | 2013-08-05 | 2013-12-18 | 东南大学 | Management unit and management method for realizing multi-task scheduling in reconfigurable system |
| CN103488585A (en) * | 2013-09-27 | 2014-01-01 | 东南大学 | Controller for realizing configuration information cache update in reconfigurable system |
-
2014
- 2014-04-28 CN CN201410176151.2A patent/CN103927270B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102279729A (en) * | 2011-06-14 | 2011-12-14 | 清华大学 | Method, buffer and processor for dynamic reconfigurable array to schedule configuration information |
| CN102968390A (en) * | 2012-12-13 | 2013-03-13 | 东南大学 | Configuration information cache management method and system based on decoding analysis in advance |
| CN103455367A (en) * | 2013-08-05 | 2013-12-18 | 东南大学 | Management unit and management method for realizing multi-task scheduling in reconfigurable system |
| CN103488585A (en) * | 2013-09-27 | 2014-01-01 | 东南大学 | Controller for realizing configuration information cache update in reconfigurable system |
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