CN112534802A - Method for operating image pickup apparatus - Google Patents
Method for operating image pickup apparatus Download PDFInfo
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- CN112534802A CN112534802A CN201980051728.8A CN201980051728A CN112534802A CN 112534802 A CN112534802 A CN 112534802A CN 201980051728 A CN201980051728 A CN 201980051728A CN 112534802 A CN112534802 A CN 112534802A
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- 238000000034 method Methods 0.000 title claims description 60
- 238000003384 imaging method Methods 0.000 claims abstract description 119
- 238000006243 chemical reaction Methods 0.000 claims abstract description 97
- 239000003990 capacitor Substances 0.000 claims abstract description 43
- 229910044991 metal oxide Inorganic materials 0.000 claims description 44
- 150000004706 metal oxides Chemical class 0.000 claims description 44
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 229910052733 gallium Inorganic materials 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- 229910052738 indium Inorganic materials 0.000 claims description 8
- 229910052725 zinc Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 229910052727 yttrium Inorganic materials 0.000 claims description 5
- 229910052684 Cerium Inorganic materials 0.000 claims description 4
- 229910052779 Neodymium Inorganic materials 0.000 claims description 4
- 229910052735 hafnium Inorganic materials 0.000 claims description 4
- 229910052746 lanthanum Inorganic materials 0.000 claims description 4
- 229910052726 zirconium Inorganic materials 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 210
- 230000006870 function Effects 0.000 description 38
- 238000010586 diagram Methods 0.000 description 26
- 239000004065 semiconductor Substances 0.000 description 25
- 239000010408 film Substances 0.000 description 24
- 239000011701 zinc Substances 0.000 description 20
- 239000000758 substrate Substances 0.000 description 19
- 229910052751 metal Inorganic materials 0.000 description 17
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 16
- 239000000463 material Substances 0.000 description 16
- 239000002184 metal Substances 0.000 description 15
- 238000001514 detection method Methods 0.000 description 14
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 11
- 229910052711 selenium Inorganic materials 0.000 description 11
- 239000011669 selenium Substances 0.000 description 11
- 230000008878 coupling Effects 0.000 description 10
- 238000010168 coupling process Methods 0.000 description 10
- 238000005859 coupling reaction Methods 0.000 description 10
- 230000001276 controlling effect Effects 0.000 description 9
- 230000000875 corresponding effect Effects 0.000 description 9
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 9
- 230000003287 optical effect Effects 0.000 description 9
- 230000004048 modification Effects 0.000 description 8
- 238000012986 modification Methods 0.000 description 8
- 230000005855 radiation Effects 0.000 description 8
- 239000011787 zinc oxide Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000000203 mixture Substances 0.000 description 7
- 238000012544 monitoring process Methods 0.000 description 7
- 238000011017 operating method Methods 0.000 description 7
- 230000035945 sensitivity Effects 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 5
- 239000001257 hydrogen Substances 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 230000009471 action Effects 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 4
- 238000002149 energy-dispersive X-ray emission spectroscopy Methods 0.000 description 4
- 229910001195 gallium oxide Inorganic materials 0.000 description 4
- 230000007257 malfunction Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000002441 X-ray diffraction Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- -1 copper indium diselenide Compound Chemical class 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910001882 dioxygen Inorganic materials 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 229910003437 indium oxide Inorganic materials 0.000 description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 210000000707 wrist Anatomy 0.000 description 3
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052790 beryllium Inorganic materials 0.000 description 2
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- ZMIGMASIKSOYAM-UHFFFAOYSA-N cerium Chemical compound [Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce] ZMIGMASIKSOYAM-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000002524 electron diffraction data Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000005525 hole transport Effects 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 238000003331 infrared imaging Methods 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000002159 nanocrystal Substances 0.000 description 2
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 229910052720 vanadium Inorganic materials 0.000 description 2
- GPPXJZIENCGNKB-UHFFFAOYSA-N vanadium Chemical compound [V]#[V] GPPXJZIENCGNKB-UHFFFAOYSA-N 0.000 description 2
- 229910001233 yttria-stabilized zirconia Inorganic materials 0.000 description 2
- XMWRBQBLMFGWIX-UHFFFAOYSA-N C60 fullerene Chemical compound C12=C3C(C4=C56)=C7C8=C5C5=C9C%10=C6C6=C4C1=C1C4=C6C6=C%10C%10=C9C9=C%11C5=C8C5=C8C7=C3C3=C7C2=C1C1=C2C4=C6C4=C%10C6=C9C9=C%11C5=C5C8=C3C3=C7C1=C1C2=C4C6=C2C9=C5C3=C12 XMWRBQBLMFGWIX-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910020187 CeF3 Inorganic materials 0.000 description 1
- 241000486661 Ceramica Species 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910001632 barium fluoride Inorganic materials 0.000 description 1
- 238000005513 bias potential Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 description 1
- 229910001634 calcium fluoride Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000018044 dehydration Effects 0.000 description 1
- 238000006297 dehydration reaction Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 229910003472 fullerene Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 150000002632 lipids Chemical class 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
- 229910000476 molybdenum oxide Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- PQQKPALAQIIWST-UHFFFAOYSA-N oxomolybdenum Chemical compound [Mo]=O PQQKPALAQIIWST-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000005424 photoluminescence Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- SZJFGTWFLXTOHF-UHFFFAOYSA-N silicon tetraazide Chemical compound [N-]=[N+]=N[Si](N=[N+]=[N-])(N=[N+]=[N-])N=[N+]=[N-] SZJFGTWFLXTOHF-UHFFFAOYSA-N 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
- H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14616—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor characterised by the channel of the transistor, e.g. channel having a doping gradient
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14665—Imagers using a photoconductor layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/766—Addressed sensors, e.g. MOS or CMOS sensors comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Abstract
Provided is an imaging device including miniaturized pixels. The pixel is provided with a photoelectric conversion element, first and second transistors, and a capacitor. One electrode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor, the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, and the gate of the second transistor is electrically connected to one electrode of the capacitor. In the first period, a first potential is supplied to the other electrode of the capacitor and the first transistor is turned on, whereby image pickup data corresponding to the illuminance of light irradiated to the photoelectric conversion element is written in the pixel. In addition, in the second period, a second potential is supplied to the other electrode of the capacitor, whereby image data is read out from the pixel.
Description
Technical Field
One embodiment of the present invention relates to an imaging apparatus and an operating method thereof.
Note that one embodiment of the present invention is not limited to the above-described technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process (process), a machine (machine), a product (manufacture), or a composition (machine). Thus, more specifically, examples of the technical field of one embodiment of the present invention disclosed in the present specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, an illumination device, a power storage device, a storage device, an imaging device, methods for driving these devices, and methods for manufacturing these devices.
Note that in this specification and the like, a semiconductor device refers to all devices which can operate by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. In addition, the memory device, the display device, the imaging device, and the electronic apparatus may include a semiconductor device.
Background
A technique of forming a transistor using an oxide semiconductor thin film formed over a substrate is attracting attention. For example, patent document 1 discloses an image pickup device in which a transistor including an oxide semiconductor, which is a transistor with extremely low off-state current, is used for a pixel circuit.
Further, patent document 2 discloses an imaging device in which pixels are miniaturized.
[ Prior Art document ]
[ patent document ]
[ patent document 1] Japanese patent application laid-open No. 2011-119711
[ patent document 2] International publication No. 2016/158439
Disclosure of Invention
Technical problem to be solved by the invention
By miniaturizing the pixels included in the imaging device, high-resolution imaging data can be acquired. On the other hand, in particular, in the front-illuminated image pickup apparatus, the light detection sensitivity of the pixel may be lowered by reducing the light receiving area of the photoelectric conversion element due to miniaturization of the photoelectric conversion element included in the pixel. Further, miniaturization of pixels may reduce the amount of charge that can be held in the pixels as imaging data. As a result, the S/N ratio of the imaging data may decrease particularly in imaging under low illumination.
Accordingly, it is an object of one embodiment of the present invention to provide a method for operating an imaging device including miniaturized pixels. Another object of one embodiment of the present invention is to provide a method for operating an imaging apparatus having a large light receiving area. Another object of one embodiment of the present invention is to provide a method for operating an imaging apparatus having high light detection sensitivity. Another object of one embodiment of the present invention is to provide a method for operating an imaging apparatus having a high S/N ratio. Another object of one embodiment of the present invention is to provide a method for operating an imaging apparatus capable of acquiring high-quality imaging data. Another object of one embodiment of the present invention is to provide a method for operating an imaging apparatus with a high dynamic range. Another object of one embodiment of the present invention is to provide an operating method of an imaging apparatus that suppresses occurrence of malfunction. Another object of one embodiment of the present invention is to provide a method for operating an imaging apparatus with high reliability. Another object of one embodiment of the present invention is to provide a novel method for operating an image pickup apparatus. Another object of one embodiment of the present invention is to provide a novel imaging apparatus and the like. Another object of one embodiment of the present invention is to provide a novel semiconductor device and the like.
Note that the description of these objects does not hinder the existence of other objects. It is not necessary for one embodiment of the invention to achieve all of the above objectives. The objects other than these objects will be apparent from the description of the specification, drawings, claims, and the like, and the objects other than these can be derived from the description of the specification, drawings, claims, and the like.
Means for solving the problems
One aspect of the present invention is a method of operating an image pickup apparatus including a pixel, wherein the pixel includes a photoelectric conversion element, a first transistor, a second transistor, and a capacitor, one electrode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor, the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, and a gate of the second transistor is electrically connected to one electrode of the capacitor, and in a first period, image pickup data corresponding to illuminance of light irradiated to the photoelectric conversion element is written into the pixel by supplying a first potential to the other electrode of the capacitor and turning the first transistor into an on state, and in a second period, image pickup data is read out from the pixel by supplying a second potential to the other electrode of the capacitor.
In the above aspect, the second transistor may be in an off state in the first period, and the second transistor may be in an on state in the second period.
In the above aspect, the second transistor may be an n-channel transistor, and the second potential may be higher than the first potential.
In the above aspect, the second transistor may be a p-channel transistor, and the second potential may be lower than the first potential.
In addition, one aspect of the present invention is an operating method of an imaging device including a pixel, wherein the pixel includes a photoelectric conversion element, a first transistor, a second transistor, a third transistor, and a capacitor, one electrode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor, the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, a gate of the second transistor is electrically connected to one of a source and a drain of the third transistor, one of the source and the drain of the third transistor is electrically connected to one electrode of the capacitor, the third transistor is turned on during a first period to reset a potential of the gate of the second transistor, the first potential is supplied to the other electrode of the capacitor to turn the first transistor on and turn the third transistor off during a second period, thereby, image pickup data corresponding to the illuminance of light irradiated to the photoelectric conversion element is written into the pixel, and in the third period, the second potential is supplied to the other electrode of the capacitor, thereby reading out the image pickup data from the pixel.
In the above aspect, the second transistor may be in an off state in the first and second periods, and the second transistor may be in an on state in the third period.
In the above aspect, the second transistor may be an n-channel transistor, and the second potential may be higher than the first potential.
In the above aspect, the second transistor may be a p-channel transistor, and the second potential may be lower than the first potential.
In the above aspect, the first transistor may include a metal oxide In the channel formation region, and the metal oxide may include In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).
Effects of the invention
By using one embodiment of the present invention, an operating method of an imaging device including miniaturized pixels can be provided. Further, a method of operating an image pickup apparatus having a large light receiving area can be provided. Further, an operation method of the image pickup apparatus with high light detection sensitivity can be provided. Further, an operation method of the image pickup apparatus having a high S/N ratio can be provided. Further, an operating method of the image pickup apparatus capable of acquiring high-quality image pickup data can be provided. Further, an operating method of the image pickup apparatus with a high dynamic range can be provided. Further, an operation method of the image pickup apparatus can be provided which suppresses occurrence of malfunction. Further, a method of operating an imaging apparatus with high reliability can be provided. Further, a novel method of operating an image pickup apparatus can be provided. Further, a novel image pickup apparatus and the like can be provided. In addition, a novel semiconductor device and the like can be provided.
Drawings
Fig. 1A is a diagram illustrating a configuration example of a pixel. Fig. 1B is a diagram illustrating an example of the operation of a pixel.
Fig. 2A is a diagram illustrating a configuration example of a pixel. Fig. 2B is a diagram illustrating an example of the operation of the pixel.
Fig. 3 is a diagram illustrating a configuration example of an imaging device.
Fig. 4 is a diagram illustrating a configuration example of an imaging device.
Fig. 5 is a diagram illustrating a configuration example of an imaging device.
Fig. 6 is a diagram illustrating a configuration example of an imaging device.
Fig. 7 is a diagram illustrating a configuration example of an imaging device.
Fig. 8 is a diagram for explaining an example of the operation of the imaging device.
Fig. 9A to 9D are diagrams illustrating examples of the structure of a pixel.
Fig. 10A to 10C are diagrams illustrating a configuration example of an imaging device.
Fig. 11A to 11E are diagrams for explaining a configuration example of an imaging device.
Fig. 12A and 12B are diagrams illustrating a configuration example of an imaging device.
Fig. 13A and 13B are diagrams illustrating a configuration example of an imaging device.
Fig. 14A to 14C are diagrams for explaining a configuration example of an imaging device.
Fig. 15a1 to 15A3 and 15B1 to 15B3 are perspective views illustrating examples of the structure of a package and a module that house an imaging device.
Fig. 16A to 16F are diagrams illustrating an example of an electronic device.
Detailed Description
The following describes embodiments with reference to the drawings. Note that a person skilled in the art can easily understand the fact that the embodiments can be implemented in a plurality of different forms, and the modes and details can be changed into various forms without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.
The embodiments shown below may be combined as appropriate. In addition, when a plurality of configuration examples are shown in one embodiment, these configuration examples may be combined with each other as appropriate.
Although the block diagram in the present specification shows the components classified by their functions in the independent blocks, the actual components are difficult to be clearly classified by their functions, and one component may have a plurality of functions.
In the drawings and the like, the size, the thickness of layers, or regions are sometimes exaggerated for convenience. Therefore, the present invention is not limited to the dimensions in the drawings. In the drawings, desirable examples are schematically shown, and therefore the present invention is not limited to the shapes, numerical values, or the like shown in the drawings.
In the drawings and the like, the same components, components having the same functions, components formed of the same material, components formed at the same time, and the like may be denoted by the same reference numerals, and a repetitive description thereof may be omitted.
In this specification and the like, "film" and "layer" may be interchanged with each other. For example, the "conductive layer" may be sometimes changed to a "conductive film". In addition, the "insulating film" may be sometimes replaced with an "insulating layer".
In this specification and the like, the terms expressing arrangement such as "upper" and "lower" are not limited to the positional relationship of the constituent elements being "directly above …" or "directly below …". For example, the phrase "a gate electrode over a gate insulating layer" includes a case where another constituent element is included between the gate insulating layer and the gate electrode.
In addition, the ordinal numbers such as "first", "second", "third", and the like in the present specification and the like are attached to avoid confusion of the constituent elements, and are not intended to be limited in number.
In this specification and the like, "electrically connected" includes a case where connection is made by "an element having some kind of electrical action". Here, the "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connection targets. For example, "an element having a certain electric function" includes not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.
Note that in this specification and the like, the "voltage" often refers to a potential difference between a certain potential and a reference potential (for example, a ground potential). Therefore, the voltage and the potential difference can be exchanged with each other. In addition, "voltage" is sometimes used to mean "potential". Note that "potential" may be used to mean "a potential difference from a certain potential (a reference potential, a ground potential, or the like)". Therefore, "potential" and "voltage" may sometimes be exchanged with each other.
In this specification and the like, a transistor refers to a device including at least three terminals, i.e., a gate, a drain, and a source. The transistor has a region (hereinafter also referred to as a channel formation region) which forms a channel between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region where current mainly flows.
In addition, when transistors having different polarities are used, or when the direction of current flow during circuit operation changes, the source function and the drain function may be interchanged. Therefore, in this specification and the like, "source" and "drain" may be interchanged with each other.
In this specification and the like, unless otherwise specified, an off-state current refers to a drain current when a transistor is in an off state (also referred to as a non-conductive state or an interruption state). In the above description of the off-state current, the drain may be referred to as the source. That is, the off-state current sometimes refers to the source current when the transistor is in the off-state. In addition, the leakage current may have the same meaning as the off-state current. In this specification and the like, an off-state current may refer to a current flowing between a source and a drain when a transistor is in an off state, for example.
In this specification and the like, a metal oxide (metal oxide) refers to an oxide of a metal in a broad sense. The metal Oxide is classified into an Oxide insulator, an Oxide conductor (including a transparent Oxide conductor), an Oxide Semiconductor (also referred to as Oxide Semiconductor), and the like.
For example, when a metal oxide is used for a channel formation region of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, in the case where the metal oxide has at least one of an amplifying action, a rectifying action, and a switching action, the metal oxide may be referred to as a metal oxide semiconductor (metal oxide semiconductor). That is, a transistor including metal oxide in a channel formation region may be referred to as an "oxide semiconductor transistor" or an "OS transistor".
In this specification and the like, a metal oxide containing nitrogen is also referred to as a metal oxide (metal oxide) in some cases. In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride (metal oxynitride). Details of the metal oxide will be described later.
(embodiment mode 1)
In this embodiment, an imaging apparatus and an operating method thereof according to an embodiment of the present invention will be described.
One embodiment of the present invention is a method for operating an imaging device provided with a pixel including no selection transistor. The pixel includes an amplifying transistor having a function of amplifying the written image pickup data when reading out the image pickup data, and a capacitor having a function of holding the written image pickup data as electric charges. The gate of the amplifying transistor is electrically connected to one electrode of the capacitor.
In the method of operating the imaging device according to the one aspect of the present invention, the potential supplied to the other electrode of the capacitor is set to be different between a period in which imaging data is written into the pixel and a period in which imaging data is read from the pixel. Specifically, the potential supplied to the other electrode of the capacitor is adjusted so that the amplifying transistor is turned off during writing of image data to the pixel and turned on during reading of image data from the pixel. Thus, the image pickup device can be normally operated without providing a selection transistor in a pixel.
In the n-channel transistor in this specification and the like, for example, the off state refers to a state in which a voltage Vgs of a gate with respect to a source is lower than a threshold voltage, and the on state refers to a state in which the voltage Vgs of the gate with respect to the source is equal to or higher than the threshold voltage. In the p-channel transistor, for example, the off state refers to a state in which a gate voltage Vgs of the source is higher than a threshold voltage, and the on state refers to a state in which the gate voltage Vgs of the source is equal to or lower than the threshold voltage.
Since the number of transistors provided in a pixel can be reduced by not providing a selection transistor in the pixel, the pixel can be miniaturized. In particular, when the image pickup device according to one embodiment of the present invention is a front-illuminated image pickup device, the light receiving area of the photoelectric conversion element provided in the pixel can be increased, and the light detection sensitivity of the pixel can be improved. Further, since the occupation area of the capacitor, the amplifying transistor, and the like provided in the pixel can be increased, the amount of charge which can be held in the pixel as image data can be increased. This makes it possible to increase the S/N ratio while miniaturizing the pixels. Therefore, the imaging apparatus according to one embodiment of the present invention can acquire high-quality imaging data.
< structural example 1 of pixel >
Fig. 1A is a diagram illustrating an example of the configuration of a pixel 10 that can be used in an imaging device according to an embodiment of the present invention. The pixel 10 includes a photoelectric conversion element 11, a transistor 12, a transistor 13, a capacitor 14, and a transistor 15. Here, the transistor 12, the transistor 13, and the transistor 15 may be n-channel transistors. In addition, for convenience of explanation, the current source 16 not included in the pixel 10 is illustrated in fig. 1A. Note that the current source 16 not included in the pixel 10 is also shown in other drawings showing a structural example of the pixel 10.
One electrode (anode in fig. 1A) of the photoelectric conversion element 11 is electrically connected to one of a source and a drain of the transistor 12. The other of the source and the drain of the transistor 12 is electrically connected to one of the source and the drain of the transistor 13. One of a source and a drain of the transistor 13 is electrically connected to one electrode of the capacitor 14. One electrode of the capacitor 14 is electrically connected to the gate of the transistor 15.
Here, a wiring electrically connecting the other of the source and the drain of the transistor 12, the one of the source and the drain of the transistor 13, the one electrode of the capacitor 14, and the gate of the transistor 15 is referred to as a node FD.
The gate of the transistor 12 is electrically connected to the wiring 22. The gate of the transistor 13 is electrically connected to the wiring 23. The other electrode of the capacitor 14 is electrically connected to the wiring 24. One of a source and a drain of the transistor 15 is electrically connected to the wiring 25. The wiring 25 is electrically connected to one electrode of the current source 16.
The other electrode (cathode in fig. 1A) of the photoelectric conversion element 11 is electrically connected to the wiring 31. The other of the source and the drain of the transistor 13 is electrically connected to the wiring 33. The other of the source and the drain of the transistor 15 is electrically connected to the wiring 35. The other electrode of the current source 16 is electrically connected to the wiring 36.
The wiring 22 and the wiring 23 are used as gate lines, a signal for controlling on/off of the transistor 12 is supplied to the transistor 12 through the wiring 22, and a signal for controlling on/off of the transistor 13 is supplied to the transistor 13 through the wiring 23. The wiring 24 is used as a signal line, and a signal is supplied to the other electrode of the capacitor 14 through the wiring 24. The wiring 25 is used as a data line, and image pickup data written in the pixel 10 is output to the outside of the pixel 10 as a signal OUT through the wiring 25.
The wiring 31, the wiring 35, and the wiring 36 are used as power supply lines, and a fixed potential can be supplied to the wiring 31, the wiring 35, and the wiring 36, for example. Here, a potential supplied to the wiring 31 is referred to as a potential VPD, a potential supplied to the wiring 35 is referred to as a potential VPI, and a potential supplied to the wiring 36 is referred to as a potential VPO. The potential VPD may be, for example, a high potential.
In this specification and the like, the low potential may be, for example, a ground potential or a negative potential. The high potential may be higher than the low potential, and may be, for example, a positive potential. Further, the low potential may be a positive potential and the high potential may be a positive potential higher than the low potential.
The wiring 33 is used as a reset power supply line, and the potential VRS as a reset potential can be supplied to the wiring 33. The potential VRS may be a potential lower than the potential VPD, and may be a negative potential, for example.
A photodiode can be used as the photoelectric conversion element 11. When light is irradiated to the photoelectric conversion element 11, electric charges corresponding to the illuminance of the light are stored in the photoelectric conversion element 11.
The transistor 12 is used as a transfer transistor that controls transfer of the charge stored to the photoelectric conversion element 11 by exposure of the photoelectric conversion element 11 to the node FD. By turning on the transistor 12, the charge stored in the photoelectric conversion element 11 is transferred into the node FD. Thereby, the potential of the node FD becomes a potential corresponding to the illuminance of light irradiated to the photoelectric conversion element 11, and image data is written in the pixel 10. Then, the transistor 12 is turned off, whereby electric charge is held in the node FD. Therefore, the image pickup data written in the pixel 10 is held.
The transistor 13 is used as a reset transistor that controls resetting of the potential of the node FD. By turning on the transistors 12 and 13 before starting exposure to the photoelectric conversion element 11, the charges stored in the photoelectric conversion element 11 and the node FD can be reset. Thereby, the potential of the node FD can be reset. Specifically, the potential of the node FD may be, for example, the potential VRS.
The capacitor 14 has a function of holding the electric charge and the like transferred from the photoelectric conversion element 11 into the node FD. The transistor 15 is used as an amplifying transistor for amplifying the image pickup data held in the pixel 10 and reading out the image pickup data to the outside of the pixel 10.
The current source 16 has a function of setting the current flowing in the wiring 25 to a fixed value. The current source 16 may be constituted by a transistor, for example. When the current source 16 is a transistor, one of a source and a drain of the transistor may be electrically connected to the wiring 25, and the other of the source and the drain of the transistor may be electrically connected to the wiring 36. In addition, a bias potential may be supplied to the gate of the transistor, which is used as a bias transistor as it is.
As described above, the wiring 35 and the wiring 36 are supplied with a fixed potential. Therefore, it can be said that the transistor 15 and the current source 16 constitute a source-grounded amplifier circuit or a source follower circuit. Here, in the pixel 10 having the structure shown in fig. 1A, the transistor 15 is an n-channel transistor. Therefore, it can be said that the source-grounded amplifier circuit is configured when the potential VPI is lower than the potential VPO, and the source follower circuit is configured when the potential VPI is higher than the potential VPO. For example, when the potential VPI is low and the potential VPO is high, the transistor 15 and the current source 16 constitute a grounded-source amplifier circuit. When the potential VPI is high and the potential VPO is low, it can be said that the transistor 15 and the current source 16 constitute a source follower circuit.
In the current source 16 shown in fig. 1A, the direction of a current flowing through the current source 16 when a source ground amplifying circuit is constituted by the transistor 15 and the current source 16 is indicated by an arrow. The direction of a current flowing through the current source when the source-grounded amplification circuit is constituted by the current source and the amplification transistor is also indicated by an arrow in the current source in the other drawings.
In the case where the transistor 15 is an n-channel transistor as shown in fig. 1A, when the transistor 15 and the current source 16 constitute a grounded-source amplifier circuit and the gate voltage of the transistor 15, that is, the potential VFD of the node FD becomes equal to or higher than the potential "VPI + Vth", the transistor 15 is turned on and the potential of the wiring 25 becomes the potential "VFD + Vth". When the transistor 15 and the current source 16 form a source follower circuit and the gate voltage of the transistor 15 becomes equal to or higher than the potential "VPO + Vth + VCSN", the transistor 15 is turned on and the potential of the wiring 25 becomes the potential "VFD-Vth". Here, the potential Vth represents the threshold voltage of the transistor 15. In the case where the transistor 15 is an n-channel transistor, when a source follower circuit is configured by the transistor 15 and the current source 16, a current flows through the current source 16 when a difference between a potential of one electrode of the current source 16 and a potential of the other electrode of the current source 16 is equal to or greater than the potential VCSN.
When the source-grounded amplifier circuit is configured by the transistor 15 and the current source 16, the pixel 10 can be operated at high speed. On the other hand, when the transistor 15 and the current source 16 constitute a source follower circuit, the accuracy of the potential of the signal OUT can be made high.
As shown in fig. 1A, the pixel 10 is not provided with a selection transistor having a function of selecting the pixel 10 from which image pickup data is read, and may be provided in such a manner that, for example, one of a source and a drain is electrically connected to one of electrodes of a source and a drain of the transistor 15 and the other of the source and the drain is electrically connected to the wiring 25. Thereby, one of the source and the drain of the transistor 15 functioning as an amplifying transistor is electrically connected to the wiring 25 functioning as a data line, and the other of the source and the drain of the transistor 15 is electrically connected to the wiring 35 functioning as a power supply line.
Here, by using a transistor with extremely low off-state current as the transistor 12 and the transistor 13, the period during which the charge is held in the node FD can be extremely long. Therefore, the image pickup data written in the pixel 10 can be held for an extremely long period of time. Thus, as will be described in detail later, a global shutter method in which charge accumulation operation is performed simultaneously in all pixels can be employed without complicating the circuit configuration and/or the operation method. As a transistor with extremely low off-state current, an OS transistor can be given, for example.
The transistor 15 may be an OS transistor. An image pickup device according to one embodiment of the present invention can be manufactured by a simple method in which all transistors included in the image pickup device use OS transistors.
Further, an OS transistor and a transistor using silicon for a channel formation region (hereinafter, Si transistor) may be used in any combination. In addition, Si transistors may be used for all transistors. Examples of the Si transistor include a transistor including amorphous silicon, a transistor including crystalline silicon (typically, low-temperature polysilicon), a transistor including single crystal silicon, and the like.
Fig. 1B is a timing chart illustrating an example of the operation of the pixel 10 having the structure shown in fig. 1A. In fig. 1B and the like, "H" represents a high potential, and "L" represents a low potential. As described above, the potential Vth represents the threshold voltage of the transistor 15.
Here, the transistor 15 and the current source 16 constitute a source-grounded amplifier circuit. The capacitive coupling coefficient of the node FD is k (k is a real number greater than 0 and equal to or less than 1). Here, k is calculated from the capacitance of the capacitor 14, the gate capacitance of the transistor 15, the parasitic capacitance, and the like.
Further, detailed changes in potential due to circuit configuration, operation timing, and the like are not considered, such as potential distribution, coupling, and loss. The same applies to timing charts other than fig. 1B.
At time T1 to time T2, the potentials of the wiring 22 and the wiring 23 are set to the high potential and the potential of the wiring 24 is set to the potential Vwrite, whereby the transistor 12 and the transistor 13 are turned on, and the potential of the node FD becomes the potential VRS of the reset potential. Thereby, the charges stored in the photoelectric conversion element 11 and the node FD are reset. Therefore, the time T1 to the time T2 can be said to be a period during which the reset operation is performed. Note that the potential Vwrite will be described later.
Here, the potential VRS may be a potential equal to or lower than the potential "VPI + Vth", and the transistor 15 is an n-channel transistor as described above. Therefore, at the time T1 to the time T2, the transistor 15 is in an off state.
At time T2 to time T3, the potential of the wiring 22 is set to a high potential and the potential of the wiring 23 is set to a low potential, whereby the transistor 12 is turned on and the transistor 13 is turned off. Thereby, the electric charges stored to the photoelectric conversion element 11 according to the illuminance of the light irradiated to the photoelectric conversion element 11 are transferred into the node FD. Here, for example, since the potential VPD, which may be a high potential, is higher than the potential VRS, the potential of the node FD rises in accordance with the illuminance of light irradiated to the photoelectric conversion element 11. Thereby, the image data is written to the pixels 10. Therefore, the time T2 to the time T3 can be said to be a period during which the write operation is performed. Note that the potential of the wiring 24 is a potential Vwrite.
At time T3 to time T4, the potentials of the wiring 22 and the wiring 23 are set to the low potential, and the transistor 12 and the transistor 13 are turned off. Thereby, the writing operation is ended and the potential of the node FD is held. Therefore, the image data is held in the pixel 10. Therefore, the time T3 to the time T4 can be said to be a period during which the holding operation is performed. Note that the potential of the wiring 24 is a potential Vwrite.
Here, at time T2 to time T4, the magnitude of the potential VRS is preferably set so that the illuminance transistor 15 is in the off state regardless of the light applied to the photoelectric conversion element 11. Specifically, it is preferable that the height of the potential VRS is set so that the potential of the gate of the transistor 15 is lower than the potential "VPI + Vth" even when light of which the maximum illuminance is assumed among the light irradiated to the photoelectric conversion element 11 is irradiated to the photoelectric conversion element 11. For example, when the potential VPI is a ground potential, the potential VRS is preferably a negative potential. This can suppress an unintended current from flowing through the wiring 25 via the transistor 15. Therefore, malfunction of the imaging apparatus according to one embodiment of the present invention can be suppressed.
At time T4 to time T5, the potentials of the wirings 22 and 23 are low. Thereby, the transistor 12 and the transistor 13 are turned off. The potential of the wiring 24 is set to the potential Vread. Here, the potential Vread is a potential higher than the potential Vwrite. Thus, the potential of the capacitive coupling node FD is increased by the potential "k (Vread-Vwrite)", and the transistor 15 is turned on. The transistor 15 is turned on, whereby the potential of the wiring 25 serving as a data line becomes a potential corresponding to the potential of the node FD. That is, the image pickup data held in the pixel 10 is read out. Therefore, the time T4 to the time T5 can be said to be a period during which the read operation is performed.
Here, the height of the potential "Vread-Vwrite" is preferably equal to or higher than the potential "{ (VPI + Vth) -VRS }/k". This makes it possible to turn on the transistor 15 independently of the illuminance of light applied to the photoelectric conversion element 11. Specifically, even when the potential of the node FD at the time T3 to the time T4 is the potential VRS, the potential of the gate of the transistor 15 can be equal to or higher than the potential "VPI + Vth", and therefore the transistor 15 can be turned on. Accordingly, even when the illuminance of light applied to the photoelectric conversion element 11 is low, the image data can be accurately read from the pixels 10, and therefore the dynamic range of the image pickup apparatus according to one embodiment of the present invention can be increased.
At time T5 to time T6, the potentials of the wiring 22 and the wiring 23 are low, and the potential of the wiring 24 is set to the potential Vwrite. Thereby, the transistor 12, the transistor 13, and the transistor 15 are turned off, and the reading operation is completed. The above is an example of the operation of the pixel 10. As described above, the potential of the wiring 24 is set to the potential Vwrite during the period in which the write operation is performed, and is set to the potential Vread during the period in which the read operation is performed. Therefore, the potential Vwrite can be said to be a writing potential, and the potential Vread can be said to be a reading potential.
As described above, although the pixel 10 does not include the selection transistor, the pixel 10 can be operated in the method shown in fig. 1B. By adopting a structure in which the pixel 10 does not include a selection transistor, the number of transistors provided in the pixel 10 can be reduced, and therefore, the pixel 10 can be miniaturized. In particular, when the image pickup apparatus according to one embodiment of the present invention is a front-illuminated image pickup apparatus, the light receiving area of the photoelectric conversion element 11 can be increased, and the light detection sensitivity of the pixel 10 can be improved. Further, the occupied area of the capacitor 14, the transistor 15, and the like can be increased, and the amount of charge that can be held at the node FD can be increased. This makes it possible to increase the S/N ratio while miniaturizing the pixel 10. Therefore, the imaging apparatus according to one embodiment of the present invention can obtain high-quality imaging data.
< structural example 2 of pixel >
Fig. 2A is a diagram illustrating a structural example of the pixel 10, and is a modified example of the structure shown in fig. 1A. The structure of the pixel 10 shown in fig. 2A differs from the structure of the pixel 10 shown in fig. 1A in that: the transistor 15 is a p-channel transistor.
In the pixel 10 of the structure shown in fig. 2A, the cathode of the photoelectric conversion element 11 may be electrically connected to one of the source and the drain of the transistor 12, and the anode of the photoelectric conversion element 11 may be electrically connected to the wiring 31. The potential VPD may be, for example, a low potential. Further, the potential VRS may be a potential higher than the potential VPD.
Similarly to the pixel 10 having the structure shown in fig. 1A, even if the pixel 10 has the structure shown in fig. 2A, it can be said that the transistor 15 and the current source 16 constitute a source-grounded amplifier circuit or a source follower circuit. Here, in the pixel 10 having the structure shown in fig. 2A, the transistor 15 is a p-channel transistor. Therefore, it can be said that the source-grounded amplifier circuit is configured when the potential VPI is higher than the potential VPO, and the source follower circuit is configured when the potential VPI is lower than the potential VPO. For example, when the potential VPI is high and the potential VPO is low, the transistor 15 and the current source 16 constitute a grounded-source amplifier circuit. When the potential VPI is low and the potential VPO is high, it can be said that the transistor 15 and the current source 16 constitute a source follower circuit.
In the case where the transistor 15 is a p-channel transistor as shown in fig. 2A, when the source-grounded amplifier circuit is configured by the transistor 15 and the current source 16, the gate voltage of the transistor 15, that is, the potential VFD of the node FD becomes equal to or lower than the potential "VPI + Vth", whereby the transistor 15 is turned on, and the potential of the wiring 25 becomes the potential "VFD-Vth". When the source follower circuit is configured by the transistor 15 and the current source 16, the gate voltage of the transistor 15 becomes equal to or lower than the potential "VPO + Vth-VCSP", the transistor 15 is turned on, and the potential of the wiring 25 becomes the potential "VFD + Vth". Here, when the transistor 15 is a p-channel transistor, if a source follower circuit is configured by the transistor 15 and the current source 16, a current flows through the current source 16 when a difference between a potential of one electrode of the current source 16 and a potential of the other electrode of the current source 16 is equal to or less than the potential VCSP (a difference between a potential of the other electrode of the current source 16 and a potential of one electrode of the current source 16 is equal to or more than the potential VCSP).
Fig. 2B is a timing chart illustrating an example of the operation of the pixel 10 having the structure shown in fig. 2A.
At time T1 to time T2, the potentials of the wiring 22 and the wiring 23 are set to the high potential, whereby the transistor 12 and the transistor 13 are turned on, and the potential of the node FD becomes the potential VRS of the reset potential. Thereby, the charges stored in the photoelectric conversion element 11 and the node FD are reset. Here, the potential VRS may be a potential equal to or higher than the potential "VPI + Vth", and the transistor 15 may be a p-channel transistor as described above. Therefore, at time T1 to time T2, the transistor 15 is turned off. Note that the potential of the wiring 24 is a potential Vwrite.
At time T2 to time T3, the potential of the wiring 22 is high and the potential of the wiring 23 is low, whereby the transistor 12 is turned on and the transistor 13 is turned off. Thereby, the electric charges stored to the photoelectric conversion element 11 according to the illuminance of the light irradiated to the photoelectric conversion element 11 are transferred into the node FD. Here, for example, since the potential VPD, which may be a low potential, is lower than the potential VRS, the potential of the node FD decreases according to the illuminance of light irradiated to the photoelectric conversion element 11. Thereby, the image data is written to the pixels 10. Note that the potential of the wiring 24 is a potential Vwrite.
At time T3 to time T4, the potentials of the wiring 22 and the wiring 23 are set to the low potential, and the transistor 12 and the transistor 13 are turned off. Thereby, the writing operation is ended and the potential of the node FD is held. Therefore, the image data is held in the pixel 10. Note that the potential of the wiring 24 is a potential Vwrite.
Here, at time T2 to time T4, the height of the potential VRS is preferably set so that the illuminance transistor 15 is in the off state regardless of the light irradiated to the photoelectric conversion element 11. Specifically, it is preferable that the height of the potential VRS is set so that the potential of the gate of the transistor 15 is higher than the potential "VPI + Vth" even when light of which the maximum illuminance is assumed among the light irradiated to the photoelectric conversion element 11 is irradiated to the photoelectric conversion element 11. This can suppress an unintended current from flowing through the wiring 25 via the transistor 15. Therefore, malfunction of the imaging apparatus according to one embodiment of the present invention can be suppressed.
At time T4 to time T5, the potentials of the wirings 22 and 23 are low. Thereby, the transistor 12 and the transistor 13 are turned off. The potential of the wiring 24 is set to the potential Vread. Here, the potential Vread is lower than the potential Vwrite. Thus, the potential of the capacitive coupling node FD is lowered by the potential "k (Vwrite-Vread)", and the transistor 15 is turned on. The transistor 15 is turned on, whereby the potential of the wiring 25 serving as a data line becomes a potential corresponding to the potential of the node FD. That is, the image pickup data held in the pixel 10 is read out.
Here, the height of the potential "Vwrite-Vread" is preferably equal to or higher than the potential "{ VRS- (VPI + Vth) }/k". This makes it possible to turn on the transistor 15 independently of the illuminance of light applied to the photoelectric conversion element 11. Specifically, even when the potential of the node FD at the time T3 to the time T4 is the potential VRS, the potential of the gate of the transistor 15 can be equal to or lower than the potential "VPI + Vth", and therefore the transistor 15 can be turned on. Accordingly, even when the illuminance of light applied to the photoelectric conversion element 11 is low, the image data can be accurately read from the pixels 10, and therefore the dynamic range of the image pickup apparatus according to one embodiment of the present invention can be increased.
At time T5 to time T6, the potentials of the wiring 22 and the wiring 23 are low, and the potential of the wiring 24 is set to the potential Vwrite. Thereby, the transistor 12, the transistor 13, and the transistor 15 are turned off, and the reading operation is completed. The above is an example of the operation of the pixel 10 having the structure shown in fig. 2A.
In the pixel 10 having the structure shown in fig. 1A and the pixel 10 having the structure shown in fig. 2A, one or both of the transistor 12 and the transistor 13 may be a p-channel transistor. In the pixel 10 having the structure shown in the following drawings, one or both of the transistor 12 and the transistor 13 may be a p-channel transistor. In this case, the magnitude relationship of the potential is switched as necessary, and thus the operation of the pixel 10 can be referred to fig. 1B, fig. 2B, and the like.
< structural example 1 of imaging apparatus >
Fig. 3 is a block diagram illustrating a configuration example of an imaging device according to an embodiment of the present invention. The image pickup apparatus includes an image pickup section 41, a signal generation circuit 44, a gate drive circuit 42, a CDS circuit 45, a data drive circuit 46, an a/D conversion circuit 47, and a power supply circuit 48. In the imaging unit 41, the pixels 10 are arranged in a matrix.
As described above, the wiring 25 is electrically connected to one electrode of the current source 16. For example, a structure in which one wiring 25 is electrically connected to one current source 16 may be employed. Note that when the pixel 10 has the structure shown in fig. 2A, the direction of the current flowing through the current source 16 is reversed from the direction shown by the arrow in fig. 3.
The signal generation circuit 44 is electrically connected to the pixel 10 through the wiring 24 serving as a signal line. For example, a configuration may be adopted in which 1 row of pixels 10 is electrically connected to the signal generation circuit 44 through 1 wiring 24.
The gate driver circuit 42 is electrically connected to the pixel 10 through the wiring 22 and the wiring 23 serving as gate lines. For example, the gate driver circuit 42 may be electrically connected to the pixels 10 in 1 row via 1 wiring 22 and 1 wiring 23.
The CDS circuit 45 is electrically connected to the pixel 10 through a wiring 25 serving as a data line. For example, a structure in which 1 column of pixels 10 is electrically connected to the CDS circuit 45 through 1 wiring 25 may be employed.
The data driving circuit 46 is electrically connected to the CDS circuit 45, and the a/D conversion circuit 47 is electrically connected to the data driving circuit 46.
The power supply circuit 48 is electrically connected to the pixel 10 through the wiring 31 and the wiring 35 which serve as power supply lines and the wiring 33 which serves as a reset power supply line. For example, all the pixels 10 may be electrically connected to the power supply circuit 48 through 1 wiring 31, 1 wiring 33, and 1 wiring 35.
The signal generation circuit 44 has a function of generating the potential Vwrite and the potential Vread. That is, the signal generation circuit 44 has a function of generating a write signal of a signal supplied to the pixel 10 when the pixel 10 performs a write operation and a read signal of a signal supplied to the pixel 10 when the pixel 10 performs a read operation.
The gate drive circuit 42 has a function of generating a signal for controlling on/off of the transistor 12 and a signal for controlling on/off of the transistor 13. For example, when the transistor 12 is an n-channel transistor, the gate driver circuit 42 may generate a signal at a high potential and supply the signal to the transistor 12 when the transistor 12 is turned on.
In the imaging device having the configuration shown in fig. 3, a circuit having a function of generating the potential Vwrite and the potential Vread is different from a circuit having a function of generating a signal for controlling on/off of the transistor 12 and the transistor 13. Thus, the potential Vwrite and the potential Vread can be made different from the signal for controlling on/off of the transistor 12 and the transistor 13. For example, even when the gate driver circuit 42 does not generate a negative potential, the potential Vwrite or the potential Vread can be set to a negative potential. Thus, for example, the difference between the potential Vwrite and the potential Vread can be made larger than when a circuit having a function of generating the potential Vwrite and the potential Vread is the same as a circuit having a function of generating a signal for controlling on/off of the transistor 12 and the transistor 13. Therefore, the dynamic range of the imaging device according to one embodiment of the present invention can be increased.
The CDS circuit 45 has a function of reducing noise of image pickup data by performing correlated double sampling or the like on a signal OUT of the image pickup data output from the pixel 10. The data driving circuit 46 has a function of selecting a column of the pixel 10 from which the held image pickup data is read. The a/D conversion circuit 47 has a function of converting image pickup data of analog data into digital data. The power supply circuit 48 has a function of generating the potential VPD, the potential VRS, and the potential VPI.
< structural example 2 of imaging apparatus >
Fig. 4 is a block diagram illustrating a configuration example of an imaging device according to an embodiment of the present invention, and is a modification example of the configuration shown in fig. 3. The structure of the image pickup apparatus shown in fig. 4 is different from that shown in fig. 3 in that: a light sensor 49 is provided.
The light sensor 49 is electrically connected to the power supply circuit 48. The light sensor 49 has a function of detecting the illuminance of external light. The photosensor 49 may include elements having the same structure as the photoelectric conversion element 11.
By providing the imaging device with the configuration shown in fig. 4, the potential VRS, which is the reset potential, can be changed according to the illuminance of external light. For example, when the pixel 10 has the structure shown in fig. 1A, the potential VRS can be made high in an environment where the outside light illuminance is low, that is, dark, and can be made low in an environment where the outside light illuminance is high, that is, bright. In addition, for example, when the pixel 10 has the structure shown in fig. 2A, the potential VRS can be made low in a dark environment and can be made high in a bright environment. This suppresses excessive shading from being excessively black and excessive highlight from being excessively white, and can improve the dynamic range of the imaging device according to one embodiment of the present invention.
Fig. 5 is a block diagram illustrating a configuration example of an imaging device according to an embodiment of the present invention, and is a modification example of the configuration shown in fig. 4. The structure of the image pickup apparatus shown in fig. 5 is different from that shown in fig. 4 in that: the optical sensor 49 is electrically connected to the signal generation circuit 44.
By providing the imaging device with the configuration shown in fig. 5, the potential Vwrite and/or the potential Vread can be changed in accordance with the external illuminance. For example, the difference between the potential Vread and the potential Vwrite can be made large in a dark environment, and the difference between the potential Vread and the potential Vwrite can be made small in a bright environment. This suppresses excessive shading from being excessively black and excessive highlight from being excessively white, and can improve the dynamic range of the imaging device according to one embodiment of the present invention.
< structural example 3 of imaging apparatus >
Fig. 6 is a block diagram illustrating a configuration example of an imaging device according to an embodiment of the present invention, and is a modification example of the configuration shown in fig. 3. The structure of the image pickup apparatus shown in fig. 6 is different from that shown in fig. 3 in that: a detection circuit 50 is provided.
The detection circuit 50 is electrically connected to the wiring 25. The detection circuit 50 has a function of detecting the potential of the wiring 25 and controlling the operations of the gate driver circuit 42, the signal generation circuit 44, and the power supply circuit 48 based on the detected potential. The imaging device including the detection circuit 50 can adjust the height of the potential VRS, the potential Vread, or the potential Vwrite, for example, in accordance with the height of the potential of the wiring 25 at the time of performing the reading operation. For example, when the pixel 10 has the structure shown in fig. 1A, the potential VRS can be made low when the potential of the wiring 25 is high at the time of the reading operation. Alternatively, the difference between the potential Vread and the potential Vwrite may be made small. Thus, since the potential of the node FD can be lowered, occurrence of high blooming can be suppressed.
In addition, for example, when the pixel 10 has the structure shown in fig. 1A, the potential VRS can be set high when the potential of the wiring 25 is low during the reading operation. Alternatively, the difference between the potential Vread and the potential Vwrite may be made large. This can increase the potential of the node FD, thereby suppressing the occurrence of shadow over-black.
In addition, for example, when the pixel 10 has the structure shown in fig. 2A, the potential VRS can be made high when the potential of the wiring 25 is low at the time of performing the reading operation. Alternatively, the difference between the potential Vwrite and the potential Vread may be made small. This can increase the potential of the node FD, and therefore, occurrence of high blooming can be suppressed.
In addition, for example, when the pixel 10 has the structure shown in fig. 2A, the potential VRS can be made low when the potential of the wiring 25 at the time of the reading operation is high. Alternatively, the difference between the potential Vwrite and the potential Vread may be made large. Thus, the potential of the node FD can be lowered, so that occurrence of shadow over-black can be suppressed.
Next, after the height of the potential VRS, the potential Vread, or the potential Vwrite is adjusted as described above, the reset operation, the write operation, and the read operation can be performed again. As described above, in the imaging device according to one embodiment of the present invention, it is possible to suppress the occurrence of the shadow and the highlight and the blackness, and to improve the dynamic range.
The detection circuit 50 does not need to have all the functions of the control gate drive circuit 42, the signal generation circuit 44, and the power supply circuit 48. For example, when the potential VRS is not adjusted in accordance with the potential of the wiring 25, the detection circuit 50 does not need to have a function of controlling the power supply circuit 48.
< structural example 4 of imaging apparatus >
Fig. 7 is a block diagram illustrating a configuration example of an imaging device according to an embodiment of the present invention, and is a modification example of the configuration shown in fig. 3. The structure of the image pickup apparatus shown in fig. 7 is different from that shown in fig. 3 in that: all the pixels 10 are electrically connected to the gate driver circuit 42 through 1 wiring 22 and 1 wiring 23. In the imaging device having the configuration shown in fig. 7, the imaging unit 41 is provided with n rows (n is an integer of 2 or more) of pixels 10.
In this specification and the like, for example, the 1 st row of pixels 10 is referred to as a pixel 10[1], the 2 nd row of pixels 10 is referred to as a pixel 10[2], and the nth row of pixels 10 is referred to as a pixel 10[ n ]. For example, the wiring 24 electrically connected to the pixel 10[1] is referred to as a wiring 24[1], the wiring 24 electrically connected to the pixel 10[2] is referred to as a wiring 24[2], and the wiring 24 electrically connected to the pixel 10[ n ] is referred to as a wiring 24[ n ].
In the imaging apparatus having the configuration shown in fig. 7, the writing of imaging data to the pixels 10 is performed in a global shutter system. Thus, it is possible to secure the simultaneity of image capturing and easily obtain an image with less distortion even in the case where the subject moves rapidly. Therefore, the image pickup apparatus shown in fig. 7 can obtain high-quality image pickup data.
Fig. 8 is a timing chart for explaining an example of the operation of the n rows of pixels 10 included in the imaging apparatus having the configuration shown in fig. 7. Here, the pixel 10 has the structure shown in fig. 1A. In addition, the potential Vread is higher than the potential Vwrite.
In this specification and the like, for example, the pixel 10[1]]Included node FD is noted as node FD [1]]Pixel 10[2]]Included node FD is noted as node FD [2]]Pixel 10[ n ]]Included node FD is noted as node FD [ n ]]. In addition, for example, node FD [1] is set]The capacitive coupling coefficient k is recorded as the capacitive coupling coefficient k1Node FD [2]]The capacitive coupling coefficient k is recorded as the capacitive coupling coefficient k2Node FD [ n ]]The capacitive coupling coefficient k is recorded as the capacitive coupling coefficient kn。
At time T1 to time T2, the potentials of the wirings 22 and 23 are set to the high potential, whereby all the transistors 12 and 13 are turned on, and the potentials of the nodes FD [1] to FD [ n ] become the potential VRS of the reset potential. Thereby, the charges stored in all the photoelectric conversion elements 11 and the nodes FD [1] to FD [ n ] are reset. Note that the potentials of the wirings 24[1] to 24[ n ] are the potential Vwrite.
Here, the potential VRS may be a potential equal to or lower than the potential "VPI + Vth", and the transistor 15 is an n-channel transistor as described above. Therefore, all the transistors 15 are turned off at the time T1 to the time T2.
At time T2 to time T3, the potential of the wiring 22 is set to a high potential and the potential of the wiring 23 is set to a low potential, whereby all the transistors 12 are turned on and all the transistors 13 are turned off. Thereby, the electric charges stored to the photoelectric conversion element 11 according to the illuminance of the light irradiated to the photoelectric conversion element 11 are transferred into the node FD. Here, for example, since the potential VPD, which may be a high potential, is higher than the potential VRS, the potentials of the nodes FD [1] to FD [ n ] rise in accordance with the illuminance of light irradiated to the photoelectric conversion element 11. Thereby, the imaging data is written to the pixels 10[1] to 10[ n ] in the global shutter method. Note that the potentials of the wirings 24[1] to 24[ n ] are the potential Vwrite.
At time T3 to time T4, the potentials of the wirings 22 and 23 are set to the low potential, and all the transistors 12 and 13 are turned off. Thus, the writing operation is ended and the potentials of the nodes FD [1] to FD [ n ] are held. Accordingly, the image pickup data is held in the pixels 10[1] to 10[ n ]. Here, as described above, it is preferable that the height of the potential VRS be set so that the illuminance transistor 15 is in the off state regardless of the light applied to the photoelectric conversion element 11 from the time T2 to the time T4. Note that the potentials of the wirings 24[1] to 24[ n ] are the potential Vwrite.
At time T4 to time T5, the potentials of the wirings 22 and 23 are set to the low potential. Thereby, all the transistors 12 and all the transistors 13 are turned off. In addition, the wiring 24[1]]Becomes a potential Vread, and makes the wiring 24[2]]To the wiring 24[ n ]]Becomes a potential Vwrite. Thereby, node FD [1 is coupled through capacitance]Is increased by a potential "k1(Vread-Vwrite) ", and is thus set at the pixel 10[1]]Transistor 15 in (1) is turned on. The transistor 15 is turned on, whereby the potential of the wiring 25 serving as a data line becomes corresponding to the node FD [1]]The potential of (2). That is, held at the pixel 10[1]]The image pickup data in (1) is read out.
At time T5 to time T6, the potentials of the wirings 22 and 23 are set to the low potential and the potentials of the wirings 24[1] to 24[ n ] are set to the potential Vwrite. Thereby, all the transistors 12, all the transistors 13, and all the transistors 15 are turned off, and the reading of the image data held in the pixel 10[1] is completed.
At time T6 to time T7, the potentials of the wirings 22 and 23 are set to the low potential.Thereby, all the transistors 12 and all the transistors 13 are turned off. In addition, the wiring 24[2]]Becomes a potential Vread, and makes the wiring 24[1]]And wiring 24[3]]To the wiring 24[ n ]]Becomes a potential Vwrite. Thereby, node FD [2] is coupled through capacitance]Is increased by a potential "k2(Vread-Vwrite) ", and is thus disposed at pixel 10[2]]Transistor 15 in (1) is turned on. The transistor 15 is turned on, whereby the potential of the wiring 25 serving as a data line becomes corresponding to the node FD [2]]The potential of (2). That is, held at the pixel 10[2]]The image pickup data in (1) is read out.
At time T7 to time T8, the potentials of the wirings 22 and 23 are set to the low potential and the potentials of the wirings 24[1] to 24[ n ] are set to the potential Vwrite. Thereby, all the transistors 12, all the transistors 13, and all the transistors 15 are turned off, and the reading of the image data held in the pixel 10[2] is completed.
After the readout of the image data held in the pixel 10[2] is completed, the potentials of the wirings 24[3] to 24[ n-1] are sequentially changed to the potential Vread, whereby the image data held in the pixel 10[3] to the pixel 10[ n-1] are sequentially read.
At time T8 to time T9, the potentials of the wirings 22 and 23 are set to the low potential. Thereby, all the transistors 12 and all the transistors 13 are turned off. In addition, the wiring 24[ n ]]Becomes a potential Vread and makes the wiring 24[1]]To wiring 24[ n-1]]Becomes a potential Vwrite. Thereby, node FD [ n ] is coupled through capacitance]Is increased by a potential "kn(Vread-Vwrite) ", and is thus set at the pixel 10[ n]Transistor 15 in (1) is turned on. The transistor 15 is turned on, whereby the potential of the wiring 25 serving as a data line becomes corresponding to the node FD [ n ]]The potential of (2). That is, held at the pixel 10n]The image pickup data in (1) is read out.
At time T9 to time T10, the potentials of the wirings 22 and 23 are set to the low potential and the potentials of the wirings 24[1] to 24[ n ] are set to the potential Vwrite. Thereby, all the transistors 12, all the transistors 13, and all the transistors 15 are turned off, and the reading of the image data held in the pixel 10[ n ] is completed.
As described above, the image pickup data held in all the pixels 10 is read out. Here, as shown in fig. 8, after the end of the write operation, it is necessary to hold the charge for a long period of time in the node FD [ n ], for example. Therefore, as described above, it is preferable to use a transistor having extremely low off-state current, such as an OS transistor, for the transistors 12 and 13.
< structural example 3 of pixel >
Fig. 9A, 9B, 9C, and 9D are diagrams illustrating examples of the structure of the pixel 10, and are modified examples of the structure shown in fig. 1A. The structure of the pixel 10 shown in fig. 9A is different from the structure of the pixel 10 shown in fig. 1A in that: one of a source and a drain of the transistor 13 is electrically connected to one electrode of the photoelectric conversion element 11.
In addition, the structure of the pixel 10 shown in fig. 9B is different from the structure of the pixel 10 shown in fig. 1A in that: the transistor 13 is not provided. In the pixel 10 having the structure shown in fig. 9B, the potential of the node FD can be reset by turning on the transistor 12 and setting the relationship between the potential VPD and the potential of the node FD so as to be forward-biased with respect to the photoelectric conversion element 11. For example, the potential of the node FD can be reset by setting the potential VPD to a negative potential similarly to the potential VRS shown in fig. 1A.
The structure of the pixel 10 shown in fig. 9C and 9D is different from the structure of the pixel 10 shown in fig. 1A in that: the transistors 12, 13, and 15 are provided with back gates. In the pixel 10 of the structure shown in fig. 9C, the on-state current of the transistor can be increased by supplying, for example, a positive potential to the back gates of the transistor 12, the transistor 13, and the transistor 15, and the off-state current of the transistor can be decreased by supplying a negative potential to them.
In the pixel 10 of the structure shown in fig. 9D, the back gate is electrically connected to the front gate. Thus, the on-state current of the transistor can be increased and the off-state current can be reduced while the potential of the back gate can be easily controlled.
In addition, a structure in which each transistor can perform appropriate operation may also be employed, such as a structure in which fig. 9C and 9D are combined. In addition, the pixel 10 may include a transistor provided with no back gate.
This embodiment can be combined with the description of the other embodiments as appropriate.
(embodiment mode 2)
In this embodiment, a configuration example of an imaging device according to an embodiment of the present invention will be described.
Fig. 10A is a sectional view illustrating a configuration example of an imaging device according to an embodiment of the present invention. Fig. 10A illustrates a photoelectric conversion element 11 provided in a substrate 101, a transistor 12 and a transistor 15 in which a channel formation region is provided in the substrate 101, and a capacitor 14 provided over the transistor 12 and the transistor 15.
As the substrate 101, a silicon substrate can be used, for example. For example, single crystal silicon, amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like can be used. When a silicon substrate is used as the substrate 101, the transistor 12, the transistor 15, and the like are Si transistors.
In the photoelectric conversion element 11, the layer 103a may be p+The type region, layer 103b may be a p-type region, and layer 103c may be n+A molding region. In addition, the layer 103b is provided with a region 105 for electrically connecting the layer 103c to the conductive layer 107 constituting the wiring 31. For example, region 105 may be p+A molding region. The image pickup apparatus having the structure shown in fig. 10A may be a front-illuminated image pickup apparatus.
Fig. 10B is a sectional view of a cross section along the chain line a1-a2, and is a sectional view in the channel width direction of the transistor 12. Note that a cross section in the channel width direction of another transistor such as the transistor 15 provided over the substrate 101 may have a structure similar to that shown in fig. 10B.
As shown in fig. 10B, the channel formation region of the transistor 12 is provided on a convex portion of the substrate 101, and a gate electrode is provided so as to cover the convex portion. That is, the transistor 12 having the structure shown in fig. 10A and 10B can be a fin transistor.
Fig. 10C is a sectional view illustrating a configuration example of an imaging device according to an embodiment of the present invention, and the configuration of the transistor 12 and the transistor 15 is different from that of the imaging device shown in fig. 10A. In fig. 10C, a flat substrate 101 is provided with a transistor 12 and a transistor 15. Therefore, the transistors 12 and 15 having the structure shown in fig. 10C can be said to be planar transistors.
Fig. 11A is a sectional view illustrating a configuration example of an image pickup device according to an embodiment of the present invention, and a transistor 12 is provided above a transistor 15 provided in a substrate 101. That is, transistors constituting the imaging device according to one embodiment of the present invention are stacked. With the above configuration, the pixels included in the imaging device according to one embodiment of the present invention can be miniaturized. This can increase the light receiving area of the photoelectric conversion element 11, and can improve the light detection sensitivity of the pixels included in the imaging device according to one embodiment of the present invention. In addition, the S/N ratio can be improved. As described above, the imaging apparatus according to one embodiment of the present invention can obtain high-quality imaging data. The transistor 13 and the like may have the same structure as the transistor 12.
Here, in the image pickup device of the structure shown in fig. 11A, the transistor 12 may be an OS transistor. Thus, as described in embodiment 1, since the capacitor 14 can hold the charge for a long period of time, the image data can be written to the pixels included in the image pickup device according to one embodiment of the present invention in a global shutter manner.
Fig. 11B shows a detailed OS transistor. The OS transistor shown in fig. 11B has a self-aligned structure in which an insulating layer is provided over a stack of a metal oxide layer and a conductive layer, and a groove reaching the metal oxide layer is provided in the insulating layer, whereby a source electrode 205 and a drain electrode 206 are formed.
The OS transistor may include a gate electrode 201 and a gate insulating film 202 in addition to the channel formation region 113, the source region 203, and the drain region 204 formed in the metal oxide layer 207. In the trench, at least a gate insulating film 202 and a gate electrode 201 are provided. In the OS transistor having the structure shown in fig. 11B, a metal oxide layer 207B is provided on the metal oxide layer 207a, and a metal oxide layer 207c, a source electrode 205, and a drain electrode 206 are provided on the metal oxide layer 207B. In fig. 11B and the like, for example, the metal oxide layer 207a, the metal oxide layer 207B, and the metal oxide layer 207c may be collectively referred to as a metal oxide layer 207.
As shown in fig. 11C, the OS transistor may have a self-aligned structure in which the source region 203 and the drain region 204 are formed in the metal oxide layer 207 using the gate electrode 201 as a mask.
Alternatively, as shown in fig. 11D, a top-gate transistor of a non-self-aligned type having a region where the source electrode 205 or the drain electrode 206 overlaps with the gate electrode 201 may be employed.
Fig. 11A, 11B, 11C, and 11D illustrate a structure in which the transistor 12 includes a back gate electrode 111. The on-state current of the transistor 12 can be increased by supplying a positive potential to the back gate electrode 111, for example, and the off-state current of the transistor 12 can be decreased by supplying a negative potential thereto.
Fig. 11E is a sectional view along a cross-sectional plane of the dot-dash line B1-B2 shown in fig. 11B, and is a sectional view in the channel width direction of the transistor 12. As shown in fig. 11E, the back gate electrode 111 may be electrically connected to gate electrodes 201 provided so as to face each other with a gate insulating film 202 or the like interposed therebetween. This can simplify the control of the potential of the back gate electrode 111, and at the same time, increase the on-state current of the transistor 12 and reduce the off-state current thereof. In addition, the transistor 12 may not include the back gate electrode 111.
An insulating layer 109 having a function of preventing diffusion of hydrogen is provided between a region where the OS transistor is formed and a region where the Si transistor is formed. That is, for example, an insulating layer 109 may be provided between the transistor 15 and the transistor 12. Hydrogen in the insulating layer provided in the vicinity of the channel formation region of the Si transistor terminates a dangling bond of silicon. On the other hand, hydrogen in the insulating layer provided in the vicinity of the channel formation region of the OS transistor may be one of the causes of generating carriers in the metal oxide layer.
By using the insulating layer 109 to enclose hydrogen in the layer provided with the Si transistor, the reliability of the Si transistor can be improved. In addition, since diffusion of hydrogen from the layer provided with the Si transistor to the layer provided with the OS transistor is suppressed, the reliability of the OS transistor can also be improved.
For the insulating layer 109, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.
Fig. 12A is a sectional view illustrating a configuration example of an imaging device according to an embodiment of the present invention, and is a modification example of the configuration shown in fig. 10A. The configuration of the imaging apparatus shown in fig. 12A is different from that shown in fig. 10A in that: the photoelectric conversion element 11 is provided so as to have a region overlapping with the transistor 12, the capacitor 14, the transistor 15, and the like. Here, a layer provided with the transistor 12, the capacitor 14, the transistor 15, and the like is the layer 131, and a layer provided with the photoelectric conversion element 11 is the layer 133.
Here, fig. 12A shows an example in which the components of the layer 131 and the components of the layer 133 are electrically connected by a bonding technique.
The layer 131 is provided with an insulating layer 123, and a conductive layer 115 and a conductive layer 117 are provided so as to have a region embedded in the insulating layer 123. The conductive layer 115 is electrically connected to one of the source and the drain of the transistor 12. Conductive layer 117 is electrically connected to conductive layer 107. In addition, the surfaces of the insulating layer 123, the conductive layer 115, and the conductive layer 117 are planarized so that the heights thereof are uniform.
The layer 133 is provided with an insulating layer 125, and a conductive layer 119 and a conductive layer 121 are provided so as to have a region embedded in the insulating layer 125. Insulating layer 125 has a region in contact with insulating layer 123, conductive layer 115 has a region in contact with conductive layer 119, and conductive layer 117 has a region in contact with conductive layer 121. Thus, one of a source and a drain of the transistor 12 is electrically connected to the layer 103a through the conductive layer 115 and the conductive layer 119, and the conductive layer 107 is electrically connected to the layer 103c through the conductive layer 117, the conductive layer 121, and the region 105. In addition, the surfaces of the insulating layer 125, the conductive layer 119, and the conductive layer 121 are planarized so that the heights thereof are uniform.
Here, the main components of the conductive layer 115 and the conductive layer 119 are preferably the same metal element. The conductive layer 117 and the conductive layer 121 preferably contain the same metal element as the main component. The insulating layer 123 and the insulating layer 125 are preferably formed of the same composition.
For example, Cu, Al, Sn, Zn, W, Ag, Pt, Au, or the like can be used for the conductive layer 115, the conductive layer 117, the conductive layer 119, and the conductive layer 121. From the viewpoint of ease of bonding, Cu, Al, W, or Au is preferably used. In addition, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the insulating layer 123 and the insulating layer 125.
In other words, it is preferable to use the same metal material as the above-described metal material for the combination of the conductive layer 115 and the conductive layer 119 and the combination of the conductive layer 117 and the conductive layer 121. Further, it is preferable to use the same insulating material as the insulating layer 123 and the insulating layer 125. By adopting the above configuration, bonding can be performed with the boundary between the layer 131 and the layer 133 as a bonding position.
By the bonding step, each electrical connection of the combination of the conductive layer 115 and the conductive layer 119 and the combination of the conductive layer 117 and the conductive layer 121 can be obtained. In addition, a mechanically strong connection of the insulating layer 123 and the insulating layer 125 can be obtained.
When bonding metal layers, a surface activation bonding method may be used in which an oxide film, an impurity-adsorbing layer, or the like on the surface is removed by sputtering or the like, and the cleaned and activated surface is brought into contact for bonding. Alternatively, a diffusion bonding method in which surfaces are bonded by using a combination of temperature and pressure may be used. The above-described methods can all be combined at the atomic level, and thus excellent electrical and mechanical bonding can be obtained.
In the case of bonding insulating layers, a hydrophilic bonding method or the like may be used, in which after high flatness is obtained by polishing or the like, surfaces hydrophilically treated with oxygen plasma or the like are brought into contact to temporarily bond, and dehydration is performed by heat treatment to thereby perform main bonding. Hydrophilic bonding also occurs at the atomic level, and therefore mechanically excellent bonding can be obtained.
In the case of the adhesive layer 131 and the layer 133, since the insulating layer and the metal layer are mixed at each bonding surface, for example, a surface activation bonding method and a hydrophilic bonding method may be combined.
For example, a method of cleaning the surface after polishing, performing an anti-oxygen treatment on the surface of the metal layer, and then performing a hydrophilic treatment to perform bonding may be employed. Further, a metal such as Au, which is difficult to oxidize, may be used as the surface of the metal layer, and hydrophilic treatment may be performed. In addition, bonding methods other than the above-described method may be used.
Light can be irradiated from the direction of the arrow to the image pickup device having the structure shown in fig. 12A. That is, the image pickup apparatus of the structure shown in fig. 12A may be a back-illuminated image pickup apparatus. This can prevent light incident on the imaging device from being blocked by wiring or the like provided in the imaging device. This can increase the light receiving area of the photoelectric conversion element 11, and can improve the light detection sensitivity of the pixels included in the imaging device according to one embodiment of the present invention. In addition, the S/N ratio can be improved. As described above, the imaging apparatus according to one embodiment of the present invention can obtain high-quality imaging data.
Fig. 12B is a sectional view illustrating a configuration example of an imaging device according to an embodiment of the present invention, and is a modification example of the configuration shown in fig. 12A. The structure of the image pickup apparatus shown in fig. 12B is different from that shown in fig. 12A in that: the photoelectric conversion element 11 has a stacked-layer structure of a layer 104a, a layer 104b, a layer 104c, and a layer 104 d. The layers 104a and 104d function as electrodes, and the layers 104b and 104c function as photoelectric conversion portions.
In the image pickup device of the structure shown in fig. 12B, the layer 133 may be formed directly on the layer 131. Layer 104a is electrically connected to one of the source and drain of transistor 12. Layer 104d is electrically connected to conductive layer 107 through conductive layer 127.
The layer 104a is preferably a metal layer with low resistance. For example, layers of aluminum, titanium, tungsten, tantalum, silver, or a stack thereof may be used.
A conductive layer having high transmittance for visible light is preferably used for the layer 104 d. For example, indium oxide, tin oxide, zinc oxide, indium tin oxide, gallium zinc oxide, indium gallium zinc oxide, graphene, or the like can be used as the layer 104 d. In addition, the layer 104d may be omitted.
The layers 104b and 104c of the photoelectric conversion section may have a pn junction photodiode structure in which a selenium-based material is used as a photoelectric conversion layer, for example. In the case of this structure, it is preferable to use a selenium-based material of a p-type semiconductor for the layer 104b and gallium oxide of an n-type semiconductor for the layer 104 c.
The photoelectric conversion element using the selenium-based material has high external quantum efficiency for visible light. The photoelectric conversion element can increase the amount of electron amplification with respect to the amount of incident light by utilizing avalanche multiplication. In addition, the selenium-based material has a high light absorption coefficient, so that there are production advantages such as that a photoelectric conversion layer can be manufactured in a thin film. The thin film of the selenium-based material can be formed by a vacuum deposition method, a sputtering method, or the like.
As the selenium-based material, crystalline selenium such as single crystal selenium and polycrystalline selenium can be used. In addition, amorphous selenium may be used. In addition, a copper indium diselenide Compound (CIS) may be used. In addition, a copper indium gallium selenide Compound (CIGS) or the like may be used.
The n-type semiconductor is preferably formed of a material having a wide band gap and having transparency to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or an oxide mixed with these can be used. In addition, these materials also function as a hole injection blocking layer, and can reduce dark current.
In addition, the photoelectric conversion element 11 may also include an organic photoconductive film. In this case, the layer 104b may have a structure in which a hole transport layer, a photoelectric conversion layer, and an electron transport layer are stacked. Here, as the hole transport layer, for example, molybdenum oxide or the like can be used. As the electron transport layer, for example, fullerene such as C60 or C70, or a derivative thereof can be used. Further, as the photoelectric conversion layer, a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used.
Fig. 13A is a sectional view illustrating a configuration example of an imaging device according to an embodiment of the present invention, and is a modification example of the configuration shown in fig. 11A. The structure of the imaging apparatus shown in fig. 13A is different from that shown in fig. 11A in that: the photoelectric conversion element 11 is provided so as to have a region overlapping with the transistor 12, the capacitor 14, the transistor 15, and the like. In other words, the structure differs from that shown in fig. 11A in that: a capacitor 14, a transistor 15, and the like, a transistor 12, and the like, and a photoelectric conversion element 11 are stacked. Here, a layer provided with the capacitor 14, the transistor 15, and the like is the layer 131, a layer provided with the transistor 12, and the like is the layer 132, and a layer provided with the photoelectric conversion element 11 is the layer 133.
Fig. 13A shows an example in which the components of the layer 132 and the components of the layer 133 are electrically connected by a bonding technique. In addition, similarly to the imaging device having the configuration shown in fig. 12A, light can be irradiated from the direction of the arrow to the imaging device having the configuration shown in fig. 13A. That is, a back-illuminated imaging device may be used.
Fig. 13B is a sectional view illustrating a configuration example of an imaging device according to an embodiment of the present invention, and is a modification example of the configuration shown in fig. 13A. The structure of the image pickup apparatus shown in fig. 13B is different from that shown in fig. 13A in that: similarly to fig. 12B, the photoelectric conversion element 11 has a stacked-layer structure of a layer 104a, a layer 104B, a layer 104c, and a layer 104 d.
In the image pickup device of the structure shown in fig. 13B, the layer 133 may be formed directly on the layer 132. In addition, similarly to the imaging device having the structure shown in fig. 12B, the layer 104a is electrically connected to one of the source and the drain of the transistor 12, and the layer 104d is electrically connected to the conductive layer 107 through the conductive layer 127.
Fig. 14A is a perspective view showing an example in which a color filter or the like is added to a pixel of an imaging device according to an embodiment of the present invention. The perspective view also shows a cross section of a plurality of pixels. An insulating layer 180 is formed on the photoelectric conversion element 11. As the insulating layer 180, a silicon oxide film having high transmittance to visible light or the like can be used. Further, a silicon azide film may be used as a passivation film layer. In addition, a dielectric film such as hafnium oxide may be laminated as an antireflection film.
A light-shielding layer 181 may be formed on the insulating layer 180. The light-shielding layer 181 has a function of preventing color mixing of light transmitted through the upper color filter. As the light-shielding layer 181, a metal layer of aluminum, tungsten, or the like can be used. In addition, the metal layer and a dielectric film having a function of an antireflection film may be laminated.
An organic resin layer 182 may be provided as a planarizing film on the insulating layer 180 and the light-shielding layer 181. In addition, a color filter 183 (color filter 183a, color filter 183b, color filter 183c) is formed in each pixel. For example, color filters 183a, 183B, and 183C have colors of R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta), and the like, whereby a color image can be obtained.
An insulating layer 186 or the like which transmits visible light may be provided over the color filter 183.
Further, as shown in fig. 14B, an optical conversion layer 185 may be used instead of the color filter 183. With this configuration, an imaging device capable of obtaining images in various wavelength regions can be realized.
For example, when a filter that blocks light of a wavelength of visible light or less is used as the optical conversion layer 185, an infrared imaging device can be obtained. When a filter that blocks light of a wavelength of near infrared rays or less is used as the optical conversion layer 185, a far infrared imaging device can be obtained. In addition, when a filter that blocks light of a wavelength of visible light or longer is used as the optical conversion layer 185, an ultraviolet imaging device can be obtained.
Further, by using a scintillator for the optical conversion layer 185, an imaging apparatus for obtaining an image that visualizes radiation intensity, such as an X-ray imaging apparatus, can be realized. When radiation such as X-rays transmitted through an object enters a scintillator, the radiation is converted into light (fluorescence) such as visible light or ultraviolet light by a photoluminescence phenomenon. Image data is obtained by detecting the light by the photoelectric conversion element 11. The imaging device having this configuration may be used for a radiation detector or the like.
The scintillator contains the following substances: when irradiated with radiation such as X-rays or gamma rays, the material absorbs energy of the radiation and emits visible light or ultraviolet light. For example, Gd may be used2O2S：Tb、Gd2O2S：Pr、Gd2O2S：Eu、BaFCl：Eu、NaI、CsI、CaF2、BaF2、CeF3LiF, LiI, ZnO, etc. dispersed in resin or ceramicA material.
In addition, in the photoelectric conversion element 11 using the selenium-based material, since radiation such as X-rays can be directly converted into electric charges, a scintillator does not need to be used.
As shown in fig. 14C, a microlens array 184 may be provided on the color filter 183. The light transmitted through each lens of the microlens array 184 is irradiated to the photoelectric conversion element 11 via the color filter 183 provided thereunder. Further, a microlens array 184 may be provided on the optical conversion layer 185 shown in fig. 14B.
An example of a package on which an image sensor chip is mounted and a camera module is described below. The image sensor chip may be configured as the image pickup device.
Fig. 15a1 is an external perspective view of the top surface side of the package on which the image sensor chip is mounted. The package includes a package substrate 410 for fixing the image sensor chip, a glass cover plate 420, an adhesive 430 for bonding the two, and the like.
Fig. 15a2 is an external perspective view of the bottom surface side of the package. The bottom surface of the package includes a Ball Grid Array (BGA) with solder balls as bumps 440. Note that the BGA is not limited to the BGA, but may include LGA (Land Grid Array), PGA (Pin Grid Array), or the like.
Fig. 15a3 is a perspective view of a package shown without a part of the glass cover 420 and a part of the adhesive 430. An electrode pad 460 is formed on the package substrate 410, and the electrode pad 460 is electrically connected to the bump 440 through the via 442. The electrode pad 460 is electrically connected to the image sensor chip 450 through a wire 470.
Fig. 15B1 is an external perspective view of the camera module in which the image sensor chip is housed on the top surface side of the lens-integrated package. The camera module includes a package substrate 411 for fixing an image sensor chip, a lens cover 421, a lens 435, and the like.
Fig. 15B2 is an external perspective view of the bottom surface side of the camera module. The package has a structure of QFN (Quad flat no-lead package) having receiving lands 441 on the bottom and side surfaces thereof. Note that this structure is an example, and QFP (Quad flat package) or the BGA described above may be provided.
Fig. 15B3 is a perspective view of the module shown with a part of the lens cover 421 and the lens 435 omitted. An IC chip 490 having functions such as a driving circuit and a signal conversion circuit of an imaging device is provided between the package substrate 411 and the image sensor chip 451, and has a configuration as an SiP (System in package). Although not shown in fig. 15B3, the land 441 is electrically connected to the electrode pad 461. In addition, the electrode pad 461 is electrically connected to the image sensor chip 451 or the IC chip 490 through a lead 471.
By housing the image sensor chip in the package of the above-described manner, the image sensor chip can be easily mounted on a printed circuit board or the like, and can be mounted on various semiconductor devices and electronic apparatuses.
This embodiment can be combined with the description of the other embodiments as appropriate.
(embodiment mode 3)
In this embodiment, a description will be given of a configuration of a CAC (Cloud-Aligned Composite) -OS that can be used for a transistor disclosed in one embodiment of the present invention.
CAC-OS is, for example, a structure in which elements contained in a metal oxide are unevenly distributed, and the size of a material containing unevenly distributed elements is 0.5nm or more and 10nm or less, preferably 1nm or more and 2nm or less or an approximate size. Note that, in the metal oxide, a state in which one or more metal elements are unevenly distributed and a region including the metal element is mixed in a size of 0.5nm or more and 10nm or less, preferably 1nm or more and 2nm or less, or approximately is also referred to as a mosaic (mosaic) shape or a patch (patch) shape hereinafter.
The metal oxide preferably contains at least indium. In particular, indium and zinc are preferably contained. In addition, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be contained.
For example, CAC In-Ga-Zn oxides-OS (In CAC-OS, In particular, In-Ga-Zn oxide may be referred to as CAC-IGZO) means that the material is divided into indium oxide (hereinafter, referred to as InO)X1(X1 is a real number greater than 0)) or indium zinc oxide (hereinafter, referred to as In)X2ZnY2OZ2(X2, Y2, and Z2 are real numbers larger than 0)), and gallium oxide (hereinafter referred to as GaO)X3(X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter referred to as GaX4ZnY4OZ4(X4, Y4, and Z4 are real numbers greater than 0)), and the like, and the mosaic-shaped InOX1Or InX2ZnY2OZ2A structure uniformly distributed in the film (hereinafter, also referred to as a cloud).
In other words, the CAC-OS is of GaOX3A region containing as a main component InX2ZnY2OZ2Or InOX1A composite metal oxide having a structure in which regions of the main component are mixed together. In this specification, for example, when the atomic number ratio of In to the element M In the first region is larger than the atomic number ratio of In to the element M In the second region, the In concentration In the first region is higher than that In the second region.
Note that IGZO is a generic term, and may be a compound containing In, Ga, Zn, and O. A typical example is InGaO3(ZnO)m1(m1 is a natural number) or In(1+x0)Ga(1-x0)O3(ZnO)m0A crystalline compound represented by (-1. ltoreq. x 0. ltoreq.1, m0 is an arbitrary number).
The crystalline compound has a single Crystal structure, a polycrystalline structure, or a CAAC (C-Axis Aligned Crystal) structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected in a non-oriented manner on the a-b plane.
On the other hand, CAC-OS is related to the material composition of the metal oxide. CAC-OS refers to the following composition: in the material composition containing In, Ga, Zn, and O, some of the nanoparticle-like regions containing Ga as a main component and some of the nanoparticle-like regions containing In as a main component were observed to be irregularly dispersed In a mosaic shape. Therefore, in CAC-OS, the crystal structure is a secondary factor.
The CAC-OS does not contain a laminate structure of two or more films different in composition. For example, a structure composed of two layers of a film containing In as a main component and a film containing Ga as a main component is not included.
Note that GaO is sometimes not observedX3A region containing as a main component InX2ZnY2OZ2Or InOX1Is a well-defined boundary between regions of major composition.
In the case where the CAC-OS contains one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like in place of gallium, the CAC-OS means a constitution as follows: some of the nano-particle-like regions containing the metal element as a main component and some of the nano-particle-like regions containing In as a main component were observed to be irregularly dispersed In a mosaic shape.
The CAC-OS can be formed by, for example, sputtering without intentionally heating the substrate. In the case of forming the CAC-OS by the sputtering method, as the film forming gas, one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used. The lower the flow ratio of the oxygen gas in the total flow of the film forming gas at the time of film formation, the better, for example, the flow ratio of the oxygen gas is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.
The CAC-OS has the following characteristics: no clear peak was observed when measured by the Out-of-plane method according to one of the X-ray diffraction (XRD: X-ray diffraction) measurements using a theta/2 theta scan. That is, it was found that the orientation in the a-b plane direction and the c-axis direction was not present in the measurement region by the X-ray diffraction measurement.
In the electron diffraction pattern of CAC-OS obtained by irradiating an electron beam (also referred to as a nanobeam) having a beam diameter of 1nm, an annular region having high brightness (annular region) and a plurality of bright spots in the annular region were observed. From this, it is known that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the plane direction and the cross-sectional direction, from the electron diffraction pattern.
In addition, for example, In the CAC-OS of In-Ga-Zn oxide, it was confirmed that, based on an EDX plane analysis image obtained by Energy Dispersive X-ray spectrometry (EDX: Energy Dispersive X-ray spectroscopy): with GaOX3A region containing as a main component and InX2ZnY2OZ2Or InOX1The main component region is unevenly distributed and mixed.
The CAC-OS has a structure different from that of an IGZO compound in which metal elements are uniformly distributed, and has properties different from those of the IGZO compound. In other words, CAC-OS has a GaOX3Etc. as main component and InX2ZnY2OZ2Or InOX1The regions having the main components are separated from each other, and the regions having the elements as the main components are formed in a mosaic shape.
In here, InX2ZnY2OZ2Or InOX1The conductivity of the region having the main component is higher than that of GaOX3Etc. as the main component. In other words, when carriers flow InX2ZnY2OZ2Or InOX1The region containing the main component exhibits conductivity of the metal oxide. Therefore, when In is usedX2ZnY2OZ2Or InOX1When the region as the main component is distributed in a cloud shape in the metal oxide, high field-effect mobility (μ) can be achieved.
On the other hand, with GaOX3The insulating property of the region containing the above-mentioned component is higher than that of InX2ZnY2OZ2Or InOX1Is the region of the main component. In other words, when GaO is usedX3When the region containing the metal oxide as a main component is distributed, leakage current can be suppressed and a good switching operation can be realized.
Therefore, when CAC-OS is used for the semiconductor element, the heat radiation is caused by GaOX3Insulation property of the like and the cause of InX2ZnY2OZ2Or InOX1Can realize high-current (I)on) And high field effect mobility (μ).
In addition, the semiconductor element using the CAC-OS has high reliability. Therefore, the CAC-OS is applied to various semiconductor devices such as displays.
This embodiment can be combined with the description of the other embodiments as appropriate.
(embodiment mode 4)
In this embodiment, an electronic apparatus to which an image pickup device according to an embodiment of the present invention can be applied will be described.
Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include a display device, a personal computer, an image storage device or an image reproduction device provided with a recording medium, a mobile phone, a portable game machine, a portable data terminal, an electronic book reader, an imaging device such as a video camera or a digital camera, a goggle type display (head mounted display), a navigation system, an audio reproduction device (a car audio system, a digital audio player, or the like), a copier, a facsimile machine, a printer, a multifunction printer, an Automated Teller Machine (ATM), an automatic vending machine, and the like. Fig. 16A to 16F show specific examples of these electronic devices.
Fig. 16A shows an example of a mobile phone 910, which includes a housing 911, a display portion 912, operation buttons 913, an external connection port 914, a speaker 915, a slot 916, a camera 917, a headphone jack 918, and the like. In the mobile phone 910, a touch sensor may be provided in the display portion 912. By touching the display portion 912 with a finger, a stylus, or the like, all operations such as making a call and inputting characters can be performed. In addition, a memory card such as an SD card, a USB memory, various removable storage devices such as an SSD (Solid State Drive), etc. may be inserted into the slot 916.
The imaging apparatus and the operation method thereof according to one embodiment of the present invention can be used as a component for acquiring imaging data using the mobile phone 910. Thus, the mobile phone 910 can acquire high-quality image data.
Fig. 16B shows an example of the portable data terminal 920, which includes a housing 921, a display portion 922, a speaker 923, a camera 924, and the like. Information can be input and output by the touch panel function of the display portion 922. In addition, characters and the like can be recognized from an image acquired by the camera 924, and the characters can be output in voice using the speaker 923.
The imaging apparatus and the method for operating the same according to one embodiment of the present invention can be used as a component for acquiring imaging data using the portable data terminal 920. Thereby, the portable data terminal 920 can acquire high-quality image data.
Fig. 16C shows an example of a wristwatch-type information terminal 930, which includes a housing/wrist band 931, a display portion 932, operation buttons 933, an external connection port 934, a camera 935, and the like. The display unit 932 is provided with a touch panel for operating the information terminal 930. The housing/wrist band 931 and the display portion 932 are flexible and are suitable for wearing on the body.
The imaging apparatus and the operation method thereof according to one embodiment of the present invention can be used as a component for acquiring imaging data using the information terminal 930. Thereby, the information terminal 930 can acquire high-quality image data.
Fig. 16D shows an example of the video camera 940, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, a speaker 947, a microphone 948, and the like. The operation keys 944 and the lens 945 can be provided on the first housing 941, and the display portion 943 can be provided in the second housing 942.
The imaging apparatus and the operation method thereof according to one embodiment of the present invention can be used as a component for acquiring imaging data using the video camera 940. Thereby, the video camera 940 can acquire high-quality image data.
Fig. 16E shows an example of a digital camera 950, which includes a housing 951, a shutter button 952, a light emitting portion 953, a lens 954, and the like. The imaging apparatus and the operation method thereof according to one embodiment of the present invention can be used as a component for acquiring imaging data using the digital camera 950. Thus, the digital camera 950 can acquire high-quality image data.
Fig. 16F shows an example of a monitoring camera 960, which includes a fixing member 961, a housing 962, a lens 963, and the like. The monitoring camera 960 may be mounted to a wall or ceiling or the like using a fixing member 961. Note that "monitoring camera" is a general name, and the name does not limit its use. For example, a device having a function of a monitoring camera is called a video camera or a video camera.
The imaging apparatus and the operation method thereof according to one embodiment of the present invention can be used as a component for acquiring imaging data using the monitoring camera 960. Thereby, the monitoring camera 960 can acquire high-quality image data.
This embodiment can be combined with the description of the other embodiments as appropriate.
[ description of symbols ]
10: pixel, 11: photoelectric conversion element, 12: transistor, 13: transistor, 14: capacitor, 15: transistor, 16: current source, 22: wiring, 23: wiring, 24: wiring, 25: wiring, 31: wiring, 33: wiring, 35: wiring, 36: wiring, 41: imaging unit, 42: gate drive circuit, 44: signal generation circuit, 45: CDS circuit, 46: data driving circuit, 47: a/D conversion circuit, 48: power supply circuit, 49: optical sensor, 50: detection circuit, 101: substrate, 103 a: layer, 103 b: layer, 103 c: layer, 104 a: layer, 104 b: layer, 104 c: layer, 104 d: layer, 105: region, 107: conductive layer, 109: insulating layer, 111: back gate electrode, 113: channel formation region, 115: conductive layer, 117: conductive layer, 119: conductive layer, 121: conductive layer, 123: insulating layer, 125: insulating layer, 127: conductive layer, 131: layer, 132: layer, 133: layer, 180: insulating layer, 181: light-shielding layer, 182: organic lipid layer, 183: color filter, 183 a: color filter, 183 b: color filter, 183 c: color filter, 184: microlens array, 185: optical conversion layer, 186: insulating layer, 201: gate electrode, 202: gate insulating film, 203: source region, 204: drain region, 205: source electrode, 206: drain electrode, 207: metal oxide layer, 207 a: metal oxide layer, 207 b: metal oxide layer, 207 c: metal oxide layer, 410: package substrate, 411: package substrate, 420: glass cover plate, 421: lens cover, 430: adhesive, 435: lens, 440: bump, 441: connection disc, 442: through hole, 450: image sensor chip, 451: image sensor chip, 460: electrode pad, 461: electrode pad, 470: lead wire, 471: lead wire, 490: IC chip, 910: mobile phone, 911: a housing, 912: display unit, 913: operation buttons, 914: external connection port, 915: a loudspeaker 916: slot, 917: camera, 918: headphone jack, 920: portable data terminal, 921: a shell, 922: display unit, 923: speakers, 924: camera, 930: information terminal, 931: case and wrist band, 932: display unit, 933: operation buttons, 934: external connection port, 935: camera, 940: video camera, 941: outer shell, 942: housing, 943: display unit, 944: operation keys, 945: lens, 946: connecting part, 947: speaker, 948: microphone, 950: digital camera, 951: a housing, 952: shutter button, 953: light-emitting section 954: lens, 960: monitoring camera, 961: fixing member, 962: housing, 963: lens barrel
Claims (9)
1. A method of operating an image capture device, the image capture device comprising pixels,
wherein the pixel includes a photoelectric conversion element, a first transistor, a second transistor, and a capacitor,
one electrode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor,
the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor,
a gate of the second transistor is electrically connected to one electrode of the capacitor,
the method for operating the imaging apparatus includes the steps of:
in a first period, a first potential is supplied to the other electrode of the capacitor and the first transistor is turned on, whereby image pickup data corresponding to illuminance of light irradiated to the photoelectric conversion element is written into the pixel; and
in a second period, a second potential is supplied to the other electrode of the capacitor, whereby the image pickup data is read out from the pixel.
2. The method according to claim 1,
wherein during the first period, the second transistor is in an off state,
and during the second period, the second transistor is in an on state.
3. The method according to claim 1 or 2,
wherein the second transistor is an n-channel type transistor,
and the second potential is higher than the first potential.
4. The method according to claim 1 or 2,
wherein the second transistor is a p-channel type transistor,
and the second potential is lower than the first potential.
5. A method of operating an image capture device, the image capture device comprising pixels,
wherein the pixel includes a photoelectric conversion element, a first transistor, a second transistor, a third transistor, and a capacitor,
one electrode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor,
the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor,
a gate of the second transistor is electrically connected to one of a source and a drain of the third transistor,
one of a source and a drain of the third transistor is electrically connected to one electrode of the capacitor,
the method for operating the imaging apparatus includes the steps of:
in a first period, the third transistor is turned on, and the potential of the gate of the second transistor is reset;
in a second period, a first potential is supplied to the other electrode of the capacitor, and the first transistor is turned on and the third transistor is turned off, whereby image pickup data corresponding to illuminance of light irradiated to the photoelectric conversion element is written in the pixel; and
in a third period, a second potential is supplied to the other electrode of the capacitor, whereby the image data is read out from the pixel.
6. The method according to claim 5,
wherein the second transistor is in an off state during the first and second periods,
and during the third period, the second transistor is in an on state.
7. The method according to claim 5 or 6,
wherein the second transistor is an n-channel type transistor,
and the second potential is higher than the first potential.
8. The method according to claim 5 or 6,
wherein the second transistor is a p-channel type transistor,
and the second potential is lower than the first potential.
9. The method of operating the image pickup apparatus according to any one of claims 1 to 8,
wherein the first transistor includes a metal oxide in a channel formation region,
and the metal oxide contains In, Zn and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf).
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018-146486 | 2018-08-03 | ||
| JP2018146486 | 2018-08-03 | ||
| PCT/IB2019/056306 WO2020026080A1 (en) | 2018-08-03 | 2019-07-24 | Operation method of image capturing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112534802A true CN112534802A (en) | 2021-03-19 |
Family
ID=69231084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201980051728.8A Pending CN112534802A (en) | 2018-08-03 | 2019-07-24 | Method for operating image pickup apparatus |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US11825220B2 (en) |
| JP (1) | JP7342002B2 (en) |
| KR (1) | KR20210029254A (en) |
| CN (1) | CN112534802A (en) |
| WO (1) | WO2020026080A1 (en) |
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| TWI442368B (en) * | 2006-10-26 | 2014-06-21 | Semiconductor Energy Lab | Electronic device, display device, and semiconductor device and method for driving the same |
| KR101775180B1 (en) * | 2010-02-12 | 2017-09-05 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for driving the same |
| KR102115344B1 (en) * | 2010-08-27 | 2020-05-26 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Memory device and semiconductor device |
| TWI696278B (en) | 2015-03-31 | 2020-06-11 | 日商新力股份有限公司 | Image sensor, camera device and electronic device |
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| JP6802653B2 (en) * | 2016-07-15 | 2020-12-16 | 株式会社ジャパンディスプレイ | Display device |
| WO2019009023A1 (en) * | 2017-07-05 | 2019-01-10 | パナソニックＩｐマネジメント株式会社 | Imaging device |
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2019
- 2019-07-24 KR KR1020217003993A patent/KR20210029254A/en unknown
- 2019-07-24 CN CN201980051728.8A patent/CN112534802A/en active Pending
- 2019-07-24 JP JP2020533886A patent/JP7342002B2/en active Active
- 2019-07-24 US US17/261,664 patent/US11825220B2/en active Active
- 2019-07-24 WO PCT/IB2019/056306 patent/WO2020026080A1/en active Application Filing
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| JP2011119711A (en) * | 2009-11-06 | 2011-06-16 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| JP2015186069A (en) * | 2014-03-25 | 2015-10-22 | キヤノン株式会社 | Photoelectric conversion device and driving method thereof |
| US20170013214A1 (en) * | 2015-07-07 | 2017-01-12 | Semiconductor Energy Laboratory Co., Ltd. | Imaging device and operating method thereof |
| US20170084649A1 (en) * | 2015-09-18 | 2017-03-23 | Semiconductor Energy Laboratory Co., Ltd. | Imaging device, module, electronic device, and method of operating the imaging device |
| CN108259790A (en) * | 2018-04-02 | 2018-07-06 | 昆山锐芯微电子有限公司 | Image sensor pixel circuit and its method of work |
Also Published As
| Publication number | Publication date |
|---|---|
| US20210281777A1 (en) | 2021-09-09 |
| WO2020026080A1 (en) | 2020-02-06 |
| JP7342002B2 (en) | 2023-09-11 |
| KR20210029254A (en) | 2021-03-15 |
| JPWO2020026080A1 (en) | 2021-09-16 |
| US11825220B2 (en) | 2023-11-21 |
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