CN112532241B - Synchronous signal generating circuit based on time competition - Google Patents
Synchronous signal generating circuit based on time competition Download PDFInfo
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- CN112532241B CN112532241B CN202011361485.9A CN202011361485A CN112532241B CN 112532241 B CN112532241 B CN 112532241B CN 202011361485 A CN202011361485 A CN 202011361485A CN 112532241 B CN112532241 B CN 112532241B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/1803—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the counter or frequency divider being connected to a cycle or pulse swallowing circuit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
Abstract
Hair brushThe invention discloses a synchronization signal generation circuit based on time competition, which comprises: a control chip, the rising edge interrupt input of which is used for realizing the capture of the rising edge of the Syn signal, the PWM output port of which outputs the PWM signal, and the I/O output port of which outputs a signal CTL Tri The three-state gate G1 is used for controlling the on-off of the three-state gate; a tri-state gate G1, the input end of which is connected with the PWM output port of the control chip 1, and the control end of which is connected with the output signal CTL of the control chip 1 Tri A connection, the output of which is connected to the synchronization signal Syn; the connecting terminal J is used for accessing/outputting a synchronous signal Syn; and one end of the resistor R is connected with the synchronous signal Syn, and the other end of the resistor R is connected with the ground, and the resistor R is used for ensuring the certainty of the level of the synchronous signal Syn. The invention has the characteristics of simple structure, low cost, high speed, strong anti-interference capability, high reliability and good practicability.
Description
Technical Field
The present invention relates to a system synchronization method, and more particularly, to a synchronization signal generation circuit based on time contention.
Background
In the fields of control such as machinery, electronics, electricity, power, computers, and chemical engineering, it is generally necessary to control a plurality of devices in synchronization. For example: in a solar power generation system, when inverters supply power in parallel, the phase of voltage needs to be synchronously output; when the UPS supplies power, the inverter supplies power in parallel and also needs to synchronize the phase of the output voltage; in the field of multi-axis numerical control machining, synchronous adjustment and control of controllers with multiple degrees of freedom are required. The synchronous control performance is directly related to the output performance of the system, and even the safe and reliable operation of the system. It can be seen that the synchronization signal is a precondition for realizing the synchronization control.
The existing synchronization signal is mainly realized by two schemes: 1. external synchronization signal scheme-the external device provides a reference signal as the synchronization signal. There is a major problem of poor reliability. Once the synchronous signal generator fails or is lost, the system cannot realize synchronous control, which causes the control disorder of the whole system and leads to system failure. 2. Synchronization scheme based on a communication bus-each device of the system sends an identification code with unique characteristics (e.g. the SN number of the chip) to the other devices and receives the identification codes of the other devices of the system via the communication bus. The master modules in the system are then determined by a specific algorithm (e.g., solving for the maximum or minimum value of the identification code values) based on the identification codes of all devices in the system. The main module takes the functions of coordinating and controlling the whole system, including synchronization, current sharing, state information uploading, command issuing and the like.
The existing synchronous signal generation method has poor reliability, or needs communication bus networking and complex algorithms, and has prominent defects in the aspects of cost, reliability, circuit scale, software program complexity and the like.
Disclosure of Invention
The invention aims to provide a synchronizing signal generating circuit based on time competition. The invention has the characteristics of simple structure, low cost, high speed, strong anti-interference capability, high reliability and good practicability.
The technical scheme of the invention is as follows: a synchronization signal generation circuit based on time contention, comprising: the control chip, the tri-state gate G1, the wiring terminal J and the resistor R;
a control chip, the rising edge interrupt input of which is used for realizing the capture of the rising edge of the Syn signal, the PWM output port of which outputs the PWM signal, and the I/O output port of which outputs a signal CTL Tri The three-state gate is used for controlling the on-off of the three-state gate G1;
a tri-state gate G1, the input end of which is connected with the PWM output port of the control chip 1, and the control end of which is connected with the output signal CTL of the control chip 1 Tri A connection, the output of which is connected to the synchronization signal Syn;
the wiring terminal J is used for accessing/outputting a synchronous signal Syn;
and one end of the resistor R is connected with the synchronous signal Syn, and the other end of the resistor R is connected with the ground, and the resistor R is used for ensuring the certainty of the level of the synchronous signal Syn.
In the above-described synchronization signal generation circuit based on time competition, the generation method of the synchronization signal circuit based on time competition is performed by the following steps:
(1) the initialization program is used for initializing the output of the PWM module and the setting of interruption, the setting of a Syn loss timer, the setting of rising edge interruption and the setting of I/O output;
(2) PWM overflow interrupt processing program for realizing power-on delay and I/O output signal CTL Tri Control of (2);
(3) a rising edge interrupt processing program realizes the identification of the rising edge of the Syn signal and the zero clearing control of the Syn loss timer;
(4) and the yn loss timer overflows an interrupt processing program to realize the resetting of related parameters so as to restart the competition of the Syn.
Compared with the prior art, the method has the following advantages:
according to the invention, a non-master-slave dynamic synchronization scheme based on time competition is adopted, and compared with a static master-slave synchronization scheme, even if a circuit for providing a synchronization signal Syn is pulled out or a signal is lost due to failure, a new synchronization signal can be regenerated from the rest PWM signals through time competition within set time, so that the reliability is higher;
because the PWM overflow interruption signal occurrence time of each circuit is different, the PWM signal which is correspondingly output by the circuit with the earliest PWM overflow interruption signal occurrence is selected as Syn based on the difference, and therefore, the synchronous signal Syn is unique.
The invention supports the circuit to carry out hot plug, can effectively inhibit Syn signals from being lost in short time due to poor contact, element failure or interference and the like, and has strong anti-interference capability and stable reliability.
Compared with a synchronization scheme via a communication bus, the invention has the following advantages: firstly, the invention does not need data exchange; secondly, the frequency of the synchronization signal is completely determined by the frequency of the PWM signal, and the bandwidth of the synchronization signal frequency is large. The communication bus synchronization scheme is limited by communication baud rate and various checks, so that the bandwidth of the synchronization signal frequency is limited; again, the respective circuits can almost simultaneously acquire the synchronization signal Syn. Since the synchronization signal Syn appears at the connection terminals J of the respective circuits at the same time, all the modules can receive the synchronization signal Syn at the same time, and there is theoretically no time difference. However, in the communication bus synchronization scheme, from the sending of the synchronization signal to the receiving of the synchronization signal, due to the processes of data transmission, receiving, verification, program processing and the like, a certain difference exists in the time for each module to acquire the synchronization signal; then, the synchronization signal generation circuit and the method provided by the invention do not need a communication protocol, do not influence the operation of the internal software of the module, and can synchronize the modules of different models and different manufacturers, thereby having wide compatibility; finally, the electronic elements required by the synchronization signal generation circuit and method provided by the invention are common elements and modules, and the synchronization signal generation circuit and method have the advantages of convenience in implementation, low cost, high cost performance, stability, reliability and the like.
Drawings
FIG. 1 is a diagram of the production circuit of the present invention;
FIG. 2 is a schematic diagram of the production circuit of the present invention;
FIG. 3 is a schematic diagram of a system connection incorporating a synchronization signal generation circuit;
FIG. 4a is an initialization flow diagram;
FIG. 4b is a flowchart of a PWM overflow interrupt handler;
FIG. 4c is a flow diagram of a rising edge interrupt handler;
FIG. 4d is a flowchart of the Syn lost timer overflow interrupt handler.
Detailed Description
The invention is further illustrated by the following figures and examples, which are not to be construed as limiting the invention.
Examples are given. A synchronization signal generation circuit based on time competition is configured as shown in FIG. 1, and comprises: the circuit comprises a control chip 1, a tri-state gate G1, a wiring terminal J and a resistor R;
the control chip has rising edge interrupt input for capturing the rising edge of Syn signal, PWM output port for outputting PWM signal, and I/O output port for outputting signal CTL Tri The three-state gate is used for controlling the on-off of the three-state gate G1;
a tri-state gate G1, the input end of which is connected with the PWM output port of the control chip 1, and the control end of which is connected with the output signal CTL of the control chip 1 Tri A connection, the output of which is connected to the synchronization signal Syn;
the connecting terminal J is used for accessing/outputting a synchronous signal Syn;
and one end of the resistor R is connected with the synchronous signal Syn, and the other end of the resistor R is connected with the ground, and the resistor R is used for ensuring the certainty of the level of the synchronous signal Syn.
Fig. 2 is a schematic diagram of a synchronization signal generation, which mainly includes a power-on delay, a PWM module, a tri-state gate, a PWM output control module, a synchronization signal Syn loss timing/counting module, and a connection terminal. Wherein, the power-on time delay realizing circuit delays T after power-on d ，T d It must satisfy: t is d >T s . Wherein, T s Is the period of the PWM signal. To facilitate the implementation of the procedure, let T d ＝KT s (K is a positive integer greater than 1). The PWM module outputs a PWM signal and an overflow signal OV, the PWM signal is connected to the input of the three-state gate, and the overflow signal OV is input to the PWM output control module. The three-state gate receives an output signal CTL of the PWM output control module, controls the connection or disconnection of the PWM signal and the terminal, and plays a role of a bus control switch. The Syn loss timing/counting module judges whether the Syn continuous loss time (or number) reaches a set trigger value or not. And if the preset trigger value is reached, outputting a Reset signal to the PWM output control module. The PWM output control module receives the output OV of the PWM module, the Reset of the Syn lost timing/counting module and the synchronous signal Syn, obtains an output control signal CTL based on a time competition relationship, realizes on-off control of the tri-state gate, and further determines the synchronous signal Syn.
Fig. 3 is a schematic diagram of a system connection integrated with a synchronization signal generation circuit based on time competition according to the present invention, which connects the terminals of the synchronization signal generation circuits of all modules together through a wire, where the signal on the wire is a synchronization signal Syn.
Fig. 4 is a flowchart of a method for generating a synchronization signal based on the circuit of fig. 1 and the principle of fig. 2, which includes the following steps:
the method comprises the steps of initializing PWM module output and interrupt setting, syn loss timer setting, rising edge interrupt setting, I/O output setting and the like;
and secondly, PWM overflow interrupt processing program is used for realizing power-on delay and I/O output signal CTL Tri Control of (2);
interrupting the program by the rising edge to realize the identification of the rising edge of the Syn signal and the zero clearing control of the Syn loss timer;
and fourthly, the Syn loss timer overflows an interrupt handler to reset relevant parameters so as to restart the competition of the Syn.
In conclusion, the synchronization signal generation circuit based on time competition provided by the invention not only has strong anti-interference capability and reliability and supports the system to carry out hot plug, but also can realize the generation of system synchronization signals by only needing few common elements and wire connection, and has the characteristics of simple structure, low cost, high speed, strong anti-interference capability, high reliability, good practicability and the like.
Claims (2)
1. A synchronization signal generation circuit based on time contention, comprising: the control chip, the tri-state gate G1, the wiring terminal J and the resistor R;
a control chip, the rising edge interrupt input of which is used for realizing the capture of the rising edge of the Syn signal, the PWM output port of which outputs the PWM signal, and the I/O output port of which outputs a signal CTL Tri The three-state gate is used for controlling the on-off of the three-state gate G1;
a tri-state gate G1 with its input end connected with the PWM output port of the control chip 1 and its control end connected with the output signal CTL of the control chip 1 Tri A connection, the output of which is connected to the synchronization signal Syn;
the connecting terminal J is used for accessing/outputting a synchronous signal Syn;
a resistor R, one end of which is connected with the synchronous signal Syn and the other end of which is connected with the ground, for ensuring the certainty of the level of the synchronous signal Syn;
the control chip is provided with a PWM module, the output end of an overflow signal OV of the PWM module is connected with a PWM output control module, the PWM output control module is connected with a Syn loss timing/counting module, and the tri-state gate G1 receives an output signal CTL of the PWM output control module, controls the connection or disconnection of a PWM signal and a terminal and plays a role of a bus control switch; the Syn loss timing/counting module judges whether the time or the number of the Syn lost continuous time reaches a set trigger value or not; if the preset trigger value is reached, outputting a Reset signal to a PWM output control module; the PWM output control module receives the output OV of the PWM module, the output Reset signal of the Syn lost timing/counting module and the synchronous signal Syn, obtains an output control signal CTL based on the time competition relationship, realizes on-off control of the tri-state gate, and further determines the synchronous signal Syn.
2. The time-competition based synchronization signal generation circuit according to claim 1, wherein the generation method of the time-competition based synchronization signal circuit is performed by:
(1) the initialization program is used for initializing the output of the PWM module and the setting of interruption, the setting of a Syn loss timer, the setting of rising edge interruption and the setting of I/O output;
(2) PWM overflow interrupt processing program for realizing power-on delay and I/O output signal CTL Tri Control of (2);
(3) a rising edge interrupt processing program realizes the identification of the rising edge of the Syn signal and the zero clearing control of the Syn loss timer;
(4) the Syn loss timer overflows the interrupt handler to reset the relevant parameters so as to restart the competition of the Syn.
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| CN202011361485.9A CN112532241B (en) | 2020-11-27 | 2020-11-27 | Synchronous signal generating circuit based on time competition |
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| CN202011361485.9A CN112532241B (en) | 2020-11-27 | 2020-11-27 | Synchronous signal generating circuit based on time competition |
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| CN112532241B true CN112532241B (en) | 2023-03-24 |
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Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2607955B1 (en) * | 1986-12-05 | 1989-02-10 | Eurotechnique Sa | DEVICE FOR AUTOSYNCHRONIZING THE OUTPUT CIRCUITS OF A MEMORY |
| US6320434B1 (en) * | 1999-06-22 | 2001-11-20 | Texas Instruments Incorporated | Circuit and method for generating a synchronous clock signal |
| JP2004096815A (en) * | 2002-08-29 | 2004-03-25 | Fuji Electric Holdings Co Ltd | Method of synchronizing carriers in pwm control action, and pwm controller |
| US7584009B2 (en) * | 2003-03-21 | 2009-09-01 | D2Audio Corporation | Multi-chip PWM synchronization and communication |
| JP2008219235A (en) * | 2007-03-01 | 2008-09-18 | Yaskawa Electric Corp | System synchronizing method, pwm signal generating device for performing the same, and motor control system provided with the same |
| JP2009153311A (en) * | 2007-12-21 | 2009-07-09 | Nippon Reliance Kk | Synchronous control system, controller, and synchronous control method |
| WO2009148789A1 (en) * | 2008-06-02 | 2009-12-10 | Richard Landry Gray | Line syncronized electrical device and controlling method thereof |
| GB2470591A (en) * | 2009-05-29 | 2010-12-01 | Powervation Ltd | Pulse width modulation synchronisation of switched mode power converters |
| TWI394026B (en) * | 2010-01-07 | 2013-04-21 | Richtek Technology Corp | Clock generator and interleaved phase clock synchronization apparauts and method using the clock generator |
| CN107147380B (en) * | 2017-05-04 | 2020-08-07 | 深圳芯智汇科技有限公司 | Synchronous control circuit and multi-chip cascade circuit comprising same |
| CN107425828B (en) * | 2017-06-15 | 2023-05-05 | 温州大学 | Synchronous control signal generating circuit |
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