CN112532191B - Power detection circuit and method of power amplifier - Google Patents

Power detection circuit and method of power amplifier Download PDF

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CN112532191B
CN112532191B CN202110183211.3A CN202110183211A CN112532191B CN 112532191 B CN112532191 B CN 112532191B CN 202110183211 A CN202110183211 A CN 202110183211A CN 112532191 B CN112532191 B CN 112532191B
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current mirror
mirror
nmos
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CN112532191A (en
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彭振飞
苏强
刘传兵
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Guangzhou Huizhi Microelectronics Co.,Ltd.
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Smarter Microelectronics Guangzhou Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R21/00—Arrangements for measuring electric power or power factor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements

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Abstract

The embodiment of the application discloses a power detection circuit and a method of a power amplifier, wherein the power detection circuit comprises: the circuit comprises a bias circuit, a rectifying circuit, a direct current offset circuit, an offset compensation circuit and a gain control circuit; the bias circuit is connected with the rectification circuit and the direct current offset circuit respectively, the direct current offset circuit is connected with the offset compensation circuit and the rectification circuit respectively, and the gain control circuit is connected with the rectification circuit and the power amplifier respectively.

Description

Power detection circuit and method of power amplifier
Technical Field
The embodiment of the application relates to the technical field of power amplifier detection, in particular to a power detection circuit and a power detection method for a power amplifier.
Background
Modern communication systems adopt increasingly complex modulation schemes, so that the requirement on the linearity performance of a radio frequency power amplifier (RF PA) is increasingly high, and the problem to be solved is urgent in order to ensure the efficiency of the PA and simultaneously improve the linearity performance of the PA.
The existing power detection circuit for realizing linear bias applied to a wireless communication system generally comprises a bias circuit, a gain control circuit and a rectification circuit, as shown in fig. 1, when a radio frequency signal is input, the radio frequency signal is converted into direct current through the rectification circuit, the current output by the rectification circuit comprises quiescent current and direct current, namely, the detection current amplified and output by the gain control circuit at least comprises the quiescent current, therefore, the range of current compensation of the power amplifier by using the detection current is limited, and because the compensation requirements of different amplifiers can change according to the input power, the compensation function of the traditional power detection circuit to different amplifiers is single, and the flexibility is low.
Disclosure of Invention
The embodiment of the application provides a power detection circuit and a method of a power amplifier, wherein a direct current offset circuit and an offset compensation circuit are added on the basis of the existing power detection circuit, so that the range adjustment of output current can be realized, the compensation requirements on different amplifiers can be met, and the flexibility is higher.
The technical scheme of the embodiment of the application is realized as follows:
the embodiment of the application provides a power detection circuit of a power amplifier, the power detection circuit includes: the circuit comprises a bias circuit, a rectifying circuit, a direct current offset circuit, an offset compensation circuit and a gain control circuit;
the bias circuit is connected with the rectifying circuit and the direct current offset circuit respectively, and is used for providing bias voltage for the rectifying circuit and the direct current offset circuit respectively;
the rectifier circuit is used for converting an input radio frequency signal into direct current and superposing the direct current and the static current to obtain a first current;
the direct current offset circuit is respectively connected with the offset compensation circuit and the rectification circuit; the direct current offset circuit is configured to provide an offset current to offset the quiescent current in the first current, and the offset compensation circuit is configured to provide an offset compensation current to offset compensate the first current;
the gain control circuit is connected with the rectifying circuit and the power amplifier respectively, and is used for amplifying a second current obtained by offsetting the first current by the offset current and offset compensating the offset compensating current to obtain a detection current, and inputting the detection current into the power amplifier so as to perform current compensation on the power amplifier.
In the above power detection circuit, the bias circuit includes a first mirror constant current source and a first NMOS current mirror;
the first mirror image constant current source is composed of a first input stage and a first output stage, the first input stage comprises a reference current source and a first PMOS current mirror, and the first output stage comprises a second PMOS current mirror;
the source electrode of the first PMOS current mirror and the source electrode of the second PMOS current mirror are connected with a power supply;
the drain electrode of the first PMOS current mirror is connected with a reference current source and is connected with the gate electrode of the first PMOS current mirror;
the grid electrode of the second PMOS current mirror is connected with the grid electrode of the first PMOS current mirror, and the drain electrode of the second PMOS current mirror is connected with the drain electrode of the first NMOS current mirror;
the grid electrode of the first NMOS current mirror is respectively connected with the drain electrode of the first NMOS current mirror, the direct current offset circuit and the rectifying circuit, and the source electrode of the first NMOS current mirror is grounded;
the current transfer ratio of the first input stage and the first output stage is equal to the ratio of the width-to-length ratio of the first PMOS current mirror to the width-to-length ratio of the second PMOS current mirror.
In the above power detection circuit, the gain control circuit includes a second mirror constant current source;
the second mirror image constant current source is composed of a second input stage and a second output stage, the second input stage comprises a third PMOS current mirror, and the second output stage comprises a fourth PMOS current mirror;
the source electrode of the third PMOS current mirror and the source electrode of the fourth PMOS current mirror are connected with a power supply;
the drain electrode of the third PMOS current mirror is respectively connected with the grid electrode of the third PMOS current mirror, the rectifying circuit and the direct current offset circuit;
the grid electrode of the fourth PMOS current mirror is connected with the grid electrode of the third PMOS current mirror, and the drain electrode of the fourth PMOS current mirror is connected with the power amplifier;
the current transmission ratio of the second input stage and the second output stage is equal to the ratio of the width-to-length ratio of the third PMOS current mirror to the width-to-length ratio of the fourth PMOS current mirror.
In the above power detection circuit, the rectification circuit includes a fixed resistor, a capacitor, and a second NMOS current mirror;
one end of the capacitor is connected with the radio frequency signal, and the other end of the capacitor is connected with the grid electrode of the second NMOS current mirror;
one end of the fixed resistor is connected with the grid electrode of the second NMOS current mirror, and the other end of the fixed resistor is connected with the bias circuit;
and the drain electrode of the second NMOS current mirror is respectively connected with the direct current offset circuit and the gain control circuit, and the source electrode of the second NMOS current mirror is grounded.
In the above power detection circuit, the dc offset circuit includes a third mirror constant current source and a third NMOS current mirror;
the third mirror constant current source is composed of a third input stage and a third output stage, the third input stage comprises a fifth PMOS current mirror, and the third output stage comprises a sixth PMOS current mirror;
the source electrode of the fifth PMOS current mirror and the source electrode of the sixth PMOS current mirror are connected with a power supply;
the grid electrode of the fifth PMOS current mirror is connected with the drain electrode of the fifth PMOS current mirror and the grid electrode of the sixth PMOS current mirror respectively;
the drain electrode of the fifth PMOS current mirror is respectively connected with the drain electrode of the third NMOS current mirror and the offset compensation circuit;
the drain electrode of the sixth PMOS current mirror is respectively connected with the rectifying circuit and the gain control circuit;
the grid electrode of the third NMOS current mirror is connected with the bias circuit, and the source electrode of the third NMOS current mirror is grounded;
the current transfer ratio of the third input stage and the third output stage is equal to the ratio of the width-to-length ratio of the fifth PMOS current mirror to the width-to-length ratio of the sixth PMOS current mirror.
In the above power detection circuit, the offset compensation circuit includes a seventh PMOS current mirror, a variable resistor, a fourth NMOS current mirror, and a fifth NMOS current mirror;
the seventh PMOS current mirror is used as a fourth output stage and forms a fourth mirror constant current source with the first output stage formed by the reference current source and the first PMOS current mirror in the bias circuit;
the grid electrode of the seventh PMOS current mirror is connected with the grid electrode of the first PMOS current mirror;
in the seventh PMOS current mirror, a drain electrode is respectively connected with the variable resistor and a grid electrode of the fifth NMOS current mirror, and a source electrode is connected with a power supply;
the variable resistor is connected with the drain electrode of the fourth NMOS current mirror;
the drain electrode of the fourth NMOS current mirror is connected with the grid electrode of the fourth NMOS current mirror, and the drain electrode of the fifth NMOS current mirror is connected with the direct current offset circuit;
the source electrode of the fourth NMOS current mirror and the source electrode of the fifth NMOS current mirror are respectively grounded;
the current transfer ratio of the first input stage and the fourth output stage is equal to the ratio of the width-to-length ratio of the first PMOS current mirror to the width-to-length ratio of the seventh PMOS current mirror.
In the above power detection circuit, the variable resistor includes: the circuit comprises a first switch, a second switch, a third switch, a first resistor, a second resistor, a third resistor and a basic resistor;
the first switch is connected with the first resistor in parallel to form a first parallel circuit;
the second switch is connected with the second resistor in parallel to form a second parallel circuit;
the third switch is connected with the third resistor in parallel to form a third parallel circuit;
the first parallel circuit, the second parallel circuit, the third parallel circuit and one end of the basic resistor are connected in series, and the other end of the basic resistor is connected with the drain electrode of the fourth NMOS current mirror;
the first switch, the second switch and the third switch are used for controlling a resistor connected with the base resistor in series.
In the power detection circuit, a first NMOS current mirror in the bias circuit and a second NMOS current mirror of the rectification circuit form a fifth mirror constant current source;
the fifth mirror constant current source is composed of a fifth input stage and a fifth output stage, the fifth input stage comprises the first NMOS current mirror, and the fifth output stage comprises the second NMOS current mirror;
the current transfer ratio of the fifth input stage and the fifth output stage is equal to the ratio of the width-to-length ratio of the first NMOS current mirror to the width-to-length ratio of the second NMOS current mirror.
In the power detection circuit, a first NMOS current mirror in the bias circuit and a third NMOS current mirror of the dc offset circuit form a sixth mirror constant current source;
the sixth mirror constant current source is composed of a fifth input stage and a sixth output stage, the fifth input stage comprises the first NMOS current mirror, and the sixth output stage comprises the third NMOS current mirror;
the current transfer ratio of the fifth input stage and the sixth output stage is equal to the ratio of the width-to-length ratio of the first NMOS current mirror to the width-to-length ratio of the third NMOS current mirror.
The embodiment of the application also provides a power detection method of a power amplifier, which is applied to a power detection circuit, wherein the power detection circuit comprises a bias circuit, a rectification circuit, a direct current offset circuit, an offset compensation circuit and a gain control circuit, and the method comprises the following steps:
receiving a bias voltage provided by the bias circuit through the rectifying circuit to generate a static current;
converting an input radio frequency signal into direct current through the rectifying circuit, and superposing the direct current and the static current to obtain first current;
providing a cancellation current to cancel the quiescent current in the first current through the direct current cancellation circuit, and providing an offset compensation current to offset compensate the first current through the offset compensation circuit;
and amplifying the first current and a second current obtained by offsetting the offset current and offset compensating the offset compensation current through a gain control circuit to obtain a detection current, and inputting the detection current into a power amplifier to perform current compensation on the power amplifier.
The embodiment of the application provides a power detection circuit and a method of a power amplifier, wherein the power detection circuit comprises: the circuit comprises a bias circuit, a rectifying circuit, a direct current offset circuit, an offset compensation circuit and a gain control circuit; the bias circuit is connected with the rectifying circuit and the direct current offset circuit respectively and is used for providing bias voltage for the rectifying circuit and the direct current offset circuit respectively; the rectifier circuit is used for converting an input radio frequency signal into direct current and superposing the direct current and the static current to obtain first current; the direct current offset circuit is respectively connected with the offset compensation circuit and the rectification circuit; the offset compensation circuit is used for providing an offset compensation current to offset the first current; the gain control circuit is connected with the rectifying circuit and the power amplifier respectively, and is used for amplifying the first current and the second current obtained by offsetting current offset and offset compensation current offset compensation to obtain a detection current, and inputting the detection current into the power amplifier so as to perform current compensation on the power amplifier. The embodiment of the application provides a power detection circuit of power amplifier, has added direct current offset circuit and skew compensation circuit on current power detection circuit's basis, not only can realize output current's range regulation to can satisfy the compensation demand to different amplifiers, the flexibility is higher.
Drawings
Fig. 1 is a schematic structural diagram of a power detection circuit of a power amplifier provided in the prior art;
FIG. 2 is a graph illustrating a variation trend of a detection current with a power of a radio frequency signal according to the prior art;
fig. 3 is a schematic structural diagram of a power detection circuit of a power amplifier according to an embodiment of the present disclosure;
fig. 4 is a variation trend graph of an initial dc component of a detection current according to an embodiment of the present disclosure;
fig. 5 is a graph illustrating a variation trend of a turning point of a detection current according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a variable resistor according to an embodiment of the present disclosure;
fig. 7 is a flowchart illustrating a power detection method of a power amplifier according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant application and are not limiting of the application. It should be noted that, for the convenience of description, only the parts related to the related applications are shown in the drawings.
In the conventional power detection circuit, the power detection circuit generally includes a bias circuit 1, a gain control circuit 2, and a rectifier circuit 3, as shown in fig. 1, the bias circuit 1 is connected to the rectifier circuit 3, the bias circuit 1 provides a bias voltage to the rectifier circuit 3, the rectifier circuit 3 is connected to the gain control circuit 2, and the gain control circuit 2 is configured to amplify a first current output from the rectifier circuit 3 to obtain a detection current. The bias circuit 1 provides a bias voltage for the second NMOS current mirror 32 in the rectifying circuit 3, so that the second NMOS current mirror 32 operates in a saturation region.
It should be noted that, in the conventional power detection circuit, when no rf signal is input, the rectifier circuit 3 only receives the bias voltage provided by the bias circuit 1 to generate a static current, and at this time, the first current output by the rectifier circuit
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Only including quiescent current, the expression is:
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wherein the content of the first and second substances,
Figure 901967DEST_PATH_IMAGE003
，
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in order to achieve the mobility of the carriers,
Figure 986915DEST_PATH_IMAGE005
is the capacitance per unit area of the oxide layer,
Figure 543798DEST_PATH_IMAGE006
the gate width of the second NMOS current mirror 32,
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the gate length of the second NMOS current mirror 32,
Figure 616589DEST_PATH_IMAGE008
the gate and source voltages of the second NMOS current mirror 32,
Figure 19889DEST_PATH_IMAGE009
is the threshold voltage of the second NMOS current mirror 32.
When a radio frequency signal is input, the rectifying circuit 3 not only generates a static current, but also includes a direct current converted from the input radio frequency signal, and at this time, a first current output by the rectifying circuit
Figure 950935DEST_PATH_IMAGE001
Comprises the following steps:
Figure 377369DEST_PATH_IMAGE011
wherein the content of the first and second substances,
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the input radio frequency signal can be any radio frequency signal, and the input radio frequency signal is set as
Figure 309870DEST_PATH_IMAGE013
。
Then, after being converted into a direct current by the rectifying circuit 3, the first current outputted by the rectifying circuit 3
Figure 677397DEST_PATH_IMAGE014
Comprises the following steps:
Figure 591127DEST_PATH_IMAGE016
the first current is amplified by the gain amplifier circuit
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Amplifying to obtain output detection current
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Since the amplification factor of the gain amplifier circuit is 1:1 (as shown in fig. 1), the output detection current is obtained
Figure 977044DEST_PATH_IMAGE017
Comprises the following steps:
Figure 378069DEST_PATH_IMAGE018
as can be seen from equation (4), the detection current output from the gain control circuit 2
Figure 191304DEST_PATH_IMAGE017
In (1),
Figure 361386DEST_PATH_IMAGE019
in the form of a quiescent current, the voltage,
Figure 867453DEST_PATH_IMAGE020
the direct current converted for the input RF signal, which varies with the variation of the input RF signal, can be used for detecting the RF signalMagnitude, however, due to the detected current
Figure 490196DEST_PATH_IMAGE017
With a quiescent current, so that the current is detected
Figure 107122DEST_PATH_IMAGE017
The starting point of the power variation trend chart with the input radio frequency signal is always higher than 0, as shown in fig. 2, the abscissa is the power of the input radio frequency signal
Figure 397289DEST_PATH_IMAGE021
With ordinate representing the output detected current
Figure 9011DEST_PATH_IMAGE017
。
Therefore, the range of current compensation for the power amplifier by using the output detection current is limited, and the compensation requirements of different amplifiers can be changed according to the input power, so that the traditional power detection circuit has a single compensation function for different amplifiers and low flexibility.
The embodiment of the application provides a power detection circuit of a power amplifier, and compared with the existing power detection circuit, a direct current offset circuit 4 and an offset compensation circuit 5 are added. Fig. 3 is a schematic structural diagram of a power detection circuit of a power amplifier according to an embodiment of the present disclosure. The following provides a detailed description of the power detection circuit according to the present application based on the power detection circuit shown in fig. 3.
As shown in fig. 3, the power detection circuit includes: the circuit comprises a bias circuit 1, a rectifying circuit 3, a direct current offset circuit 4, an offset compensation circuit 5 and a gain control circuit 2;
the bias circuit 1 is connected with the rectifying circuit 3 and the direct current offset circuit 4 respectively, and the bias circuit 1 is used for providing bias voltage for the rectifying circuit 3 and the direct current offset circuit 4 respectively;
the rectifying circuit 3 is used for converting an input radio frequency signal into direct current and superposing the direct current and the static current to obtain a first current;
the direct current offset circuit 4 is respectively connected with the offset compensation circuit 5 and the rectification circuit 3; the direct current offset circuit 4 is used for providing offset current to offset static current in the first current, and the offset compensation circuit 5 is used for providing offset compensation current to offset and compensate the first current;
the gain control circuit 2 is connected with the rectifying circuit 3 and the power amplifier 6 respectively, and the gain control circuit 2 is used for amplifying a first current and a second current obtained by offsetting current and offsetting offset compensation current offset compensation to obtain a detection current, and inputting the detection current into the power amplifier 6 to perform current compensation on the power amplifier 6.
It should be noted that, in the power detection circuit provided in the embodiment of the present application, compared with the conventional power detection circuit, the dc offset circuit 4 and the offset compensation circuit 5 are added, and the offset current in the dc offset circuit 4 is added
Figure 384629DEST_PATH_IMAGE022
Which may be used to cancel the quiescent current in the first current, and an offset compensation circuit 5 for providing an offset compensation current to offset compensate the first current.
It should be noted that, in the embodiment of the present application, the cancellation current in the dc cancellation circuit 4 can be determined by adjusting the size of the third NMOS current mirror 40 in the dc cancellation circuit 4
Figure 539667DEST_PATH_IMAGE022
The magnitude of the static current in the cancelled first current is further determined, the gain control circuit 2 is used for amplifying the cancelled first current to obtain a starting point of the detection current, and therefore the range adjustment of the output detection current is achieved.
It should be noted that, in the embodiment of the present application, the offset compensation circuit 5 can perform offset compensation on the first current, and then amplify the offset compensated first current through the gain control circuit 2, so that the turning point of the obtained detection current changes with the magnitude of the offset compensation current, which can meet the compensation requirements of different amplifiers, and has higher flexibility.
Specifically, in the embodiment of the present application, the bias circuit 1 includes a first mirror constant current source and a first NMOS current mirror 13;
the first mirror image constant current source is composed of a first input stage and a first output stage, the first input stage comprises a reference current source 10 and a first PMOS current mirror 11, and the first output stage comprises a second PMOS current mirror 12;
the source electrode of the first PMOS current mirror 11 and the source electrode of the second PMOS current mirror 12 are connected with a power supply; the drain of the first PMOS current mirror 11 is connected to a reference current source and is connected to the gate of the first PMOS current mirror 11; the gate of the second PMOS current mirror 12 is connected to the gate of the first PMOS current mirror 11, and the drain of the second PMOS current mirror 12 is connected to the drain of the first NMOS current mirror 13; the grid electrode of the first NMOS current mirror 13 is respectively connected with the drain electrode of the first NMOS current mirror 13, the direct current offset circuit 4 and the rectifying circuit 3, and the source electrode is grounded;
the current transfer ratio of the first input stage and the first output stage is equal to the ratio of the width-to-length ratio of the first PMOS current mirror 11 to the width-to-length ratio of the second PMOS current mirror 12.
It should be noted that, in the embodiment of the present application, in the first mirror constant current source, the magnitude of the reference current source 10 depends on the actual situation of the power detection circuit.
It should be noted that, in the embodiment of the present application, a current ratio of the input stage and the output stage of the first mirror constant current source is equal to a ratio of a width-to-length ratio of the first PMOS current mirror 11 to a width-to-length ratio of the second PMOS current mirror 12, so that the current ratio of the input stage and the output stage of the first mirror constant current source can be determined by adjusting the ratio of the width-to-length ratio of the first PMOS current mirror 11 to the width-to-length ratio of the second PMOS current mirror 12 according to an actual scene and an application requirement.
It should be further noted that, in the embodiment of the present application, the current ratio of the input stage to the output stage output of the first mirror constant current source in the embodiment of the present application is 1: 1.
In the embodiment of the present application, the gate of the first NMOS current mirror 13 is used as the output terminal of the bias circuit 1, and provides a bias voltage to the dc cancel circuit 4 and the rectifier circuit 3, so as to generate a quiescent current, and the bias voltage can make the dc cancel circuit 4 and the rectifier circuit 3 operate in a linear region, a saturation region, or an off region.
Specifically, in the embodiment of the present application, the bias voltage causes the dc offset circuit 4 and the rectifier circuit 3 to operate in the saturation region.
Specifically, in the embodiment of the present application, the gain control circuit 2 includes a second mirror constant current source;
the second mirror image constant current source is composed of a second input stage and a second output stage, the second input stage comprises a third PMOS current mirror 21, and the second output stage comprises a fourth PMOS current mirror 22;
the source electrode of the third PMOS current mirror 21 and the source electrode of the fourth PMOS current mirror 22 are connected with a power supply; the drain electrode of the third PMOS current mirror 21 is connected to the gate electrode of the third PMOS current mirror 21, the rectifying circuit 3, and the dc offset circuit 4, respectively; the grid electrode of the fourth PMOS current mirror 22 is connected with the grid electrode of the third PMOS current mirror 21, and the drain electrode of the fourth PMOS current mirror 22 is connected with the power amplifier 6;
the current transfer ratio of the second input stage and the second output stage is equal to the ratio of the width-to-length ratio of the third PMOS current mirror 21 to the width-to-length ratio of the fourth PMOS current mirror 22.
It should be noted that, in the embodiment of the present application, a current ratio of the input stage and the output stage of the second mirror constant current source in the gain control circuit 2 is equal to a ratio of the width-to-length ratio of the third PMOS current mirror 21 to the width-to-length ratio of the fourth PMOS current mirror 22, that is, the current ratio of the input stage and the output stage of the second mirror constant current source is an amplification factor of the gain control circuit 2, and can be adjusted according to an actual amplification requirement.
It should be further noted that, in the embodiment of the present application, the current ratio of the input stage and the output stage output of the second mirror constant current source in the embodiment of the present application is 1:1, that is, the amplification factor of the gain control circuit 2 is 1, and the input stage and the output stage output currents of the second mirror constant current source are equal.
It should be noted that, in the embodiment of the present application, the gain control circuit 2 is configured to amplify the first current and the second current obtained through cancellation current cancellation and offset compensation current offset compensation to obtain a detection current, and input the detection current into the power amplifier 6 to perform current compensation on the power amplifier 6.
Specifically, in the embodiment of the present application, the rectifier circuit 3 includes a fixed resistor 30, a capacitor 31, and a second NMOS current mirror 32;
one end of the capacitor 31 is connected with a radio frequency signal, and the other end of the capacitor is connected with the grid of the second NMOS current mirror 32; one end of the fixed resistor 30 is connected with the grid of the second NMOS current mirror 32, and the other end is connected with the bias circuit 1; the drain of the second NMOS current mirror 32 is connected to the dc offset circuit 4 and the gain control circuit 2, respectively, and the source of the second NMOS current mirror 32 is grounded.
It should be noted that, in the embodiment of the present application, the fixed resistor 30 is an isolation resistor for the rf signal, and is used to isolate the rf signal so as to prevent the input rf signal from flowing into the bias circuit 1. The capacitor 31 is a dc blocking capacitor, and is used to isolate the bias circuit 1 to prevent the static current provided by the bias circuit 1 from flowing into the rf signal.
Specifically, in the embodiment of the present application, a dc offset circuit 4 is added, and the dc offset circuit 4 includes a third mirror constant current source and a third NMOS current mirror 40;
the third mirror constant current source is composed of a third input stage and a third output stage, the third input stage comprises a fifth PMOS current mirror 41, and the third output stage comprises a sixth PMOS current mirror 42;
the source electrode of the fifth PMOS current mirror 41 and the source electrode of the sixth PMOS current mirror 42 are connected with a power supply; the gate of the fifth PMOS current mirror 41 is connected to the drain of the fifth PMOS current mirror 41, and the gate of the sixth PMOS current mirror 42, respectively; the drain of the fifth PMOS current mirror 41 is connected to the drain of the third NMOS current mirror 40 and the offset compensation circuit 5, respectively; the drain electrode of the sixth PMOS current mirror 42 is connected to the rectifying circuit 3 and the gain control circuit 2, respectively; the grid electrode of the third NMOS current mirror 40 is connected with the bias circuit 1, and the source electrode of the third NMOS current mirror 40 is grounded;
the current transfer ratio of the third input stage and the third output stage is equal to the ratio of the width-to-length ratio of the fifth PMOS current mirror 41 to the width-to-length ratio of the sixth PMOS current mirror 42.
It should be noted that, in the embodiment of the present application, the third NMOS current mirror 40 receives the bias voltage provided by the bias circuit 1, and generates the quiescent current.
It should be noted that, in the embodiment of the present application, a current ratio of the output of the third input stage and the third output stage of the third mirrored constant current source is 1:1, that is, the input stage and the output stage of the third mirrored constant current source are equal, and the current output by the third output stage is used for canceling the static current in the first current output by the rectifier circuit 3.
Specifically, in the embodiment of the present application, the first NMOS current mirror 13 in the bias circuit 1 and the second NMOS current mirror 32 in the rectifier circuit 3 constitute a fifth mirror constant current source;
the fifth mirror constant current source is composed of a fifth input stage and a fifth output stage, the fifth input stage comprises a first NMOS current mirror 13, and the fifth output stage comprises a second NMOS current mirror 32;
the current transfer ratio of the fifth input stage and the fifth output stage is equal to the ratio of the width-to-length ratio of the first NMOS current mirror 13 to the width-to-length ratio of the second NMOS current mirror 32.
Specifically, in the embodiment of the present application, the first NMOS current mirror 13 in the bias circuit 1 and the third NMOS current mirror 40 of the dc cancellation circuit 4 constitute a sixth mirror constant current source;
the sixth mirror constant current source 70 is composed of a fifth input stage including the first NMOS current mirror 13 and a sixth output stage including the third NMOS current mirror 40;
the current transfer ratio of the fifth input stage and the sixth output stage is equal to the ratio of the width-to-length ratio of the first NMOS current mirror 13 to the width-to-length ratio of the third NMOS current mirror 40.
It should be noted that, in the embodiment of the present application, the current transfer ratio of the fifth input stage and the fifth output stage is equal to the ratio of the width-to-length ratio of the first NMOS current mirror 13 to the width-to-length ratio of the second NMOS current mirror 32, and the fifth input stage and the fifth output stageThe current transfer ratio of the sixth output stage is equal to the ratio of the width-to-length ratio of the first NMOS current mirror 13 to the width-to-length ratio of the third NMOS current mirror 40, that is, the current ratio output by the sixth output stage and the fifth output stage can be determined according to the equality of the fifth input stage, and is equal to the ratio of the width-to-length ratio of the second NMOS current mirror 32 to the width-to-length ratio of the third NMOS current mirror 40, so that the counteracting current in the dc counteracting circuit 4 can be determined by adjusting the ratio of the width-to-length ratio of the second NMOS current mirror 32 to the width-to-length ratio of the third NMOS current mirror 40 according to actual scenes and application requirements
Figure 684340DEST_PATH_IMAGE022
The magnitude of the cancellation of the quiescent current in the first current.
It should be noted that, in the embodiment of the present application, by adjusting the size of the third NMOS current mirror 40 to make the size of the third NMOS current mirror 40 equal to the size of the second NMOS current mirror 32, the drain current of the third NMOS current mirror 40 is obtained
Figure 735473DEST_PATH_IMAGE022
Comprises the following steps:
Figure 395124DEST_PATH_IMAGE024
wherein the content of the first and second substances,
Figure 291536DEST_PATH_IMAGE003
，
Figure 87454DEST_PATH_IMAGE004
in order to achieve the mobility of the carriers,
Figure 43909DEST_PATH_IMAGE005
is the capacitance per unit area of the oxide layer,
Figure 394119DEST_PATH_IMAGE006
the gate width of the third NMOS current mirror 40,
Figure 159468DEST_PATH_IMAGE007
the gate length of the third NMOS current mirror 40,
Figure 278734DEST_PATH_IMAGE025
the gate and source voltages of the third NMOS current mirror 40,
Figure 140510DEST_PATH_IMAGE026
is the threshold voltage of the third NMOS current mirror 40.
Since the size of the third NMOS current mirror 40 is equal to the size of the second NMOS current mirror 32, i.e., the ratio of the width-to-length ratio of the second NMOS current mirror 32 to the width-to-length ratio of the third NMOS current mirror 40 is 1, therefore,
Figure 978016DEST_PATH_IMAGE027
and
Figure 481810DEST_PATH_IMAGE028
equalisation, i.e. first current output by the rectifying circuit 3
Figure 986741DEST_PATH_IMAGE001
Is equal to the drain current of the third NMOS current mirror 40
Figure 284998DEST_PATH_IMAGE022
Then, the current after the first current is cancelled by the cancellation current is:
Figure 609800DEST_PATH_IMAGE030
at this time, the quiescent current in the first current is completely cancelled by the cancellation current, so that the detection current amplified by the gain control circuit
Figure 648776DEST_PATH_IMAGE017
The starting point of the power variation trend graph with the input RF signal is 0, as shown by the solid line part in FIG. 4, and the abscissa is the power of the input RF signal
Figure 477055DEST_PATH_IMAGE021
With ordinate representing the output detected current
Figure 8530DEST_PATH_IMAGE017
。
It should be further noted that, in the embodiment of the present application, by adjusting the size of the third NMOS current mirror 40, the ratio of the width-to-length ratio of the second NMOS current mirror 32 to the width-to-length ratio of the third NMOS current mirror 40 can be determined, and then the current ratio of the outputs of the fifth output stage and the sixth output stage is determined, that is, the offset current in the dc offset circuit 4 is determined
Figure 289470DEST_PATH_IMAGE022
For the offset magnitude of the quiescent current in the first current, the detection current obtained by the first current through offset current offset and gain control circuit amplification is:
Figure 400645DEST_PATH_IMAGE032
wherein the content of the first and second substances,
Figure 145747DEST_PATH_IMAGE033
，
Figure 51386DEST_PATH_IMAGE034
is the overdrive voltage of the second NMOS current mirror 32,
Figure 85202DEST_PATH_IMAGE035
，
Figure 468910DEST_PATH_IMAGE036
for the overdrive voltage of the third NMOS current mirror 40, it can be seen from equation (7) that adjusting the size of the third NMOS current mirror 40 can adjust
Figure 286429DEST_PATH_IMAGE036
And then change the size of
Figure 362969DEST_PATH_IMAGE037
Adjusting the detected current
Figure 680818DEST_PATH_IMAGE017
The starting point of the power variation trend graph of the input RF signal, as shown by the dotted line portion in FIG. 4, has the abscissa of the power of the input RF signal
Figure 602638DEST_PATH_IMAGE021
With ordinate representing the output detected current
Figure 525594DEST_PATH_IMAGE017
。
Specifically, in the embodiment of the present application, the offset compensation circuit 5 includes a seventh PMOS current mirror 50, a variable resistor 51, a fourth NMOS current mirror 52, and a fifth NMOS current mirror 53;
the seventh PMOS current mirror is used as a fourth output stage and forms a fourth mirror constant current source with the first output stage formed by the reference current source and the first PMOS current mirror in the bias circuit;
the gate of the seventh PMOS current mirror 50 is connected to the gate of the first PMOS current mirror 11; in the seventh PMOS current mirror 50, the drain is connected to the variable resistor 51 and the gate of the fifth NMOS current mirror 53, respectively, and the source is connected to the power supply; the variable resistor 51 is connected to the drain of the fourth NMOS current mirror 52; the drain of the fourth NMOS current mirror 52 is connected to the gate of the fourth NMOS current mirror 52, and the drain of the fifth NMOS current mirror 53 is connected to the dc offset circuit 4; the source of the fourth NMOS current mirror 52 and the source of the fifth NMOS current mirror 53 are grounded, respectively;
the current transfer ratio of the first input stage and the fourth output stage is equal to the ratio of the width-to-length ratio of the first PMOS current mirror 11 to the width-to-length ratio of the seventh PMOS current mirror 50.
It should be noted that, in the embodiment of the present application, the gate voltage of the fifth NMOS current mirror 53 may be changed by adjusting the size of the variable resistor 51
Figure 38615DEST_PATH_IMAGE038
And further adjusting the offset compensation circuit 5 for realizing the detection of the current
Figure 250285DEST_PATH_IMAGE017
Offset compensation current for offset compensation
Figure 241375DEST_PATH_IMAGE039
Offset compensating current
Figure 815576DEST_PATH_IMAGE039
The expression of (a) is:
Figure 965410DEST_PATH_IMAGE041
wherein the content of the first and second substances,
Figure 195534DEST_PATH_IMAGE038
comprises the following steps:
Figure 787052DEST_PATH_IMAGE043
wherein the content of the first and second substances,
Figure 419022DEST_PATH_IMAGE044
is the threshold voltage of the fourth NMOS current mirror 52,
Figure 211528DEST_PATH_IMAGE045
is the overdrive voltage of the fourth NMOS current mirror 52,
Figure 194528DEST_PATH_IMAGE046
is the voltage across the variable resistor 51.
When the size of the fourth NMOS current mirror 52 is large enough,
Figure 527420DEST_PATH_IMAGE045
can be ignored, then
Figure 810634DEST_PATH_IMAGE047
At this time, the offset compensation current
Figure 839289DEST_PATH_IMAGE039
The expression of (a) is:
Figure DEST_PATH_IMAGE049
then, the offset compensated current
Figure 981688DEST_PATH_IMAGE039
After compensation, the third current outputted by the DC offset circuit 4
Figure DEST_PATH_IMAGE050
Comprises the following steps:
Figure 55954DEST_PATH_IMAGE052
the third current
Figure 131358DEST_PATH_IMAGE050
Is injected into the drain terminal of the second NMOS current mirror 32 for rectifying the first current output by the circuit
Figure 327984DEST_PATH_IMAGE001
Carrying out offset and compensation, and obtaining detection current through a gain control circuit
Figure 551155DEST_PATH_IMAGE017
：
Figure DEST_PATH_IMAGE054
As can be seen from equation (12), by adjusting the size of the variable resistor 51, the voltage across the variable resistor 51 is changed
Figure DEST_PATH_IMAGE055
Further change the detection current
Figure 629445DEST_PATH_IMAGE017
The turning point of the trend graph of the power of the input RF signal is shown in FIG. 5, and the abscissa is the power of the input RF signal
Figure 887251DEST_PATH_IMAGE021
With ordinate representing the output detected current
Figure 989199DEST_PATH_IMAGE017
。
Specifically, in the embodiment of the present application, the variable resistor 51 includes: a first switch 511, a second switch 512, a third switch 513, a first resistor 514, a second resistor 515, a third resistor 516, and a base resistor 517;
the first switch 511 is connected in parallel with the first resistor 514 to form a first parallel circuit; the second switch 512 is connected in parallel with the second resistor 515 to form a second parallel circuit; the third switch 513 is connected in parallel with the third resistor 516 to form a third parallel circuit; one end of the first parallel circuit, the second parallel circuit, the third parallel circuit and the basic resistor 517 are connected in series, and the other end of the basic resistor 517 is connected with the drain electrode of the fourth NMOS current mirror 52;
a first switch 511, a second switch 512 and a third switch 513 for controlling a resistance in series with a base resistance 517.
In the embodiment of the present application, when the first switch 511 is turned on, the first resistor 514 is short-circuited, when the first switch 511 is turned off, the first resistor 514 is connected in series with the base resistor 517, when the second switch 512 is turned on, the second resistor 515 is short-circuited, when the second switch 512 is turned off, the second resistor 515 is connected in series with the base resistor 517, when the third switch 513 is turned on, the third resistor 516 is short-circuited, and when the third switch 513 is turned off, the third resistor 516 is connected in series with the base resistor 517.
It should be further noted that, in the embodiment of the present application, the first switch 511, the second switch 512, and the third switch 513 are used to control the resistor connected in series with the base resistor 517, as shown in fig. 6, when all of the first switch 511, the second switch 512, and the third switch 513 are turned on, the resistance of the variable resistor 51 is the smallest, and when all of the first switch 511, the second switch 512, and the third switch 513 are turned off, the resistance of the variable resistor 51 is the largest.
The embodiment of the application discloses power amplifier's power detection circuit, power detection circuit includes: the circuit comprises a bias circuit, a rectifying circuit, a direct current offset circuit, an offset compensation circuit and a gain control circuit; the bias circuit is connected with the rectifying circuit and the direct current offset circuit respectively and is used for providing bias voltage for the rectifying circuit and the direct current offset circuit respectively; the rectifier circuit is used for converting an input radio frequency signal into direct current and superposing the direct current and the static current to obtain first current; the direct current offset circuit is respectively connected with the offset compensation circuit and the rectification circuit; the offset compensation circuit is used for providing an offset compensation current to offset the first current; the gain control circuit is connected with the rectifying circuit and the power amplifier respectively, and is used for amplifying the first current and a second current obtained by offsetting the current and offsetting the compensating current to obtain a detection current, and inputting the detection current into the power amplifier so as to perform current compensation on the power amplifier. The embodiment of the application provides a power detection circuit of power amplifier, has added direct current offset circuit and skew compensation circuit on current power detection circuit's basis, not only can realize output current's range regulation to can satisfy the compensation demand to different amplifiers, the flexibility is higher.
The embodiment of the present application further provides a power detection method of a power amplifier, which is applied to the power detection circuit including the bias circuit, the rectification circuit, the dc offset circuit, the offset compensation circuit, and the gain control circuit, and fig. 7 is a schematic flow diagram of the power detection method of the power amplifier provided in the embodiment of the present application. As shown in fig. 7, the method mainly comprises the following steps:
s701, receiving a bias voltage provided by a bias circuit through a rectification circuit to generate a static current.
In the embodiment of the present application, referring to fig. 3, the bias circuit 1 in the power detection circuit is connected to the gate of the second NMOS current mirror 32 in the rectification circuit 3, and provides a bias voltage to the second NMOS current mirror 32, so as to generate a quiescent current.
It should be noted that, in the embodiment of the present application, the bias circuit 1 provides a bias voltage for the second NMOS current mirror 32, so that the second NMOS current mirror 32 can operate in a linear region, a saturation region, or an off region, and the present application is not limited in particular.
S702, converting the input radio frequency signal into direct current through a rectifying circuit, and superposing the direct current and static current to obtain first current.
In the embodiment of the present application, referring to fig. 3, the rectifier circuit 3 converts an input radio frequency signal into a direct current, and outputs the direct current from the drain of the second NMOS current mirror 32 in the rectifier circuit 3.
It should be noted that, in the embodiment of the present application, the first current output from the drain of the second NMOS current mirror 32 in the rectifier circuit 3 includes both the dc current converted from the input radio frequency signal and the quiescent current generated by the bias circuit 1 for the bias voltage provided by the second NMOS current mirror 32.
And S703, providing a cancellation current to cancel the static current in the first current through the direct current cancellation circuit, and providing an offset compensation current to offset compensate the first current through the offset compensation circuit.
In the embodiment of the present application, referring to fig. 3, the offset current of the dc offset circuit 4 flows into the drain of the second NMOS current mirror 32 in the rectifying circuit 3 via the third mirror constant current source, and offsets the quiescent current in the first current, thereby changing the detection current amplified by the gain control circuit
Figure 902928DEST_PATH_IMAGE017
The starting point of the change with the power of the input rf signal is shown in fig. 4.
It should be further noted that, in the embodiment of the present application, the dc cancellation circuit 4 cancels the quiescent current in the first current output by the drain of the second NMOS current mirror 32, and the magnitude of the cancellation current directly affects the detection current
Figure 381314DEST_PATH_IMAGE017
Detecting the current if the offset current and the quiescent current are equal to each other with the starting point of the power change of the input radio frequency signal
Figure 759206DEST_PATH_IMAGE017
The starting point of the power variation with the input radio frequency signal is 0.
It should be further noted that, in the embodiment of the present application, the size of the third NMOS current mirror 40 may be set according to requirements and scenarios to determine the magnitude of the offset current output by the drain of the third NMOS current mirror 40, so as to determine the detection current
Figure 898633DEST_PATH_IMAGE017
A starting point of a power variation with an input radio frequency signal.
It should be noted that, in the embodiment of the present application, the resistance of the variable resistor 51 in the offset compensation circuit 5 can be adjusted according to the requirement, so as to achieve different offset compensation in the first current output by the drain of the second NMOS current mirror 32, so that the detection current is made to be different
Figure 768500DEST_PATH_IMAGE017
The turning points are different along with the change of the power of the input radio frequency signal. Referring to fig. 3, the current outputted from the offset compensation circuit 5 flows into the input terminal of the dc offset circuit 4, passes through the dc offset circuit 4, flows into the drain of the second NMOS current mirror 32 in the rectification circuit 3, performs offset compensation on the first current outputted from the rectification circuit 3, and further changes the second current
Figure 581735DEST_PATH_IMAGE017
The turning point of the variation with the power of the input rf signal is shown in fig. 5.
It should be noted that, in the embodiment of the present application, the offset compensation circuit 5 performs offset compensation on the first current output by the drain of the second NMOS current mirror 32, and the magnitude of the offset compensation current directly affects the detection current
Figure 17395DEST_PATH_IMAGE017
If the offset compensation current is large, the detection current is changed along with the power change of the input radio frequency signal
Figure 992305DEST_PATH_IMAGE017
The turning point of the change along with the power of the input radio frequency signal is smaller, and if the offset compensation current is small, the detection current
Figure 146205DEST_PATH_IMAGE017
The turning point along with the power change of the input radio frequency signal is larger, and the turning point are in negative correlation.
And S704, amplifying the first current and the second current after offset current cancellation and offset compensation current offset compensation through a gain control circuit to obtain a detection current, and inputting the detection current into a power amplifier to perform current compensation on the power amplifier.
In the embodiment of the present application, the first current output from the rectifying circuit 3 is offset by the offset current of the dc offset circuit 4 to obtain the quiescent current of the first current, the first current is offset-compensated by the offset compensation current of the offset compensation circuit 5 to obtain the second current, and then the second current is amplified by the gain control circuit 2 to obtain the detection current, and the detection current is input to the power amplifier 6.
The embodiment of the application provides a power detection method of a power amplifier, which is applied to a power detection circuit of the power amplifier, wherein the power detection circuit comprises: the circuit comprises a bias circuit, a rectifying circuit, a direct current offset circuit, an offset compensation circuit and a gain control circuit, and the method comprises the following steps: receiving a bias voltage provided by a bias circuit through a rectifying circuit to generate a static current; converting an input radio frequency signal into direct current through a rectifying circuit, and superposing the direct current and the static current to obtain first current; providing a counteracting current to counteract the static current in the first current through a direct current counteracting circuit, and providing an offset compensating current to offset compensate the first current through an offset compensating circuit; and amplifying the first current and a second current obtained by offsetting the offset current and offset compensation through a gain control circuit to obtain a detection current, and inputting the detection current into a power amplifier to perform current compensation on the power amplifier. The embodiment of the application provides a power detection circuit of power amplifier, has added direct current offset circuit and skew compensation circuit on current power detection circuit's basis, not only can realize output current's range regulation to can satisfy the compensation demand to different amplifiers, the flexibility is higher.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application are included in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A power detection circuit for a power amplifier, the power detection circuit comprising: the circuit comprises a bias circuit, a rectifying circuit, a direct current offset circuit, an offset compensation circuit and a gain control circuit;
the bias circuit is connected with the rectifying circuit and the direct current offset circuit respectively, and is used for providing bias voltage for the rectifying circuit and the direct current offset circuit respectively;
the rectifier circuit is used for converting an input radio frequency signal into direct current and superposing the direct current and the static current to obtain a first current;
the direct current offset circuit is respectively connected with the offset compensation circuit and the rectification circuit; the direct current offset circuit is configured to provide an offset current to offset the quiescent current in the first current, and the offset compensation circuit is configured to provide an offset compensation current to offset compensate the first current;
the gain control circuit is connected with the rectifying circuit and the power amplifier respectively, and is used for amplifying a second current obtained by offsetting the first current by the offset current and offset compensating the offset compensating current to obtain a detection current, and inputting the detection current into the power amplifier so as to perform current compensation on the power amplifier.
2. The power detection circuit of claim 1, wherein the bias circuit comprises a first mirrored constant current source and a first NMOS current mirror;
the first mirror image constant current source is composed of a first input stage and a first output stage, the first input stage comprises a reference current source and a first PMOS current mirror, and the first output stage comprises a second PMOS current mirror;
the source electrode of the first PMOS current mirror and the source electrode of the second PMOS current mirror are connected with a power supply;
the drain electrode of the first PMOS current mirror is connected with a reference current source and is connected with the gate electrode of the first PMOS current mirror;
the grid electrode of the second PMOS current mirror is connected with the grid electrode of the first PMOS current mirror, and the drain electrode of the second PMOS current mirror is connected with the drain electrode of the first NMOS current mirror;
the grid electrode of the first NMOS current mirror is respectively connected with the drain electrode of the first NMOS current mirror, the direct current offset circuit and the rectifying circuit, and the source electrode of the first NMOS current mirror is grounded;
the current transfer ratio of the first input stage and the first output stage is equal to the ratio of the width-to-length ratio of the first PMOS current mirror to the width-to-length ratio of the second PMOS current mirror.
3. The power detection circuit of claim 1, wherein the gain control circuit comprises a second mirrored constant current source;
the second mirror image constant current source is composed of a second input stage and a second output stage, the second input stage comprises a third PMOS current mirror, and the second output stage comprises a fourth PMOS current mirror;
the source electrode of the third PMOS current mirror and the source electrode of the fourth PMOS current mirror are connected with a power supply;
the drain electrode of the third PMOS current mirror is respectively connected with the grid electrode of the third PMOS current mirror, the rectifying circuit and the direct current offset circuit;
the grid electrode of the fourth PMOS current mirror is connected with the grid electrode of the third PMOS current mirror, and the drain electrode of the fourth PMOS current mirror is connected with the power amplifier;
the current transmission ratio of the second input stage and the second output stage is equal to the ratio of the width-to-length ratio of the third PMOS current mirror to the width-to-length ratio of the fourth PMOS current mirror.
4. The power detection circuit of claim 2, wherein the rectification circuit comprises a fixed resistor, a capacitor, and a second NMOS current mirror;
one end of the capacitor is connected with the radio frequency signal, and the other end of the capacitor is connected with the grid electrode of the second NMOS current mirror;
one end of the fixed resistor is connected with the grid electrode of the second NMOS current mirror, and the other end of the fixed resistor is connected with the bias circuit;
and the drain electrode of the second NMOS current mirror is respectively connected with the direct current offset circuit and the gain control circuit, and the source electrode of the second NMOS current mirror is grounded.
5. The power detection circuit of claim 2, wherein the dc cancellation circuit comprises a third mirrored constant current source and a third NMOS current mirror;
the third mirror constant current source is composed of a third input stage and a third output stage, the third input stage comprises a fifth PMOS current mirror, and the third output stage comprises a sixth PMOS current mirror;
the source electrode of the fifth PMOS current mirror and the source electrode of the sixth PMOS current mirror are connected with a power supply;
the grid electrode of the fifth PMOS current mirror is connected with the drain electrode of the fifth PMOS current mirror and the grid electrode of the sixth PMOS current mirror respectively; the drain electrode of the fifth PMOS current mirror is respectively connected with the drain electrode of the third NMOS current mirror and the offset compensation circuit;
the drain electrode of the sixth PMOS current mirror is respectively connected with the rectifying circuit and the gain control circuit;
the grid electrode of the third NMOS current mirror is connected with the bias circuit, and the source electrode of the third NMOS current mirror is grounded;
the current transfer ratio of the third input stage and the third output stage is equal to the ratio of the width-to-length ratio of the fifth PMOS current mirror to the width-to-length ratio of the sixth PMOS current mirror.
6. The power detection circuit of claim 2, wherein the offset compensation circuit comprises a seventh PMOS current mirror, a variable resistor, a fourth NMOS current mirror, and a fifth NMOS current mirror;
the seventh PMOS current mirror is used as a fourth output stage and forms a fourth mirror constant current source with the first input stage formed by the reference current source and the first PMOS current mirror in the bias circuit;
the grid electrode of the seventh PMOS current mirror is connected with the grid electrode of the first PMOS current mirror;
in the seventh PMOS current mirror, a drain electrode is respectively connected with one end of the variable resistor and a grid electrode of the fifth NMOS current mirror, and a source electrode is connected with a power supply;
the other end of the variable resistor is connected with the drain electrode of the fourth NMOS current mirror;
the drain electrode of the fourth NMOS current mirror is connected with the grid electrode of the fourth NMOS current mirror, and the drain electrode of the fifth NMOS current mirror is connected with the direct current offset circuit;
the source electrode of the fourth NMOS current mirror and the source electrode of the fifth NMOS current mirror are respectively grounded;
the current transfer ratio of the first input stage and the fourth output stage is equal to the ratio of the width-to-length ratio of the first PMOS current mirror to the width-to-length ratio of the seventh PMOS current mirror.
7. The power detection circuit of claim 6, wherein the variable resistance comprises: the circuit comprises a first switch, a second switch, a third switch, a first resistor, a second resistor, a third resistor and a basic resistor;
the first switch is connected with the first resistor in parallel to form a first parallel circuit;
the second switch is connected with the second resistor in parallel to form a second parallel circuit;
the third switch is connected with the third resistor in parallel to form a third parallel circuit;
the first parallel circuit, the second parallel circuit and the third parallel circuit are connected in series and then are connected in series with one end of the basic resistor, and the other end of the basic resistor is connected with the drain electrode of the fourth NMOS current mirror;
the first switch, the second switch and the third switch are used for controlling a resistor connected with the base resistor in series.
8. The power detection circuit of claim 4, wherein the first NMOS current mirror in the bias circuit and the second NMOS current mirror of the rectification circuit form a fifth mirror constant current source;
the fifth mirror constant current source is composed of a fifth input stage and a fifth output stage, the fifth input stage comprises the first NMOS current mirror, and the fifth output stage comprises the second NMOS current mirror;
the current transfer ratio of the fifth input stage and the fifth output stage is equal to the ratio of the width-to-length ratio of the first NMOS current mirror to the width-to-length ratio of the second NMOS current mirror.
9. The power detection circuit of claim 5, wherein the first NMOS current mirror of the bias circuit and the third NMOS current mirror of the DC cancellation circuit form a sixth mirror constant current source;
the sixth mirror constant current source is composed of a fifth input stage and a sixth output stage, the fifth input stage comprises the first NMOS current mirror, and the sixth output stage comprises the third NMOS current mirror;
the current transfer ratio of the fifth input stage and the sixth output stage is equal to the ratio of the width-to-length ratio of the first NMOS current mirror to the width-to-length ratio of the third NMOS current mirror.
10. A power detection method of a power amplifier is applied to a power detection circuit, wherein the power detection circuit comprises a bias circuit, a rectifying circuit, a direct current cancellation circuit, an offset compensation circuit and a gain control circuit, and the method comprises the following steps:
receiving a bias voltage provided by the bias circuit through the rectifying circuit to generate a static current;
converting an input radio frequency signal into direct current through the rectifying circuit, and superposing the direct current and the static current to obtain first current;
providing a cancellation current to cancel the quiescent current in the first current through the direct current cancellation circuit, and providing an offset compensation current to offset compensate the first current through the offset compensation circuit;
and amplifying the first current and a second current obtained by offsetting the offset current and offset compensating the offset compensation current through a gain control circuit to obtain a detection current, and inputting the detection current into a power amplifier to perform current compensation on the power amplifier.
CN202110183211.3A 2021-02-10 2021-02-10 Power detection circuit and method of power amplifier Active CN112532191B (en)

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