CN112530896A - Lead frame for semiconductor packaging and preparation method thereof - Google Patents
Lead frame for semiconductor packaging and preparation method thereof Download PDFInfo
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- CN112530896A CN112530896A CN202011525742.8A CN202011525742A CN112530896A CN 112530896 A CN112530896 A CN 112530896A CN 202011525742 A CN202011525742 A CN 202011525742A CN 112530896 A CN112530896 A CN 112530896A
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- 238000002360 preparation method Methods 0.000 title abstract description 6
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- 229910052709 silver Inorganic materials 0.000 claims description 18
- 239000004332 silver Substances 0.000 claims description 18
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- 229910052802 copper Inorganic materials 0.000 claims description 8
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- BZSXEZOLBIJVQK-UHFFFAOYSA-N 2-methylsulfonylbenzoic acid Chemical compound CS(=O)(=O)C1=CC=CC=C1C(O)=O BZSXEZOLBIJVQK-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical group [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 claims 1
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- NNFCIKHAZHQZJG-UHFFFAOYSA-N potassium cyanide Chemical compound [K+].N#[C-] NNFCIKHAZHQZJG-UHFFFAOYSA-N 0.000 description 2
- 238000011179 visual inspection Methods 0.000 description 2
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- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention belongs to the technical field of semiconductor devices, and particularly relates to a lead frame for semiconductor packaging and a preparation method thereof. The lead frame comprises a frame body and an electroplated layer, wherein the upper surface of the frame body is provided with a plurality of micro-etched grooves, the electroplated layer is filled in each micro-etched groove, and the thickness of the electroplated layer is the same as that of the micro-etched grooves. The lead frame of the invention forms a concave micro-etching groove on the frame body by a mode of micro-etching and then electroplating, so that the electroplating layer is formed in the micro-etching groove, and through reasonable control of the micro-etching and electroplating processes, the thickness of the lead frame can be reduced, the thinning production of semiconductor packaging is facilitated, and the lead frame can play a role in protecting the electroplating layer, thereby better ensuring the weldability and the product qualification rate.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a lead frame for semiconductor packaging and a preparation method thereof.
Background
The lead frame is a basic component for manufacturing semiconductor elements of the integrated circuit, provides a carrier for a chip of the integrated circuit, realizes electrical connection between the chip and an external circuit board by means of bonding materials, and also provides a heat dissipation channel together with a package shell for releasing heat. With the trend of miniaturization development of electronic products, packaging technologies with high integration and small volume gradually become the main market demand, and the requirements of semiconductor packaging products on thinning and miniaturization are higher and higher. The quad flat non-leaded package (QFN) has the characteristics of small pad size and small volume, and is more suitable for portable small electronic equipment with requirements on integration level, size and performance compared with the traditional package technologies such as SOIC, TSOP, QFP and the like.
However, it is a technical challenge to realize multi-type functions in a miniaturized package and simultaneously satisfy the requirements of heat dissipation, voltage resistance, radiation resistance and other reliable performances against severe environments. At present, in order to comply with the market trend of thinning of packaged products, the thickness of a chip is often reduced by grinding during packaging, and in recent years, the thinning of a lead frame is also increasingly researched. However, the lead frame is easily warped and deformed during storage and transportation due to the overall thinning. In addition, the lead welding point is needed to be provided on the surface of the existing lead frame through electroplating, the electroplated layer also has certain thickness, and meanwhile, the height of lead bonding can be increased, so that the thickness reduction of the packaging body is not facilitated. The electroplated layer protruding from the surface of the lead frame is also easily damaged or scratched, which is not beneficial to routing and also can affect the reliability of the packaged product.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides the lead frame which is beneficial to realizing the thinning of the semiconductor package and has higher reliability and the preparation method thereof.
The above object of the present invention is achieved by the following technical solutions: the utility model provides a lead frame for semiconductor package, includes frame body and plating layer, the upper surface of frame body has a plurality of microetching grooves, and each microetching inslot all fills there is above-mentioned plating layer.
Preferably, the thickness of the plating layer is the same as the thickness of the micro-etched groove.
The thickness of the known QFN product is usually 0.55-0.75 mm, including the sum of the heights of a lead frame, a chip, silver paste and lead radian, while the thickness of the current lead frame is 0.1-0.254 mm, the thickness of the chip is 0.2mm, the height of a wire arc can reach 0.2mm, the whole thickness is difficult to thin, and an electroplated layer is easy to scratch or wear. The electroplated layer is arranged in the micro-etched groove of the frame body, the surface of the electroplated layer is flush with the upper surface of the frame body, the whole thickness of the lead frame is the thickness of the frame body, the wire arc height can be properly reduced during lead bonding, and the thin production of a packaging product is facilitated. And the electroplated layer does not protrude out of the surface of the frame body any more, so that the probability of scratching and scuffing is greatly reduced, and better weldability and higher product yield can be ensured.
Preferably, the thickness of the electroplated layer is 1.5-10 μm.
Preferably, the electroplated layer is a nickel-palladium-gold electroplated layer or a silver electroplated layer.
Preferably, the frame body is made of copper or copper alloy material.
Another object of the present invention is to provide a method for manufacturing a lead frame for a semiconductor package, comprising the steps of:
(1) film pasting: respectively attaching a layer of dry film on the upper surface and the lower surface of the substrate;
(2) micro-etching: removing part of the dry film on the upper surface of the substrate through exposure and development to expose a local area of the upper surface of the substrate; then, carrying out micro-etching treatment on the local area to form a micro-etching groove on the substrate;
(3) electroplating: treating the substrate with an electroplating solution to form an electroplated layer in the exposed micro-etching groove;
(4) etching: sticking a dry film again to cover the electroplated layer, and removing partial dry films on the upper surface and the lower surface of the substrate through exposure and development to expose a region to be etched; etching the substrate to obtain a frame body with etching holes;
(5) removing the film: and removing the residual dry films on the upper surface and the lower surface of the lead frame, and cleaning and drying to obtain the lead frame.
The method comprises the steps of forming a micro-etching groove on a substrate of the lead frame through micro-etching treatment, forming an electroplated layer in the micro-etching groove through an electroplating process, and controlling process parameters to ensure that the height of the electroplated layer does not exceed the upper surface of the frame body, so that the electroplated layer is protected from being scratched. Therefore, the microetching treatment needs to be carried out quickly, and the depth of the microetching is controlled within the range of 1.5-10 mu m through the limitation of process parameters.
Preferably, the microetching treatment in step (2) is performed by spraying the upper surface of the substrate with a microetching solution, wherein the microetching solution mainly comprises copper chloride, sodium chlorate and hydrochloric acid.
More preferably, Cu in the microetching solution2+The concentration is 110-170 g/L, H+The concentration is 1-3 mol/L.
When the micro-etching reaction is carried out, the copper is Cu or Cu (NH)3)4 2+And Cu (NH)3)2 +These three oxidation states exist. The metal copper in the lead frame substrate is oxidized and dissolved in the etching solution to form cuprous ion Cu+While micro-etching Cu in the solution+And generating Cu through a series of reactions under the action of an oxidant and HCl2+，Cu2+And the metal Cu on the substrate is continuously etched away through the cyclic regeneration reaction. Among them, increasing the HCl concentration can accelerate the etching speed, but also can increase the side etching or increase the micro etching depth, or generate chlorine gas in the sodium chlorate supplementing process, which brings harm to human body and environment. Therefore, the concentration of each component is strictly controlled during the treatment process, thereby obtaining a stable microetching rate and effect.
Further preferably, the temperature of the microetching treatment is controlled to be 45-55 ℃.
The temperature of the microetching treatment also has a great influence on the etching rate, and the etching rate is accelerated when the temperature is increased within a certain range, but the microetching depth is difficult to control when the temperature is too high, and the production efficiency is influenced when the temperature is lower.
More preferably, the spraying pressure of the microetching liquid is 1-3 kg/cm3。
Preferably, the electroplating solution in step (3) of the present invention is a silver electroplating solution, wherein the concentration of Ag is 30-50 g/L, the concentration of free KCN is 0-2 g/L, the pH value is 8-9, and the set current density is 5-8 ASD.
Preferably, the working temperature of the silver plating solution is 25-35 ℃.
The silver plating process adopts medium-low speed selective plating, and simultaneously, under the condition of low cyanogen and low temperature plating, the obtained silver plating layer has better compactness, and has the advantages of high hardness, good routing performance and the like. Because the invention carries on the electroplating under the dry film protection, the too fast electroplating speed will influence the coating compactness, and then cause the routing performance to decline. The silver plating solution has extremely low content of free cyanide, reduces chemical damage to equipment, and simultaneously meets the requirements of safety and environmental protection.
Because the selective electroplating is carried out, the micro-etching treatment is only carried out on partial area, and the thickness of the whole lead frame is not required to be thinned, thereby avoiding the problems of warping or strength reduction and the like caused by over-thin lead frame. The microetching and electroplating process of the invention also saves more materials and energy and has controllable cost.
The lead frame prepared by the invention is used for a semiconductor chip packaging structure, the solderability of the electroplated layer is good, the overall thickness of the obtained product is reduced, and the reliability and the qualification rate are better.
Compared with the prior art, the invention has the following advantages:
1. the invention firstly carries out micro-etching treatment on the electroplating area of the frame body to form the concave micro-etching groove, and then carries out electroplating to form the electroplating layer in the micro-etching groove, thereby reducing the thickness of the lead frame and being beneficial to the thin production of the semiconductor package.
2. The invention prevents the electroplated layer from protruding out of the surface of the frame body, can effectively reduce the scratch or abrasion of the electroplated layer, and plays a role in protecting the electroplated layer, thereby better ensuring the weldability and the product percent of pass.
3. The invention carries out micro-etching and electroplating in the local area of the lead frame body, simultaneously leads the thickness of the obtained electroplated layer to be exactly the same as the thickness of the micro-etching groove through the control of the process conditions, keeps the surface of the lead frame smooth, and has simple production process and controllable cost.
Drawings
FIG. 1, comprising FIGS. 1(a) -FIG. (h), illustrates a process for manufacturing a lead frame according to a first embodiment;
fig. 2 is a sectional view showing a lead frame unit produced by the first comparative example;
in the drawings: 1-substrate, 11-upper surface, 12-lower surface, 21, 22-dry film, 3-to-be-electroplated area, 4-micro-etched groove, 5-electroplated layer, 6-to-be-etched area, and 7-etched hole.
Detailed Description
The technical solution of the present invention is further described below with reference to the accompanying drawings. Like parts are designated with like reference numerals throughout the several views. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Portions of the art that are incumbent may not be shown. The starting materials used in the embodiments of the present invention are those commonly used in the art, and the methods used in the examples are those conventional in the art, unless otherwise specified.
It is to be understood that in the following embodiments, when referring to the positional relationship or the number of the constituent elements, terms such as "upper", "lower", and the like are used for illustrative purposes only and are not limiting, and other similar or analogous examples may be used without departing from the scope of the present disclosure.
The substrate of the lead frame is made of conductive material, such as copper, copper alloy, copper molybdenum compound, nickel-iron alloy, pure nickel, etc., and those skilled in the art can select other materials with high reliability and conductive and heat-conductive properties. In this embodiment, copper (content not less than 97%) is used as a substrate material of the lead frame, and the thickness of the substrate is 0.15 mm.
The first embodiment is as follows:
the embodiment one provides a lead frame for a semiconductor package, which is prepared by the following method:
(1) film pasting: preparing a substrate 1 which is degreased, cleaned and dried, as shown in figure 1(a), respectively attaching a layer of dry film 21, 22 on the upper and lower surfaces of the substrate, and as shown in figure 1(b) after attaching the dry films;
(2) micro-etching: aligning the black-and-white negative film with the substrate, and exposing to transfer the image of the portion to be removed onto the dry film 21 on the upper surface 11 of the substrate as shown in fig. 1(c) and 1 (d); then, developing is carried out, the part of the dry film which does not generate photopolymerization reaction is removed, and the region 3 to be electroplated on the upper surface of the lead frame unit is exposed; spraying the substrate by using a microetching solution consisting of copper chloride, sodium chlorate and hydrochloric acid to remove part of the thickness of the substrate in the region 3 to be electroplated and form a concave microetching groove 4; wherein, Cu in the microetching solution2+The concentration is about 138-140 g/L, H+The concentration is 1.8-2.2 mol/L, the temperature of the microetching liquid is 43-45 ℃, and the spraying pressure is set to be 2.2kg/cm3(ii) a The thickness of the formed micro-etching groove 4 is 5 μm;
(3) electroplating: after cleaning and drying, electroplating is carried out in the micro-etching groove 4 area of the lead frame to form a silver electroplating layer 5 shown in figure 1 (e); wherein the pH value of the silver electroplating solution is 9.0 +/-0.2, the silver concentration is 35-60 g/L, the concentration of free potassium cyanide is about 0.1-0.5 g/L, the current density is set to be 5-8 ASD, and the working temperature of the silver electroplating solution is set to be 26-32 ℃; the thickness of the formed silver plating layer is 5 microns, is the same as the thickness of the micro-etching groove, is just flush with the upper surface 11 of the frame body, and the silver plating layer is prevented from protruding out of the surface of the frame, so that the silver plating layer is not easy to scratch, the whole thickness of the lead frame is the thickness of the frame body, and the reduction of the arc height during lead bonding is facilitated;
(4) etching: after the electroplating is finished, cleaning and drying, attaching a layer of dry film 21 on the upper surface 11 of the substrate to cover the electroplated layer 5 on the upper surface of the lead frame, and playing an anti-etching role, as shown in fig. 1 (f); then, exposing and developing, as shown in fig. 1(g), exposing the areas to be etched 6 on the upper and lower surfaces of the substrate, and etching the exposed areas to be etched 6 on the substrate to form etching holes 7;
(4) removing the film: finally, removing the residual dry films on the upper surface and the lower surface of the substrate, and cleaning and drying to obtain the lead frame shown in the figure 1 (h); the microetching is carried out before electroplating, so that the silver electroplated layer sinks to avoid being scratched, and an effective protection effect is achieved, thereby being beneficial to improving the weldability of the lead frame and the qualification rate of packaged products.
In the electroplating process, the current density is controlled within +/-10% of the set current density; the thickness of the lead frame and the plating layer was measured by an EDX scanner, and the overall thickness of the lead frame was 0.15 mm.
Example two:
the lead frame provided in the second embodiment is prepared in the same manner as the first embodiment, and is different from the first embodiment only in that H+The concentration is 3-3.3 mol/L; other parameters are the same as in the first embodiment.
The microetching groove in this example was measured to have a thickness of 8 μm, the plating layer was measured to have a thickness of 8 μm, and the lead frame had an overall thickness of 0.15 mm.
Example three:
the preparation process of the lead frame provided by the third embodiment is the same as that of the first embodiment, and the difference with the first embodiment is only that the temperature of the microetching treatment is 56-58 ℃; other parameters are the same as in the first embodiment.
The microetching groove in this example was measured to have a thickness of 9 μm, the plating layer was measured to have a thickness of 9 μm, and the lead frame had an overall thickness of 0.15 mm.
Example four:
the lead frame prepared in the first embodiment is used for preparing a quad flat non-leaded package (QFN), and the specific process comprises the following steps:
firstly, attaching the ground wafer to an adhesive film, and then cutting the wafer into single and separated chips along a cutting path;
adhering a chip to a chip seat of the lead frame unit by using silver adhesive, and connecting an I/O port of the chip to a silver electroplated layer on the lead frame through a bonding wire to form circuit connection;
then, the chip, the lead frame and the bonding wires are wrapped by epoxy resin compounds in an injection molding mode to protect the functions of the packaging body elements, and the nickel-palladium-gold electroplated layer on the lower surface of the lead frame unit is exposed for subsequent welding with a circuit board;
laser printing on the surface of the package body after molding to be used as a mark, and baking and curing in a 175 ℃ oven;
and finally, carrying out unit cutting, and cutting and separating from the non-functional area to obtain an independent packaging product.
The total thickness of the package in this embodiment is 0.55mm, wherein the height of the wire loop is 0.15 mm.
Comparative example one:
comparative example a lead frame for a semiconductor package was provided, which was manufactured by a method different from that of example a only in that the step (2) was not performed, and the remaining steps and conditions were the same as those of example a.
Comparative example two:
the lead frame prepared in the first comparative example is used for the quad flat non-leaded package, and the processing procedure is the same as that of the fourth example, and is not described again here.
The total thickness of the package in this comparative example was 0.70mm, with a wire loop height of 0.2 mm.
The lead frames in the first embodiment to the third embodiment and the first comparative embodiment are randomly sampled, the solderability test is carried out, and meanwhile, the visual inspection and the metallographic microscope are combined to observe whether the surface defects exist in the plating layer. And placing the lead frame before and after the test under a low power microscope, and performing a solderability test through visual inspection, wherein the lead frame is qualified if the plating layer is 100% continuously covered with the solder paste, and the solderability test is failed if an irregular plating layer, no plating layer or holes are generated. And if the phenomena of plating leakage and gold infiltration are not observed on the surface of the lead frame sample, the lead frame sample is qualified. The test results are shown in table 1.
Table 1 examples one-third and comparative examples one air hole, solderability test and defect detection results
Note: in the table, N is the total amount of actual test samples under the test item, N is the number of qualified test samples, and the yield is N/N × 100%.
In semiconductor packaging processes, the chip may also be mounted by, for example, wire bonding, glue, flip chip or other means to achieve connection of the chip to a lead frame. The lead frame is not only suitable for QFN-like leadless packages, but also suitable for other thinned etching packages.
The specific embodiments described herein are merely illustrative of the spirit of the invention and do not limit the scope of the invention. Various modifications or additions may be made to the described embodiments or alternatives may be employed by those skilled in the art without departing from the spirit or ambit of the invention as defined in the appended claims.
Claims (10)
1. The lead frame for semiconductor packaging comprises a frame body and an electroplated layer and is characterized in that a plurality of micro-etched grooves are formed in the upper surface of the frame body, and the electroplated layer is filled in each micro-etched groove.
2. The lead frame for semiconductor packages according to claim 1, wherein the thickness of the plated layer is the same as the thickness of the micro-etched grooves.
3. The lead frame for semiconductor package according to claim 1, wherein the thickness of the plating layer is 1.5 to 10 μm.
4. The lead frame for semiconductor packages according to claim 1, wherein the plating layer is a nickel palladium gold plating layer or a silver plating layer.
5. The lead frame for semiconductor packages according to claim 1, wherein the frame body is made of a copper or copper alloy material.
6. A method of manufacturing a lead frame for a semiconductor package according to any one of claims 1 to 5, comprising the steps of:
(1) film pasting: respectively attaching a layer of dry film on the upper surface and the lower surface of the substrate;
(2) micro-etching: removing part of the dry film on the upper surface of the substrate through exposure and development to expose a local area of the upper surface of the substrate; then, carrying out micro-etching treatment on the local area to form a micro-etching groove on the substrate;
(3) electroplating: treating the substrate with an electroplating solution to form an electroplated layer in the exposed micro-etching groove;
(4) etching: sticking a dry film again to cover the electroplated layer, and removing partial dry films on the upper surface and the lower surface of the substrate through exposure and development to expose a region to be etched; etching the substrate to obtain a frame body with etching holes;
(5) removing the film: and removing the residual dry films on the upper surface and the lower surface of the lead frame, and cleaning and drying to obtain the lead frame.
7. The method of manufacturing a lead frame for semiconductor packages according to claim 6, wherein the microetching treatment in the step (2) is performed by spraying the upper surface of the substrate with a microetching solution comprising copper chloride, sodium chlorate and hydrochloric acid as main components.
8. The method of claim 7, wherein the microetching Cu is performed by a chemical mechanical polishing method2+The concentration is 110-170 g/L, H+The concentration is 1-3 mol/L.
9. The method of manufacturing a lead frame for semiconductor package according to claim 6 or 7, wherein the microetching treatment is controlled to a temperature of 45 to 55 ℃.
10. The method of claim 7, wherein the spray pressure of the microetching solution is 1-3 kg/cm3。
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| CN114481239A (en) * | 2022-04-06 | 2022-05-13 | 新恒汇电子股份有限公司 | Flexible lead frame preparation process capable of avoiding electroplating of blind holes |
| CN116525495A (en) * | 2023-05-10 | 2023-08-01 | 安徽立德半导体材料有限公司 | Identification code silver plating process and application thereof to lead frame |
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Application publication date: 20210319 |