CN112530895A - Lead frame for packaging, semiconductor packaging structure and packaging method - Google Patents
Lead frame for packaging, semiconductor packaging structure and packaging method Download PDFInfo
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- CN112530895A CN112530895A CN202011521988.8A CN202011521988A CN112530895A CN 112530895 A CN112530895 A CN 112530895A CN 202011521988 A CN202011521988 A CN 202011521988A CN 112530895 A CN112530895 A CN 112530895A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention belongs to the technical field of semiconductor devices, and particularly relates to a lead frame for packaging, a semiconductor packaging structure and a packaging method. The lead frame comprises a plurality of lead frame units, a concave groove is arranged between every two adjacent lead frame units, and the opening direction of the concave groove is vertical upwards. According to the invention, the upper surface of the substrate is treated by the acidic etching solution to remove part of the thickness between the lead frame units to form the concave groove, then the residual metal connecting part of the substrate is removed by the alkaline etching solution after plastic packaging, an ideal etching effect is obtained by controlling the process conditions of alkaline etching, so that the adjacent packaging units are connected by the plastic packaging material without metal connection, the integral test before cutting can be realized, the test flow of a single packaging body is simplified, the product detection efficiency is improved, meanwhile, the abrasion of the metal material of the lead frame to the cutting tool is avoided, the service life of the cutting tool is prolonged, and the production cost is reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a lead frame for packaging, a semiconductor packaging structure and a packaging method.
Background
Semiconductor packaging technology is developed more and more widely, wherein a lead frame is used as a chip carrier of an integrated circuit, and the lead frame is used as an important part for manufacturing semiconductor elements of the integrated circuit, and the chip is connected with an external circuit board through bonding materials in an electric signal mode.
The current semiconductor packaging process mainly comprises the steps of chip film pasting, chip cutting, chip welding, bonding, plastic package forming, laser printing, electroplating, lead frame film pasting, unit cutting and the like. Because metal connection still exists between the lead frame units, the whole packaging structure cannot be tested, and the product is generally required to be detected after a single packaging body is obtained by cutting and separating so as to ensure that the product meets different performance requirements. The detection efficiency of single packaged products one by one is low, the operation is complex, the error is easy to occur, and particularly, under the condition of carrying out multiple visual detections on single products, the labor and time costs are high.
The surface tinning is often required to be carried out on the exposed bottom of the package after the plastic package forming so as to provide better weldability, or the lower surfaces of some lead frames form electroplated layers through pre-electroplating, but the base plate and the exposed electroplated layers of the lead frames are made of metal materials, the hardness is higher, the cutting tool is seriously damaged when the package body is subjected to unit cutting, the service life of the cutting tool is shortened, the production efficiency is reduced, and the cost is increased. Moreover, cutting the metal connecting strips between the lead frame units may also cause problems such as metal residue, which affects the quality of the final packaged product. As shown in fig. 1, a connecting bar between two adjacent package units 210 of the semiconductor package structure in the prior art includes a plastic-sealed resin and a metal frame body, and a part of products also include an electroplated layer, so that the cutter loss during cutting is large, the efficiency is low, the cost is high, and many problems exist.
In order to solve the above problems, a method of pre-molding the lead frame may be adopted. For example, patent application with publication number CN105470232A provides a method for manufacturing a pre-encapsulated lead frame, in which a molding compound is injected after half-etching is performed on the front surface of the middle rib, and then the remaining part of the middle rib is removed by etching along the back surface of the middle rib, and the molding compound is used to replace the metal of the middle rib part, thereby reducing the damage to the cutting tool. In patent application publication No. CN109256367A, a pre-molding lead frame is provided, in which an insulator is embedded between conductive elements through a pre-molding process, the lower surface is etched to expose the lower surface of the insulating layer during semiconductor packaging, and finally, only the insulating layer and the molding layer are cut to obtain separated packaging units. However, in all of these methods, pre-plastic packaging is required for the lead frame, a plastic packaging and flash removal process is added, and film pasting, mask alignment, exposure and development are required for each etching, so that the production cost is increased due to the increase of the process, the production period is prolonged, and the production efficiency is improved. In addition, lateral corrosion is easily caused by etching on the back surface of the connecting part, and since the etching area is small, the conventional etching method is difficult to avoid the phenomenon, so that the problems of delamination of the lead frame unit and the packaging resin and the like can be caused, and the reliability of the packaging body is influenced.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides the lead frame for packaging, the semiconductor packaging structure and the packaging method, and the production process is simple, high-efficiency and low in cost.
The above object of the present invention is achieved by the following technical solutions:
the utility model provides a lead frame for encapsulation, includes a plurality of lead frame units, and the upper surface of each lead frame unit is provided with first plating layer, wherein, is provided with the concave groove between two adjacent lead frame units, and the opening direction of this concave groove is vertical upwards.
Another object of the present invention is to provide a semiconductor package structure, including: the lead frame is characterized in that two adjacent lead frame units in the lead frame are connected through a plastic package part, wherein the upper surfaces of the lead frame units are also provided with semiconductor chips, and the semiconductor chips are connected with the first electroplated layer through leads; the lower surface of the lead frame unit is provided with a second plating layer.
The invention also provides a preparation method of the lead frame, which comprises the following steps: selectively plating the upper surface of the lead frame, and forming a first plating layer in a partial area of the upper surface; etching to expose the side wall of the lead frame unit; and carrying out half-etching treatment on the upper surfaces of the lead frames, removing the thickness of part of the substrate between the adjacent lead frame units, exposing part of the outer walls of the lead frame units and forming the concave grooves.
The existing lead frame is subjected to half-etching treatment on the lower surface to expose a cutting channel which can be used for separating lead frame units, but metal connection still exists between two adjacent lead frame units, for example, the adjacent lead frame units are electrically connected to cause short circuit when the whole packaging structure is directly tested, and the short circuit can be only independently tested after cutting and separation. The invention firstly carries out half etching treatment on the upper surface of the lead frame substrate to form a concave groove with an upward opening between the adjacent lead frame units, namely the upper surface part of the substrate at the connection part of the lead frame units is removed and the lower surface part is remained, thus the lower surface can be etched and the metal connecting part is removed after plastic package, so that the adjacent lead frame units of the packaging structure are connected only through the insulated plastic package part without metal connection, therefore, the metal material part does not need to be cut when the units are cut, the cutter loss is reduced, the cost is saved, the whole packaging structure can be tested without causing short circuit between the pins of the adjacent units, the individual test after cutting is not needed, and the test efficiency is improved.
Preferably, the lead frame of the present invention uses a substrate made of copper or copper alloy material.
Preferably, the half etching is carried out by using an acidic etching solution, and the main components of the etching solution comprise copper chloride, sodium chlorate and hydrochloric acid.
More preferably, in the acidic etching solution, Cu is contained2+The concentration is 110-170 g/L, H+The concentration is 1-3 mol/L.
According to the invention, the upper surface of the metal substrate between the lead frame units is treated by the acidic etching solution containing sodium chlorate, and the carrying amount and overflow amount of HCl can be greatly reduced, the etching factor can be improved and the side etching can be reduced due to the high content of copper ions and weak acidity in the etching solution. The acidic etching solution has good stability, is not easy to decompose, can keep balanced etching rate, has smaller attacking force to a dry film in a low-acid environment, reduces the generation of dry film dissolved substances, improves the effective utilization rate of the etching solution, can reduce the corrosion to equipment, and prolongs the service life of the equipment.
Another object of the present invention is to provide a semiconductor packaging method, including the steps of:
s1, preparing the lead frame of the above embodiment;
s2, welding or adhering the semiconductor chip on the upper surface of the corresponding lead frame unit through bonding materials, and connecting the semiconductor chip to the first electroplated layer through leads;
s3, forming a plastic package part by using a plastic package material through an injection molding process, so that the lead frame units, the semiconductor chip and the leads are covered by the plastic package material and the plastic package material is filled in the concave grooves between the adjacent lead frame units;
s4, after the plastic package part is cured and molded, the lower surface of the lead frame is subjected to film pasting, exposure and development, and then all exposed areas of the lower surface of the lead frame unit are electroplated to form a second electroplated layer;
s5, removing the film to expose the metal connecting parts between the adjacent lead frame units, removing the metal connecting parts of the lead frames through an etching process, and forming cutting channels between the adjacent lead frame units to obtain the semiconductor packaging structure;
and S6, after testing, cutting along the cutting path, and separating to obtain the independent semiconductor packaging unit.
Preferably, the second plating layer is a tin plating layer in step S4.
Preferably, the etching process in step S5 is to treat the exposed connecting portion on the lower surface of the lead frame with an alkaline etching solution.
The invention carries out tin electroplating on the lower surface of the lead frame, not only can provide good solderability, but also has the function of alkali-resistant etching solution, so that the lead frame can be directly treated by the alkali-resistant etching solution after electroplating without being pasted with a dry film or protected by other alkali-resistant materials. The tin plating layer of the lower surface of the lead frame unit plays a role in protecting the substrate of the frame, so that the lead frame unit is not corroded, the metal material part between the adjacent lead frame units is etched, the plastic package material is exposed, and when cutting is carried out, only the plastic package part needs to be cut, the cutter cannot rub with the metal of the frame body and the plating layer, the loss of the cutter is reduced, and the cost is saved. Meanwhile, the etching process is simplified, and the production efficiency is improved.
Preferably, the main component of the alkaline etching solution of the present invention comprises ammonium chloride (NH)4Cl) and ammonia (NH)3·H2O）。
In the alkaline etching reaction, Cu and Cu (NH) are used as copper3)4 2+And Cu (NH)3)2 +These three oxidation states exist. The metal copper in the lead frame substrate is oxidized and dissolved in the etching solution to form cuprous ion Cu+Ammonium chloride and ammonia water in the etching solution and a large amount of oxygen in the air can oxidize the etching solution continuously to form soluble Cu (NH)3)4 2+And can be used as an oxidant to continue reacting with the metal Cu, and the metal copper on the connecting part of the lead frame can be etched away through a series of cyclic reactions.
More preferably, Cu is contained in the alkaline etching solution of the present invention2+The concentration is 150-160 g/L.
Because the cutting channels between the lead frame units are narrow, the area to be etched is small, so that the requirement on the etching process is higher, the metal connecting part is ensured to be completely removed, and the influence of side etching on the quality of the lead frame is avoided. Cu in etching solution2+The increase of the content is beneficial toThe occurrence probability of the side etching is reduced, so that the etching solution with high copper content can obtain ideal etching effect. In the above etching process of the present invention, when Cu is present2+When the concentration is stabilized within the range of 150-160 g/L, the amount of side etching is minimum, and the influence on the lead frame unit can be almost ignored.
More preferably, Cl is contained in the alkaline etching solution of the present invention-The concentration of (b) is 170-320 g/L.
More preferably, the pH value of the alkaline etching solution is 8.0-8.8.
Further preferably, the etching process in step S5 is performed at an operating temperature of 42 to 48 ℃.
In alkaline etching solution, by dissociating ammonia and Cl-The pH value can be adjusted by controlling the content of (A). When the pH value is lower than 8.0, Cl-The content can be obviously increased, and the attack strength to the tin electroplated layer can be increased; if the pH is higher than 8.8, the risk of lateral corrosion is greatly increased, and the etching factor is reduced.
When Cl is present-When the concentration is increased, Cu in the etching solution is inhibited2+Is helpful for quantitatively reducing the occurrence of the lateral erosion. Thus Cl-The function of the buffer is to stabilize the pH value of the etching solution within a narrow range. Generally, the increase of the operating temperature promotes the evaporation of the etching solution, and the evaporation of ammonia gas is also accompanied, so that the pH value is reduced and Cl is caused-The concentration increases. However, high operating temperatures also increase the etching rate, increase the degree of undercutting, and may result in incomplete etching of the connection; if the temperature is too low, the etching rate is too slow, and the reaction time is too long, the occurrence of lateral erosion is also aggravated. Therefore, the present invention needs to control the operation temperature within the range of 42-48 ℃ during the alkaline etching to obtain the minimum amount of side etching. Therefore, the invention needs to pass the operating temperature and Cl in the alkaline etching process-The control of concentration and pH value can reduce side corrosion and obtain ideal etching effect.
Another object of the present invention is also a semiconductor package unit prepared by the above-described packaging method.
Compared with the prior art, the invention has the following advantages:
1. according to the invention, the upper surface part of the substrate at the joint of the adjacent lead frame units is etched and removed, and the metal connecting part is etched and removed after the plastic packaging material is filled, so that the adjacent lead frame units of the packaging structure are connected only through the insulated plastic packaging part, the whole test can be realized before cutting, the test flow of the packaging body is simplified, and the product detection efficiency is improved;
2. the adjacent packaging units of the semiconductor packaging structure are connected only through the plastic packaging material and are not connected with metal, so that the abrasion of the metal material to the cutting tool is avoided, the service life of the cutting tool is prolonged, and the production cost is reduced;
3. according to the invention, after plastic packaging, the metal connecting part is removed by using the alkaline etching solution, and the lateral corrosion is effectively reduced by controlling the conditions of the alkaline etching solution, such as ion concentration, pH value and operating temperature, so that an ideal etching effect is obtained;
4. the invention adopts alkaline etching solution when carrying out half etching treatment after tinning, and the tinning layer can resist alkaline corrosion, thereby playing a certain protection role on the lead frame unit, reducing the steps of film pasting, exposure and development, further simplifying the process flow and improving the production efficiency.
Drawings
FIG. 1 is a diagram illustrating a semiconductor package according to the prior art;
FIG. 2 is a schematic diagram of a lead frame for a package according to the present invention;
FIGS. 3 to 7 are schematic structural views of a packaging process flow in the fourth embodiment;
in the drawings: 100-lead frame, 101-lead frame upper surface, 102-lead frame lower surface, 110-lead frame unit, 111-first electroplated layer, 112-second electroplated layer, 113-side wall, 114-outer wall, 120-metal connecting part, 130-concave groove, 200-semiconductor packaging structure, 201-semiconductor chip, 202-bonding material, 203-lead, 204-plastic sealing part and 210-semiconductor packaging unit.
Detailed Description
The technical solution of the present invention is further described below with reference to the accompanying drawings. Like parts are designated with like reference numerals throughout the several views. For clarity, the various parts of the drawings are not to scale and are merely intended to illustrate relative positions, as may relate to height, thickness, etc., for understanding in connection with the written description of embodiments; portions well known in the art may not be shown. The starting materials used in the embodiments of the present invention are those commonly used in the art, and the methods used in the examples are those conventional in the art, unless otherwise specified.
It is to be understood that in the following embodiments, when referring to the positional relationship or the number of the constituent elements, terms such as "upper", "lower", "first", "second", and the like are used for illustrative purposes only and for distinguishing similar objects, and are not restrictive, and there is no precedence or relative importance, and other similar or analogous examples may be used without departing from the scope of the present disclosure. When an element is referred to as being "mounted on" another element, it can be directly on the other element or intervening media may also be present; when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening media may be present.
The substrate of the lead frame is made of conductive material, such as copper, copper alloy, copper molybdenum compound, nickel-iron alloy, pure nickel, etc., and those skilled in the art can select other materials with high reliability and conductive and heat-conductive properties. In the embodiment of the present invention, copper (content not less than 97%) is used as a substrate material of the lead frame, and the size of the lead frame unit is 12 × 12 mm.
The first embodiment is as follows:
as shown in fig. 2, the lead frame 100 of the present embodiment has an upper surface 101 (front surface) and a lower surface 102 (back surface), and includes a plurality of lead frame units 110 having a first plating layer 111 on the upper surface. The first plating layer 111 in this embodiment is a nickel-palladium-gold plating layer, and other metal materials with good solderability and conductivity may be used instead as required. The adjacent lead frame units have a concave groove 130 therebetween, wherein the concave groove 130 is formed by performing a half-etching process on the upper surface of the substrate, so that the opening direction of the concave groove 130 is vertically upward, and the remaining portion of the lower surface of the substrate remains to form a metal connection portion. The cutting lines a in the drawing are indicated by virtual cutting lines a when the lead frame units 110 are cut and separated.
The thickness of the frame body of this embodiment is 0.24mm, wherein the thickness of the connecting portion is 0.12 mm.
Example two:
the embodiment provides a method for manufacturing a lead frame in the first embodiment, which includes the following steps:
preparing a copper substrate which is degreased, cleaned and dried as a frame body, attaching dry films to the upper surface 101 and the lower surface 102 of the substrate, aligning through a mask, exposing, developing, removing the dry films in a local area of the upper surface of the substrate, and then electroplating nickel-palladium-gold on the substrate to form a first electroplated layer 111 in the local area of the upper surface; the electroplating process is the prior art and is not described herein again;
stripping, cleaning and drying the electroplated substrate, sticking a film again, forming etching holes in the middle of the substrate by a conventional etching process to form a patterned lead frame, exposing the side walls 113 inside the lead frame units 110, and enabling the upper surfaces of the lead frame units 110 to have the same circuit pattern;
etching solution composed of copper chloride, sodium chlorate and hydrochloric acid (wherein, Cu2+The concentration is 135-145 g/L, H+Concentration of 1.8-2.2 mol/L) performing half etching treatment on the upper surface of the substrate between the adjacent lead frame units 110, removing the thickness of the substrate 1/2, exposing partial outer walls 114 of the lead frame units 110, and forming the concave grooves 130 and the metal connecting parts 120; the half thickness of the substrate is removed, so that the etching time for removing the metal connecting part after plastic packaging can be reduced, the metal connecting part is easier to remove, the occurrence of lateral corrosion is reduced, and the problems of warping, breaking and the like of the lead frame due to over-thinness of the connecting part can be avoided;
finally, the lead frame 100 of the first embodiment is obtained by removing the film, cleaning and drying.
Example three:
the present embodiment provides a semiconductor package structure 200, including: the lead frame units 110 are connected with each other through the plastic package part 204, wherein the upper surfaces of the lead frame units 110 are provided with first electroplated layers 111 which are wrapped on the plastic package part 204, and the lower surfaces of the lead frame units 110 are provided with exposed second electroplated layers 112; the lead frame unit upper surface 101 is also mounted with a semiconductor chip 201, the semiconductor chip 201 being connected to the first plated layer 111 of the corresponding lead frame unit 110 by gold wires 203, which is a nickel palladium gold plated layer in this embodiment; the molding part 204 is made of an epoxy resin (EMC) material and covers the semiconductor chip 201, the leads 203, and the lead frame unit 110.
Example four:
the embodiment provides a packaging method of a quad flat non-leaded package (QFN), which comprises the following steps (FIGS. 3-7):
s1, preparing the lead frame 100 of the first or second embodiment, including a plurality of lead frame units 110, with the connecting portions 120 and the concave grooves 130 between adjacent lead frame units 110;
s2, pasting the grinded, filmed and cut semiconductor chip 210 on the chip seat of the lead frame unit 110 by the silver paste 202, then conducting wire bonding, connecting the I/O port on the chip 201 to the first electroplated layer 111 of the lead frame unit 110 by the gold wire 203, and forming circuit connection;
s3, forming a molding part 204 by using EMC material, so that the molding material covers the upper surface 101, the side walls 113, a part of the outer walls 114, the semiconductor chip 201 and the gold wires 203 of the lead frame, but does not cover the lower surface 102 of the lead frame, and the molding material is filled in the concave grooves 130 between the adjacent lead frame units 110 to function as a connection between the adjacent lead frame units 110;
s4, after the plastic package part 204 is cured and molded, the lower surface 102 of the lead frame is subjected to film pasting, exposure and development, and then all exposed areas of the lower surface 102 of the lead frame unit are subjected to tin plating to form a second electroplated layer 112; the second electroplated layer 112 of the present embodiment is a tin-plated layer, has good solderability and alkali corrosion resistance, can not only provide a bare bonding pad for being soldered with a circuit board, but also serve as a protective layer for a subsequent etching process to prevent the copper substrate part of the lead frame unit from being corroded by the etching solution;
s5, removing the film to expose the metal connecting portions 120 between the adjacent lead frame units 110, etching the lower surface 102 of the lead frame with an alkaline etching solution, and removing the metal connecting portions 120 (such as the hatched portions in fig. 5) of the lead frame, thereby forming dicing streets between the adjacent lead frame units 110, as shown by the dotted line a, and obtaining the semiconductor package structure 200; the alkaline etching solution mainly contains NH4Cl and NH3·H2O, wherein Cl-The concentration is 190 g/L, Cu2+The concentration is 155 g/L, the pH value is controlled to be 8.3 +/-0.1, and the operation temperature is 50 ℃;
s6, performing reliability test on the obtained semiconductor package structure 200, and after the test is passed, cutting the semiconductor package structure along the cutting streets between the lead frame units 110 by using a cleaver, and separating to obtain the individual semiconductor package units 210.
Because the connecting portion of metal material has been got rid of after the etching, the cutting knife only needs the cutting plastic envelope resin part, and can not act on metal substrate, reduces the cutting resistance, consequently can alleviate the loss to the cutting knife greatly, prolongs cutting tool's life, improves cutting efficiency simultaneously.
Example five:
the present embodiment provides a semiconductor package unit 210 manufactured by the method of the fourth embodiment, including: a lead frame unit 110, wherein a partial region of the upper surface 101 of the lead frame unit is provided with a nickel palladium gold electroplating layer 111, and the lower surface is provided with a tin electroplating layer 112; a semiconductor chip 201 bonded to the upper surface 101 of the lead frame unit by silver paste 202 and connected to the ni-pd-au plating layer 111 of the lead frame unit by gold wires 203; the mold part 204 covers the upper surface 101, the side wall 113, the semiconductor chip 201, and the leads 203 of the lead frame unit, but does not cover the tin plating layer 112.
The lead frame is not only suitable for QFN-like leadless packages, but also suitable for other etching type packaging products.
The specific embodiments described herein are merely illustrative of the spirit of the invention and do not limit the scope of the invention. Various modifications or additions may be made to the described embodiments or alternatives may be employed by those skilled in the art without departing from the spirit or ambit of the invention as defined in the appended claims.
Claims (10)
1. A lead frame for packaging is characterized by comprising a plurality of lead frame units (110), wherein a first electroplated layer (111) is arranged on the upper surface of each lead frame unit (110), a concave groove (130) is arranged between every two adjacent lead frame units (110), and the opening direction of the concave groove (130) is vertically upward.
2. A semiconductor package structure, comprising:
the lead frame (100) as claimed in claim 1, and two adjacent lead frame units (110) in the lead frame (100) are connected through the plastic sealing part (204), wherein the semiconductor chip (201) is further mounted on the upper surface of the lead frame unit (110), and the semiconductor chip (201) is connected with the first electroplating layer (111) through the lead (203); the lower surface of the lead frame unit (110) is provided with a second plating layer (112).
3. A method of making the lead frame of claim 1, comprising: selectively plating the upper surface (101) of the lead frame, and forming a first plating layer (111) in a partial area of the upper surface (101); etching treatment is carried out to expose the side wall (113) of the lead frame unit (110); the upper surface (101) of the lead frame is subjected to half etching treatment, the thickness of a part of the substrate between the adjacent lead frame units (110) is removed, and a part of the outer wall (114) of each lead frame unit (110) is exposed to form a concave groove (130).
4. A semiconductor packaging method, comprising the steps of:
s1, preparing the lead frame (100) of claim 1;
s2, welding or adhering the semiconductor chip (201) on the upper surface (101) of the corresponding lead frame unit (110) through the bonding material (202), and connecting the semiconductor chip to the first electroplating layer (111) through the lead (203);
s3, forming a plastic package part (204) by using a plastic package material through an injection molding process, enabling the plastic package material to cover the lead frame units (110), the semiconductor chip (201) and the leads (203), and filling the concave grooves (130) between the adjacent lead frame units (110);
s4, after the plastic package part (204) is solidified and formed, the lower surface (102) of the lead frame is subjected to film pasting, exposure and development, and then all exposed areas of the lower surface (102) of the lead frame unit are electroplated to form a second electroplated layer (112);
s5, removing the film to expose the metal connecting parts (120) between the adjacent lead frame units (110), removing the metal connecting parts (120) of the lead frames through an etching process, and forming cutting paths between the adjacent lead frame units (110) to obtain the semiconductor packaging structure (200);
and S6, after testing, cutting along the cutting path, and separating to obtain the independent semiconductor packaging unit (210).
5. The semiconductor packaging method according to claim 4, wherein the second plating layer is a tin plating layer in step S4.
6. The semiconductor packaging method according to claim 4, wherein the etching process in step S5 is to treat the exposed connecting portion on the lower surface of the lead frame with an alkaline etching solution.
7. The semiconductor packaging method according to claim 6, wherein the pH of the alkaline etchant is 8.0 to 8.8.
8. The semiconductor packaging method according to claim 6, wherein the main components of the alkaline etching solution include ammonium chloride and ammonia water.
9. The semiconductor packaging method according to claim 4, wherein the etching process in step S5 is performed at a temperature controlled within a range of 42-48 ℃.
10. A semiconductor package unit prepared by the packaging method as claimed in any one of claims 4 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011521988.8A CN112530895A (en) | 2020-12-22 | 2020-12-22 | Lead frame for packaging, semiconductor packaging structure and packaging method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011521988.8A CN112530895A (en) | 2020-12-22 | 2020-12-22 | Lead frame for packaging, semiconductor packaging structure and packaging method |
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| CN112530895A true CN112530895A (en) | 2021-03-19 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116632123A (en) * | 2023-04-28 | 2023-08-22 | 崇辉半导体(江门)有限公司 | Manufacturing method of EMC bracket |
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| US20030203539A1 (en) * | 2002-04-29 | 2003-10-30 | Shafidul Islam | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
| CN1735963A (en) * | 2003-01-15 | 2006-02-15 | 先进互联技术有限公司 | Semiconductor packaging with partially patterned lead frames and its making methods |
| US20060033184A1 (en) * | 2004-08-11 | 2006-02-16 | Park Hyung J | Process and lead frame for making leadless semiconductor packages |
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